StrongIRFET
IRFH7004PbF
HEXFET® Power MOSFET
Applications
l
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Brushed Motor drive applications
BLDC Motor drive applications
Battery powered circuits
Half-bridge and full-bridge topologies
Synchronous rectifier applications
Resonant mode power supplies
OR-ing and redundant power switches
DC/DC and AC/DC converters
DC/AC Inverters
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
40V
1.1mΩ
1.4mΩ
259A
ID (Package Limited)
100A
c
Benefits
l
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Base Part Number
Package Type
IRFH7004PBF
PQFN 5mm x 6mm
PQFN 5X6 mm
Standard Pack
Form
Quantity
Tape and Reel
4000
6.0
IRFH7004TRPBF
300
250
4.0
T J = 125°C
2.0
Limited By Package
200
150
100
50
T J = 25°C
0.0
0
4
6
8
10
12
14
16
18
20
25
Fig 1. Typical On-Resistance vs. Gate Voltage
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50
75
100
125
150
T C , Case Temperature (°C)
VGS, Gate -to -Source Voltage (V)
1
Orderable Part Number
ID = 100A
ID, Drain Current (A)
l
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
Fully Characterized Capacitance and Avalanche
SOA
Enhanced body diode dV/dt and dI/dt Capability
RoHS Compliant containing no Lead, no Bromide,
and no Halogen
RDS(on), Drain-to -Source On Resistance (m Ω)
l
Fig 2. Maximum Drain Current vs. Case Temperature
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IRFH7004PbF
Absolute Maximum Ratings
Symbol
Parameter
Max.
c
c
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
259
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
164
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
100
IDM
Pulsed Drain Current
1247
d
Units
A
Maximum Power Dissipation
156
W
Linear Derating Factor
1.3
W/°C
VGS
Gate-to-Source Voltage
± 20
V
TJ
Operating Junction and
-55 to + 150
TSTG
Storage Temperature Range
PD @TC = 25°C
Avalanche Characteristics
Single Pulse Avalanche Energy
EAS (Thermally limited)
e
Single Pulse Avalanche Energy l
Avalanche Currentd
Repetitive Avalanche Energy d
EAS (Thermally limited)
IAR
EAR
°C
mJ
191
479
A
See Fig. 14, 15, 22a, 22b
mJ
Thermal Resistance
Symbol
RθJC (Bottom)
RθJC (Top)
k
Junction-to-Case k
Parameter
Junction-to-Case
j
Junction-to-Ambient j
Junction-to-Ambient
RθJA
RθJA (<10s)
Typ.
Max.
0.5
0.8
–––
15
–––
34
–––
21
Units
°C/W
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Units
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
40
–––
–––
V
ΔV(BR)DSS/ΔTJ
Breakdown Voltage Temp. Coefficient
–––
0.033
–––
V/°C
VGS = 0V, ID = 250μA
RDS(on)
Static Drain-to-Source On-Resistance
–––
1.1
1.4
mΩ
VGS = 10V, ID = 100A
–––
1.7
–––
mΩ
VGS = 6.0V, ID = 50A
Reference to 25°C, ID = 1.0mA
g
g
VGS(th)
Gate Threshold Voltage
2.2
3.0
3.9
V
VDS = VGS, ID = 150μA
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
μA
VDS = 40V, VGS = 0V
–––
–––
150
IGSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
VGS = 20V
Gate-to-Source Reverse Leakage
–––
–––
-100
Internal Gate Resistance
–––
2.4
–––
RG
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package is limited to 100A by production test
capability. Note that current limitations arising from heating of the
device leads may occur with some lead mounting arrangements.
(Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.038mH
RG = 50Ω, IAS = 100A, VGS =10V.
ISD ≤ 100A, di/dt ≤ 1366A/μs, VDD ≤ V(BR)DSS, TJ ≤ 150°C.
2
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d
VDS = 40V, VGS = 0V, TJ = 125°C
VGS = -20V
Ω
Pulse width ≤ 400μs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1 inch square 2 oz copper pad on 1.5 x 1.5 in. board of
FR-4 material.
Rθ is measured at TJ approximately 90°C.
Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50Ω, IAS = 31A,
VGS =10V.
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IRFH7004PbF
Dynamic @ TJ = 25°C (unless otherwise specified)
Min.
Typ.
Max.
Units
gfs
Symbol
Forward Transconductance
Parameter
117
–––
–––
S
VDS = 10V, ID = 100A
Conditions
Qg
Total Gate Charge
–––
129
194
nC
ID = 100A
Qgs
Gate-to-Source Charge
–––
34
–––
VDS =20V
Qgd
Gate-to-Drain ("Miller") Charge
–––
40
–––
VGS = 10V
g
Qsync
Total Gate Charge Sync. (Qg - Qgd)
–––
169
–––
td(on)
Turn-On Delay Time
–––
15
–––
tr
Rise Time
–––
51
–––
ID = 30A
td(off)
Turn-Off Delay Time
–––
73
–––
RG = 2.7Ω
tf
Fall Time
–––
49
–––
Ciss
Input Capacitance
–––
6419
–––
Coss
Output Capacitance
–––
952
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
–––
656
–––
ƒ = 1.0 MHz
Coss eff. (ER)
Effective Output Capacitance (Energy Related)
–––
1161
–––
VGS = 0V, VDS = 0V to 32V
Coss eff. (TR)
Effective Output Capacitance (Time Related)
–––
1305
–––
VGS = 0V, VDS
Min.
Typ.
Max.
–––
–––
100
ns
VDD = 20V
VGS = 10V
pF
g
VGS = 0V
i
= 0V to 32V h
Diode Characteristics
Symbol
IS
Parameter
Continuous Source Current
c
Units
A
Pulsed Source Current
(Body Diode)
d
–––
–––
1247
A
Diode Forward Voltage
–––
0.95
1.3
V
dv/dt
Peak Diode Recovery
–––
2.5
–––
V/ns
trr
Reverse Recovery Time
–––
35
–––
ns
–––
35
–––
–––
26
–––
–––
27
–––
–––
1.5
–––
f
Reverse Recovery Charge
IRRM
Reverse Recovery Current
3
integral reverse
G
S
p-n junction diode.
VSD
Qrr
D
showing the
(Body Diode)
ISM
Conditions
MOSFET symbol
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nC
TJ = 25°C, IS = 100A, VGS = 0V
g
TJ = 175°C, IS = 100A, VDS = 40V
TJ = 25°C
VR = 34V,
TJ = 125°C
IF = 100A
TJ = 25°C
di/dt = 100A/μs
g
TJ = 125°C
A
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TJ = 25°C
March 17, 2015
IRFH7004PbF
10000
10000
VGS
15V
10V
8.0V
7.0V
6.0V
5.0V
4.5V
4.25V
1000
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
1000
100
10
BOTTOM
100
4.25V
10
≤60μs PULSE WIDTH
≤60μs PULSE WIDTH
4.25V
Tj = 150°C
Tj = 25°C
1
1
0.1
1
10
0.1
100
Fig 3. Typical Output Characteristics
100
1.8
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
Fig 4. Typical Output Characteristics
10000
1000
T J = 150°C
100
T J = 25°C
10
VDS = 10V
≤60μs PULSE WIDTH
1.0
ID = 100A
VGS = 10V
1.6
1.4
1.2
1.0
0.8
0.6
3
4
5
6
7
8
9
-60 -40 -20 0
Fig 6. Normalized On-Resistance vs. Temperature
Fig 5. Typical Transfer Characteristics
100000
14.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
VGS, Gate-to-Source Voltage (V)
C rss = C gd
C oss = C ds + C gd
10000
Ciss
20 40 60 80 100 120 140 160
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
C, Capacitance (pF)
1
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Coss
Crss
1000
ID= 100A
12.0
VDS= 32V
VDS= 20V
10.0
8.0
6.0
4.0
2.0
0.0
100
0.1
1
10
0
100
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
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20
40
60
80
100 120 140 160
QG, Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
4
VGS
15V
10V
8.0V
7.0V
6.0V
5.0V
4.5V
4.25V
Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage
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IRFH7004PbF
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
10000
1000
T J = 150°C
100
T J = 25°C
10
VGS = 0V
0.5
1.0
1.5
2.0
1000
100μsec
100
10msec
1
DC
0.1
2.5
1
10
100
VDS, Drain-to-Source Voltage (V)
VSD, Source-to-Drain Voltage (V)
Fig 10. Maximum Safe Operating Area
1.0
49
VDS= 0V to 32V
Id = 1.0mA
0.8
47
46
Energy (μJ)
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Tc = 25°C
Tj = 150°C
Single Pulse
0.1
Fig 9. Typical Source-Drain Diode
Forward Voltage
48
1msec
Limited by
package
10
0.01
1.0
0.0
OPERATION IN THIS AREA
LIMITED BY R DS(on)
45
44
0.6
0.4
43
42
0.2
41
0.0
40
-60 -40 -20 0
0
20 40 60 80 100 120 140 160
T J , Temperature ( °C )
10
15
20
25
30
35
40
VDS, Drain-to-Source Voltage (V)
Fig 11. Drain-to-Source Breakdown Voltage
RDS(on), Drain-to -Source On Resistance ( mΩ)
5
Fig 12. Typical COSS Stored Energy
40
VGS = 5.0V
VGS = 6.0V
VGS = 7.0V
VGS = 8.0V
30
VGS =10V
20
10
0
0
200
400
600
800
1000 1200 1400
ID, Drain Current (A)
Fig 13. Typical On-Resistance vs. Drain Current
5
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IRFH7004PbF
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 125°C and
Tstart =25°C (Single Pulse)
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 125°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
140
120
EAR , Avalanche Energy (mJ)
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 100A
100
80
60
40
20
0
25
50
75
100
125
Starting T J , Junction Temperature (°C)
150
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 16. Maximum Avalanche Energy vs. Temperature
6
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IRFH7004PbF
10
IF = 60A
V R = 34V
8
TJ = 25°C
TJ = 125°C
3.0
IRRM (A)
VGS(th) , Gate threshold Voltage (V)
4.0
ID = 150μA
ID = 1.0mA
2.0
6
4
ID = 1.0A
2
1.0
0
-75 -50 -25
0
25
50
75 100 125 150
0
200
T J , Temperature ( °C )
600
800
1000
diF /dt (A/μs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig 17. Threshold Voltage vs. Temperature
10
300
IF = 100A
V R = 34V
8
TJ = 25°C
TJ = 125°C
6
QRR (nC)
IRRM (A)
400
4
250
IF = 60A
V R = 34V
200
TJ = 25°C
TJ = 125°C
150
100
2
50
0
0
0
200
400
600
800
1000
0
200
diF /dt (A/μs)
400
600
800
1000
diF /dt (A/μs)
Fig. 19 - Typical Recovery Current vs. dif/dt
Fig. 20 - Typical Stored Charge vs. dif/dt
250
IF = 100A
V R = 34V
QRR (nC)
200
TJ = 25°C
TJ = 125°C
150
100
50
0
0
200
400
600
800
1000
diF /dt (A/μs)
Fig. 21 - Typical Stored Charge vs. dif/dt
7
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IRFH7004PbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
20V
VGS
+
V
- DD
IAS
tp
A
0.01Ω
I AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test
Circuit
R
D
VDS
V GS
VDS
90%
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
tf
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
DUT
0
1K
s
VCC
Vgs(th)
Qgs1 Qgs2
Fig 24a. Gate Charge Test Circuit
8
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Qgd
Qgodr
Fig 24b. Gate Charge Waveform
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IRFH7004PbF
PQFN 5x6 Outline "B" Package Details
For more information on board mounting, including footprint and stencil recommendation, please refer to application note AN-1136:
http://www.irf.com/technical-info/appnotes/an-1136.pdf
For more information on package inspection techniques, please refer to application note AN-1154:
http://www.irf.com/technical-info/appnotes/an-1154.pdf
PQFN 5x6 Part Marking
INTERNATIONAL
RECTIFIER LOGO
DATE CODE
ASSEMBLY
SITE CODE
(Per SCOP 200-002)
PIN 1
IDENTIFIER
XXXX
XYWWX
XXXXX
PART NUMBER
(“4 or 5 digits”)
MARKING CODE
(Per Marking Spec)
LOT CODE
(Eng Mode - Min last 4 digits of EATI#)
(Prod Mode - 4 digits of SPN code)
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
9
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IRFH7004PbF
PQFN 5x6 Tape and Reel
REEL DIMENSIONS
TAPE DIMENSIONS
CODE
Ao
Dimension design to accommodate the component width
Bo
Dimension design to accommodate the component lenght
Ko
Dimension design to accommodate the component thickness
Overall width of the carrier tape
Pitch between s ucces sive cavity centers
W
P1
DES CRIPTION
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Note: All dimens ion are nominal
Package
T ype
Reel
Diameter
(Inch)
QTY
Reel
Width
W1
(mm)
Ao
(mm)
Bo
(mm)
Ko
(mm)
P1
(mm)
W
(mm)
Pin 1
Quadrant
5 X 6 PQFN
13
4000
12.4
6.300
5.300
1.20
8.00
12
Q1
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
10
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IRFH7004PbF
†
Qualification information
Industrial
Qualification level
Moisture Sensitivity Level
(per JE DE C JE S D47F
PQFN 5mm x 6mm
RoHS compliant
††
guidelines )
MS L1
††
(per JE DE C J-S T D-020D )
Yes
Qualification standards can be found at International Rectifiers web site: http://www.irf.com/product-info/reliability/
Applicable version of JEDEC standard at the time of product release.
Revision History
Date
Comment
• Updated EAS (L =1mH) = 479mJ on page 2
2/19/2015
• Updated note 10 “Limited by TJmax , starting TJ = 25°C, L = 1mH, RG = 50Ω, IAS = 31A, VGS =10V”. on page 2
3/17/2015 • Updated package outline and tape and reel on pages 9 and 10.
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
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