PD - 95550A
IRFR4105PbF
IRFU4105PbF
Ultra Low On-Resistance
l Surface Mount (IRFR4105)
l Straight Lead (IRFU4105)
l Fast Switching
l Fully Avalanche Rated
l Lead-Free
Description
HEXFET® Power MOSFET
l
D
VDSS = 55V
RDS(on) = 0.045Ω
G
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient device for use in a wide
variety of applications.
The D-PAK is designed for surface mounting using
vapor phase, infrared, or wave soldering techniques.
The straight lead version (IRFU series) is for throughhole mounting applications. Power dissipation levels
up to 1.5 watts are possible in typical surface mount
applications.
ID = 27A
S
D-PAK
TO-252AA
I-PAK
TO-251AA
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
Units
27
19
100
68
0.45
± 20
65
16
6.8
5.0
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
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Junction-to-Case
Junction-to-Ambient (PCB mount) **
Junction-to-Ambient
Typ.
Max.
Units
–––
–––
–––
2.2
50
110
°C/W
1
1/7/05
IRFR/U4105PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
IGSS
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
LD
Internal Drain Inductance
LS
Internal Source Inductance
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V(BR)DSS
∆V(BR)DSS/∆TJ
Min. Typ. Max. Units
Conditions
55
––– –––
V
VGS = 0V, ID = 250µA
––– 0.052 ––– V/°C Reference to 25°C, I D = 1mA
––– ––– 0.045
VGS = 10V, ID = 16A
2.0
––– 4.0
V
VDS = V GS, ID = 250µA
6.5
––– –––
S
VDS = 25V, ID = 16A
––– ––– 25
VDS = 55V, VGS = 0V
µA
––– ––– 250
VDS = 44V, VGS = 0V, TJ = 150°C
––– ––– 100
VGS = 20V
nA
––– ––– -100
VGS = -20V
––– ––– 34
ID = 16A
––– ––– 6.8
nC
VDS = 44V
––– ––– 14
VGS = 10V, See Fig. 6 and 13
–––
7.0 –––
VDD = 28V
–––
49 –––
ID = 16A
ns
–––
31 –––
RG = 18Ω
–––
40 –––
RD = 1.8Ω, See Fig. 10
Between lead,
–––
4.5
–––
nH
6mm (0.25in.)
G
from package
––– 7.5 –––
and center of die contact
––– 700 –––
VGS = 0V
––– 240 –––
pF
VDS = 25V
––– 100 –––
ƒ = 1.0MHz, See Fig. 5
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 27
showing the
A
G
integral reverse
––– ––– 100
p-n junction diode.
S
––– ––– 1.6
V
TJ = 25°C, IS = 16A, VGS = 0V
––– 57
86
ns
TJ = 25°C, IF = 16A
––– 130 200
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 410µH
R G = 25Ω, IAS = 16A. (See Figure 12)
Calculated continuous current based on maximum allowable junction
ISD ≤ 16A, di/dt ≤ 420A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
temperature; Package limitation current = 20A
This is applied for I-PAK, Ls of D-PAK is measured between lead and
center of die contact
Uses IRFZ34N data and test conditions
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
2
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IRFR/U4105PbF
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
I , Drain-to-Source Current (A)
D
I , Drain-to-Source Current (A)
D
100
10
4.5V
1
20µs PULSE WIDTH
TC = 25°C
0.1
0.1
1
10
100
10
A
100
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
10
V DS = 25V
20µs PULSE WIDTH
6
7
8
9
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
A
100
Fig 2. Typical Output Characteristics
2.4
5
1
VDS , Drain-to-Source Voltage (V)
100
1
20µs PULSE WIDTH
TC = 175°C
0.1
0.1
Fig 1. Typical Output Characteristics
ction
4.5V
1
VDS , Drain-to-Source Voltage (V)
4
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
TOP
10
A
I D = 26A
2.0
1.6
1.2
0.8
0.4
VGS = 10V
0.0
-60 -40 -20
0
20
40
60
A
80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFR/U4105PbF
20
1200
C, Capacitance (pF)
1000
V GS , Gate-to-Source Voltage (V)
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
Ciss C oss = Cds + C gd
800
Coss
600
400
Crss
200
0
A
1
10
I D = 16A
V DS = 44V
V DS = 28V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
100
0
VDS , Drain-to-Source Voltage (V)
30
A
40
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
20
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
TJ = 175°C
TJ = 25°C
10
100
10µs
100µs
10
1ms
VGS = 0V
1
0.4
0.8
1.2
1.6
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10
A
2.0
TC = 25°C
TJ = 175°C
Single Pulse
1
1
A
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFR/U4105PbF
30
VGS
25
D.U.T.
RG
ID , Drain Current (A)
RD
V DS
LIMITED BY PACKAGE
+
-VDD
20
5.0V
15
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
10
Fig 10a. Switching Time Test Circuit
VDS
5
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
0.01
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
15V
L
VDS
D.U.T
RG
IAS
10V
tp
DRIVER
+
V
- DD
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
E AS , Single Pulse Avalanche Energy (mJ)
IRFR/U4105PbF
140
TOP
120
BOTTOM
ID
6.5A
11A
16A
100
80
60
40
20
0
VDD = 25V
25
V(BR)DSS
50
A
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
tp
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
5.0 V
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRFR/U4105PbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
•
•
•
•
RG
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
Period
P.W.
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRFR/U4105PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRF R120
WITH AS SEMB LY
LOT CODE 1234
ASSEMBLED ON WW 16, 1999
IN THE ASS EMBLY LINE "A"
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
Note: "P" in ass embly line position
indicates "Lead-Free"
IRFU120
12
916A
34
ASS EMBLY
LOT CODE
DATE CODE
YEAR 9 = 1999
WEEK 16
LINE A
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
12
ASS EMBLY
LOT CODE
8
34
DATE CODE
P = DESIGNAT ES LEAD-F REE
PRODUCT (OPTIONAL)
YEAR 9 = 1999
WEEK 16
A = ASS EMBLY SIT E CODE
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IRFR/U4105PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRF U120
WIT H AS SEMBLY
LOT CODE 5678
AS SEMBLE D ON WW 19, 1999
IN T HE ASSEMBLY LINE "A"
PART NUMBER
INT E RNAT IONAL
RECT IFIER
LOGO
IRFU120
919A
56
78
ASSE MBLY
LOT CODE
Note: "P" in as s embly line
pos ition indicates "Lead-F ree"
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
OR
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRF U120
56
ASS EMBLY
LOT CODE
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78
DAT E CODE
P = DESIGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 9 = 1999
WEEK 19
A = ASS EMBLY SIT E CODE
9
IRFR/U4105PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.1/05
10
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/