PD - 95571
Advanced Process Technology
Surface Mount (IRFZ34NS)
Low-profile through-hole (IRFZ34NL)
175°C Operating Temperature
Fast Switching
Fully Avalanche Rated
Lead-Free
l
l
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IRFZ34NSPbF
IRFZ34NLPbF
HEXFET® Power MOSFET
D
RDS(on) = 0.040Ω
G
ID = 29A
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible onresistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRFZ34NL) is available for lowprofile applications.
S
D 2 Pak
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TA = 25°C
PD @TC = 25°C
V GS
EAS
IAR
EAR
dv/dt
TJ
TSTG
VDSS = 55V
TO-262
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
29
20
100
3.8
68
0.45
± 20
130
16
5.6
5.0
-55 to + 175
Units
A
W
W
W/°C
V
mJ
A
mJ
V/ns
300 (1.6mm from case )
°C
Thermal Resistance
Parameter
RθJC
RθJA
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Junction-to-Case
Junction-to-Ambient (PCB mount) **
Typ.
Max.
Units
2.2
40
°C/W
1
07/19/04
IRFZ34NS/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
RDS(ON)
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
55
2.0
6.5
LS
Internal Source Inductance
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V(BR)DSS
IDSS
IGSS
Drain-to-Source Leakage Current
Typ.
0.052
7.0
49
31
40
Max. Units
Conditions
V
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
0.040
Ω
VGS = 10V, I D = 16A
4.0
V
VDS = V GS, ID = 250µA
S
VDS = 25V, I D = 16A
25
VDS = 55V, V GS = 0V
µA
250
VDS = 44V, VGS = 0V, TJ = 150°C
100
VGS = 20V
nA
-100
VGS = -20V
34
ID = 16A
6.8
nC VDS = 44V
14
VGS = 10V, See Fig. 6 and 13
VDD = 28V
ID = 16A
ns
RG = 18Ω
RD = 1.8Ω, See Fig. 10
Between lead,
nH
7.5
and center of die contact
700
VGS = 0V
240
pF
VDS = 25V
100
= 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
I SM
V SD
t rr
Q rr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
29
100
57
130
1.6
86
200
A
V
ns
nC
Conditions
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
TJ = 25°C, IS = 16A, VGS = 0V
TJ = 25°C, IF = 16A
di/dt = 100A/µs
D
S
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 610µH
RG = 25Ω, IAS = 16A. (See Figure 12)
ISD ≤ 16 A, di/dt ≤ 420A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Uses IRFZ34N data and test conditions
** When mounted on 1" square PCB (FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
2
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IRFZ34NS/LPbF
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
100
10
4.5V
20µs PULSE WIDTH
TCJ == 25°C
T
25°C
1
0.1
1
10
A
100
10
4.5V
100
2.4
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
10
V DS = 25V
20µs PULSE WIDTH
6
7
8
9
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
A
100
Fig 2. Typical Output Characteristics
100
5
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1
20µs PULSE WIDTH
TTCJ =
= 175°C
175°C
1
0.1
VDS , Drain-to-Source Voltage (V)
4
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
I , Drain-to-Source Current (A)
D
I , Drain-to-Source Current (A)
D
TOP
10
A
I D = 26A
2.0
1.6
1.2
0.8
0.4
VGS = 10V
0.0
-60 -40 -20
0
20
40
60
A
80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFZ34NS/LPbF
1200
V GS , Gate-to-Source Voltage (V)
1000
C, Capacitance (pF)
20
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
Ciss C oss = Cds + C gd
V DS = 44V
V DS = 28V
16
800
Coss
12
600
400
Crss
200
0
A
1
I D = 16A
10
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
100
0
VDS , Drain-to-Source Voltage (V)
30
A
40
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
20
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
TJ = 175°C
TJ = 25°C
10
100
10µs
100µs
10
1ms
VGS = 0V
1
0.4
0.8
1.2
1.6
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10
A
2.0
TC = 25°C
TJ = 175°C
Single Pulse
1
1
10ms
A
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFZ34NS/LPbF
RD
V DS
VGS
30
D.U.T.
RG
+
- V DD
I D , Drain Current (A)
25
10 V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
20
15
Fig 10a. Switching Time Test Circuit
10
VDS
90%
5
0
25
50
75
100
125
150
10%
VGS
175
TC , Case Temperature ( °C)
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Fig 9. Maximum Drain Current Vs.
Case Temperature
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
0.01
0.01
0.00001
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t1 / t 2
2. Peak TJ =P DM x ZthJC + TC
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
L
VDS
D.U.T.
RG
+
-
VDD
IAS
10 V
tp
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
EAS , Single Pulse Avalanche Energy (mJ)
IRFZ34NS/LPbF
250
TOP
BOTTOM
200
ID
6.5A
11A
16A
150
100
50
0
VDD = 25V
25
50
A
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
tp
VDD
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
VDS
IAS
Current Regulator
Same Type as D.U.T.
Fig 12b. Unclamped Inductive Waveforms
50KΩ
12V
.2µF
.3µF
QG
10 V
D.U.T.
QGS
+
V
- DS
QGD
VGS
VG
3mA
IG
Charge
Fig 13a. Basic Gate Charge Waveform
6
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRFZ34NS/LPbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
+
-
-
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
V DD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
* VGS
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ISD
= 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
7
IRFZ34NS/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T HIS IS AN IRF530S WIT H
LOT CODE 8024
AS S EMB L ED ON WW 02, 2000
IN T HE AS S E MB LY L INE "L"
INT E RNAT IONAL
RECT IFIE R
L OGO
Note: "P" in as sembly line
pos ition indicates "Lead-Free"
PART NUMB ER
F 530S
AS S E MB LY
LOT CODE
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
OR
INT ERNAT IONAL
RE CT IF IER
LOGO
ASS E MBLY
LOT CODE
8
PART NUMBE R
F 530S
DAT E CODE
P = DE S IGNAT ES LEAD-F RE E
PRODUCT (OPT IONAL)
YE AR 0 = 2000
WEE K 02
A = AS S EMBLY SIT E CODE
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IRFZ34NS/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE : THIS IS AN IRL3103L
LOT CODE 1789
AS S EMBLE D ON WW 19, 1997
IN T HE AS S EMBLY LINE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT ERNATIONAL
RE CT IF IE R
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YE AR 7 = 1997
WE EK 19
LINE C
OR
INTE RNAT IONAL
RECTIFIER
LOGO
AS S EMBLY
LOT CODE
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PART NUMBE R
DATE CODE
P = DES IGNAT ES LEAD-F REE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S IT E CODE
9
IRFZ34NS/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
3
4
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/04
10
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/