StrongIRFET
IRFR7446PbF
Applications
l Brushed Motor drive applications
l BLDC Motor drive applications
l PWM Inverterized topologies
l Battery powered circuits
l Half-bridge and full-bridge topologies
l Synchronous rectifier applications
l Resonant mode power supplies
l OR-ing and redundant power switches
l DC/DC and AC/DC converters
HEXFET® Power MOSFET
D
G
S
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
40V
3.0mΩ
3.9mΩ
120A
ID (Package Limited)
56A
c
D
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dv/dt and dI/dt Capability
l Lead-Free
S
G
D-Pak
IRFR7446TRPbF
G
D
S
Gate
Drain
Source
Ordering Information
Orderable part number
Package Type
D-PAK
D-PAK
IRFR7446PBF
IRFR7446TRPBF
LIMITED BY PACKAGE
ID = 56A
100
8
6
TJ = 125°C
4
80
60
40
20
TJ = 25°C
0
2
4
8
12
16
20
VGS, Gate-to-Source Voltage (V)
Fig 1. Typical On-Resistance vs. Gate Voltage
1
Complete Part Number
120
10
ID, Drain Current (A)
( Ω)
RDS (on), Drain-to -Source On Resistance m
IRFR7446PBF
IRFR7446TRPBF
Standard Pack
Form
Quantity
Tube/Bulk
75
Tape and Reel
2000
www.irf.com © 2015 International Rectifier
25
50
75
100
125
150
175
TC, Case Temperature (°C)
Fig 2. Maximum Drain Current vs. Case Temperature
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IRFR7446PbF
Absolute Maximum Ratings
Symbol
Max.
120
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
56
IDM
Pulsed Drain Current
520
PD @TC = 25°C
Maximum Power Dissipation
d
W
W/°C
V
Linear Derating Factor
VGS
Gate-to-Source Voltage
± 20
TJ
Operating Junction and
TSTG
Storage Temperature Range
-55 to + 175
EAS (Thermally limited)
IAR
EAR
°C
300
Soldering Temperature, for 10 seconds (1.6mm from case)
EAS (Thermally limited)
A
98
0.66
Avalanche Characteristics
Units
c
84c
ID @ TC = 25°C
e
Single Pulse Avalanche Energy l
Avalanche Current d
Repetitive Avalanche Energy d
125
Single Pulse Avalanche Energy
mJ
251
A
See Fig 15,16, 23a, 23b
mJ
Thermal Resistance
Symbol
Parameter
Junction-to-Case
RθJC
k
RθJA
Junction-to-Ambient (PCB Mount)
RθJA
Junction-to-Ambient
k
j
Typ.
Max.
–––
1.52
–––
50
–––
110
Units
°C/W
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Units
V
Conditions
VGS = 0V, ID = 250μA
d
V(BR)DSS
Drain-to-Source Breakdown Voltage
40
–––
–––
ΔV(BR)DSS/ΔTJ
Breakdown Voltage Temp. Coefficient
–––
26
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
3.0
3.9
mΩ
VGS = 10V, ID = 56A
4.4
–––
mΩ
VGS = 6.0V, ID
mV/°C Reference to 25°C, ID = 1mA
g
= 28A g
VGS(th)
Gate Threshold Voltage
2.2
3.0
3.9
V
VDS = VGS, ID = 100μA
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
μA
VDS = 40V, VGS = 0V
–––
–––
150
IGSS
Gate-to-Source Forward Leakage
–––
–––
100
nA
VGS = 20V
Gate-to-Source Reverse Leakage
–––
–––
-100
Internal Gate Resistance
–––
1.5
–––
RG
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 56A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.08mH
RG = 50Ω, IAS = 56A, VGS =10V.
ISD ≤ 100A, di/dt ≤ 1306A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
2
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VDS = 40V, VGS = 0V, TJ = 125°C
VGS = -20V
Ω
Pulse width ≤ 400μs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS .
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
Limited by TJmax starting TJ = 25°C, L= 1mH, RG = 50Ω, IAS = 22A, VGS =10V.
*
LD and LS are Internal Drain Inductance and Internal Source Inductance
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IRFR7446PbF
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
Min. Typ. Max. Units
170
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
65
18
22
43
9.8
13
32
20
3150
480
330
570
680
–––
130
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
Conditions
VDS = 10V, ID = 56A
ID =56A
VDS =20V
VGS = 10V
ID = 56A, VDS =0V, VGS = 10V
VDD = 20V
ID = 30A
RG = 2.7Ω
VGS = 10V
VGS = 0V
VDS = 25V
ƒ = 1.0 MHz, See Fig. 5
VGS = 0V, VDS = 0V to 32V
See Fig. 12
VGS = 0V, VDS = 0V to 32V
g
ns
pF
g
i
h
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
––– 120
ISM
(Body Diode)
Pulsed Source Current
–––
–––
d
VSD
(Body Diode)
Diode Forward Voltage
dv/dt
trr
Peak Diode Recovery
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
f
3
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c
480
Conditions
A
MOSFET symbol
A
showing the
integral reverse
D
G
S
p-n junction diode.
–––
0.9
1.3
V TJ = 25°C, IS = 56A, VGS = 0V
–––
4.8
––– V/ns TJ = 175°C, IS = 56A, VDS = 40V
VR = 34V,
–––
20
–––
ns TJ = 25°C
TJ = 125°C
IF = 56A
–––
21
–––
di/dt = 100A/μs
–––
13
–––
nC TJ = 25°C
TJ = 125°C
–––
13
–––
–––
1.8
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) *
g
g
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IRFR7446PbF
1000
TOP
100
BOTTOM
VGS
15V
10V
7.0V
6.0V
5.5V
5.0V
4.5V
4.3V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
1000
10
4.3V
1
≤ 60μs PULSE WIDTH
Tj = 25°C
100
BOTTOM
4.3V
10
≤ 60μs PULSE WIDTH
Tj = 175°C
0.1
1
0.1
1
10
100
0.1
VDS, Drain-to-Source Voltage (V)
100
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
Fig 4. Typical Output Characteristics
1000
100
TJ = 175°C
10
TJ = 25°C
1
VDS = 10V
≤ 60μs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
6.0
7.0
8.0
ID = 56A
VGS = 10V
1.5
1.0
0.5
-60 -40 -20 0
VGS, Gate-to-Source Voltage (V)
100000
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 6. Normalized On-Resistance vs. Temperature
Fig 5. Typical Transfer Characteristics
16
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
VGS, Gate-to-Source Voltage (V)
C, Capacitance (pF)
1
VDS, Drain-to-Source Voltage (V)
Fig 3. Typical Output Characteristics
Coss = Cds + Cgd
10000
Ciss
1000
Coss
Crss
ID= 56A
VDS = 32V
VDS = 20V
12
8
4
0
100
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
4
VGS
15V
10V
7.0V
6.0V
5.5V
5.0V
4.5V
4.3V
TOP
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0
20
40
60
80
100
QG Total Gate Charge (nC)
Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage
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IRFR7446PbF
1000
100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
TJ = 175°C
10
TJ = 25°C
1
100μsec
100
1msec
Limited by Package
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.1
2.0
1
10
VDS , Drain-toSource Voltage (V)
VSD, Source-to-Drain Voltage (V)
Fig 10. Maximum Safe Operating Area
Fig 9. Typical Source-Drain Diode
Forward Voltage
0.4
49
Id = 1.0mA
47
0.3
46
Energy (μJ)
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
DC
0.1
0.1
48
10msec
45
44
0.2
43
0.1
42
41
0.0
40
0
-60 -40 -20 0 20 40 60 80 100120140160180
20
30
40
VDS, Drain-to-Source Voltage (V)
TJ , Temperature ( °C )
Fig 11. Drain-to-Source Breakdown Voltage
( Ω)
RDS(on), Drain-to -Source On Resistance m
10
Fig 12. Typical COSS Stored Energy
16.0
VGS = 5.5V
VGS = 6.0V
VGS = 7.0V
VGS = 8.0V
VGS =10V
14.0
12.0
10.0
8.0
6.0
4.0
2.0
0
20 40 60 80 100 120 140 160 180 200
ID, Drain Current (A)
Fig 13. Typical On-Resistance vs. Drain Current
5
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IRFR7446PbF
Thermal Response ( ZthJC ) °C/W
10
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
0.01
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Avalanche Current (A)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 23a, 23b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 14)
EAR , Avalanche Energy (mJ)
140
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 56A
120
100
80
60
40
20
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 16. Maximum Avalanche Energy vs. Temperature
6
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IRFR7446PbF
6
4.0
IF = 34A
VR = 34V
3.5
TJ = 25°C
TJ = 125°C
4
3.0
IRRM (A)
VGS(th) Gate threshold Voltage (V)
4.5
ID =50μA
ID = 250μA
ID = 1.0mA
2.5
2
ID = 1.0A
2.0
1.5
-75 -50 -25
0
25
50
75
0
100 125 150 175
0
200
TJ , Temperature ( °C )
400
600
800
1000
diF /dt (A/μs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig 17. Threshold Voltage vs. Temperature
80
6
IF = 34A
VR = 34V
IF = 56A
VR = 34V
TJ = 25°C
TJ = 125°C
IRRM (A)
QRR (nC)
4
TJ = 25°C
TJ = 125°C
60
40
2
20
0
0
0
200
400
600
800
0
1000
200
400
600
800
1000
diF /dt (A/μs)
diF /dt (A/μs)
Fig. 20 - Typical Stored Charge vs. dif/dt
Fig. 19 - Typical Recovery Current vs. dif/dt
80
IF = 56A
VR = 34V
TJ = 25°C
TJ = 125°C
QRR (nC)
60
40
20
0
0
200
400
600
800
1000
diF /dt (A/μs)
Fig. 21 - Typical Stored Charge vs. dif/dt
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IRFR7446PbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
V DD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
20V
VGS
+
V
- DD
IAS
A
0.01Ω
tp
I AS
Fig 23a. Unclamped Inductive Test Circuit
RD
VDS
Fig 23b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 24a. Switching Time Test Circuit
tr
t d(off)
Fig 24b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2μF
.3μF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 25a. Gate Charge Test Circuit
8
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Qgs1 Qgs2
Qgd
Qgodr
Fig 25b. Gate Charge Waveform
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IRFR7446PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120
WIT H ASS EMBLY
LOT CODE 1234
AS S EMBLED ON WW 16, 2001
IN T HE AS S EMBLY LINE "A"
PART NUMBER
INT ERNAT IONAL
RECT IFIER
LOGO
Note: "P" in as s embly line pos ition
indicates "Lead-Free"
IRFR120
12
116A
34
AS S EMBLY
LOT CODE
DAT E CODE
YEAR 1 = 2001
WEEK 16
LINE A
"P" in as s embly line pos ition indicates
"Lead-Free" qualification to the cons umer-level
OR
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRF R120
12
AS S EMBLY
LOT CODE
34
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
P = DES IGNAT ES LEAD-FREE
PRODUCT QUALIFIED T O T HE
CONS UMER LEVEL (OPT IONAL)
YEAR 1 = 2001
WEEK 16
A = AS S EMBLY S IT E CODE
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
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IRFR7446PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
TRL
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
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IRFR7446PbF
Qualification information†
††
Qualification level
D-PAK
Industrial
†††
(per JEDEC JESD47F guidelines)
MS L1
†††
(per JE DE C J-S T D-020D
RoHS compliant
)
Yes
Qualification standards can be found at International Rectifiers web site: http://www.irf.com/product-info/reliability/
Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information: http:www.irf.com/whoto-call/salesrep/
Applicable version of JEDEC standard at the time of product release.
Revision History
Date
1/6/2015
Comment
• Updated EAS (L =1mH) = 251mJ on page 2
• Updated note 10 “Limited by TJmax , starting TJ = 25°C, L = 1mH, RG = 50Ω, IAS = 22A, VGS =10V”. on page 2
• Updated package outline on page 9.
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
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