NL17SZ02 2-Input NOR Gate The NL17SZ02 is a single 2−input NOR Gate in three tiny footprint packages. The device performs much as LCX multi−gate products in speed and drive. Features • • • • • • • • • Tiny SOT−353, SOT−553 and SOT−953 Packages 2.4 ns TPD at 5 V (typ) Source/Sink 24 mA at 3.0 V Over−Voltage Tolerant Inputs Pin For Pin with NC7SZ02P5X, TC7SZ02FU and TC7SZ02AFE Chip Complexity: FETs = 20 Designed for 1.65 V to 5.5 V VCC Operation NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant http://onsemi.com MARKING DIAGRAMS 5 1 SOT−353/SC70−5/SC−88A DF SUFFIX CASE 419A L3 M G = Specific Device Marking = Date Code = Pb−Free Package (Note: Microdot may be in either location) 5 A VCC 1 5 VCC IN A 5 1 GND B GND 5 M SOT−953 SOT−353/SC70−5/ SC−88A/SOT−553 Figure 1. Pinout (Top View) A B w1 1 = Specific Device Marking = Date Code SOT−953 CASE 527AE 4 3 4 3 L3 M OUT Y IN B Y 5 1 SOT−553 XV5 SUFFIX CASE 463B L3 M 2 2 L3 MG G 5M 1 = Specific Device Code = Month Code ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Y Figure 2. Logic Symbol © Semiconductor Components Industries, LLC, 2014 February, 2014 − Rev. 8 1 Publication Order Number: NL17SZ02/D NL17SZ02 PIN ASSIGNMENT PIN ASSIGNMENT (SOT−953) (SOT−353/SC70−5/SC−88A/SOT−553) FUNCTION TABLE Pin Function Pin Function 1 IN A 1 A 2 GND A B Y 2 B 3 IN B L L H 3 GND 4 OUT Y L H L 4 Y 5 VCC H L L 5 VCC H H L Output Input Y=A+B MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage −0.5 to )7.0 V VIN DC Input Voltage −0.5 to )7.0 V VOUT DC Output Voltage (SOT−353/SC70−5/SC−88A/SOT−553 Packages) −0.5 to VCC + 0.5 V VOUT DC Output Voltage (SOT−953 Package) −0.5 to VCC + 0.5 −0.5 to + 0.5 V −50 mA VOUT < GND, VOUT > VCC ±50 mA VOUT < GND −50 mA Output at High or Low State Power−Down Mode (VCC = 0 V) IIK DC Input Diode Current IOK DC Output Diode Current (SOT−353/SC70−5/SC−88A/SOT−553 Packages) IOK DC Output Diode Current (SOT−953 Package) IOUT DC Output Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA −65 to )150 °C 260 °C TSTG Storage Temperature Range TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature Under Bias qJA Thermal Resistance PD Power Dissipation in Still Air at 85°C MSL Moisture Sensitivity FR Flammability Rating ESD ESD Classification ILATCHUP +150 °C SOT−353 (Note 1) SOT−553 350 496 °C/W SOT−353 SOT−553 186 135 mW Level 1 Oxygen Index: 28 to 34 Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Latchup Performance Above VCC and Below GND at 125°C (Note 5) UL 94 V−0 @ 0.125 in Class 2 Class A N/A ±100 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow. 2. Tested to EIA/JESD22−A114−A, rated to EIA/JESD22−A114−B. 3. Tested to EIA/JESD22−A115−A, rated to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. http://onsemi.com 2 NL17SZ02 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 1.65 5.5 V VCC DC Supply Voltage VIN DC Input Voltage 0 5.5 V VOUT DC Output Voltage (SOT−353/SC70−5/SC−88A/SOT−553 Packages) 0 5.5 V VOUT DC Output Voltage (SOT−953 Package) TA Operating Temperature Range tr, tf Input Rise and Fall Time 0 VCC V −55 +125 °C 0 0 100 20 ns/V VCC = 3.0 V $0.3 V VCC = 5.0 V $0.5 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS Symbol Parameter Condition TA = 255C VCC (V) Min 0.75 VCC 0.7 VCC VIH High−Level Input Voltage 1.65 to 1.95 2.3 to 5.5 VIL Low−Level Input Voltage 1.65 to 1.95 2.3 to 5.5 VOH High−Level Output Voltage VIN = VIL or VIH IOH = −100 mA IOH = −3 mA IOH = −8 mA IOH = −12 mA IOH = −16 mA IOH = −24 mA IOH = −32 mA 1.65 to 5.5 1.65 2.3 2.7 3.0 3.0 4.5 VOL Low−Level Output Voltage VIN = VIH or VOH IOL = 100 mA IOL = 3 mA IOL = 8 mA IOL = 12 mA IOL = 16 mA IOL = 24 mA IOL = 32 mA 1.65 to 5.5 1.65 2.3 2.7 3.0 3.0 4.5 Input Leakage Current VIN = 5.5 V or GND IOFF Power Off Leakage Current (SOT−353/ SC70−5/SC−88A/ SOT−553 Packages) VIN = 5.5 V or VOUT = 5.5 V ICC Quiescent Supply Current VIN = 5.5 V or GND IIN −555C v TA v 1255C Typ Max Min 0.75 VCC 0.7 VCC 0.25 VCC 0.3 VCC VCC − 0.1 1.29 1.9 2.2 2.4 2.3 3.8 Max VCC 1.52 2.1 2.4 2.7 2.5 4.0 Unit V 0.25 VCC 0.3 VCC VCC − 0.1 1.29 1.9 2.2 2.4 2.3 3.8 V V 0.1 0.24 0.3 0.4 0.4 0.55 0.55 0.1 0.24 0.3 0.4 0.4 0.55 0.55 V 0 to 5.5 $0.1 $1.0 mA 0 1 10 mA 5.5 1 10 mA 0.08 0.20 0.22 0.28 0.38 0.42 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. AC ELECTRICAL CHARACTERISTICS tR = tF = 3.0 ns VCC Symbol tPLH tPHL Parameter Propagation Delay (Figure 3 and 4) TA = 255C −555C v TA v 1255C Condition (V) Min Typ Max Min Max Unit RL = 1 MW, CL = 15 pF 1.65 2.0 5.3 11.5 2.0 12.0 ns RL = 1 MW, CL = 15 pF 1.8 2.0 4.4 9.5 2.0 10.0 RL = 1 MW, CL = 15 pF 2.5 $ 0.2 0.8 2.9 6.5 0.8 7.0 RL = 1 MW, CL = 15 pF 3.3 $ 0.3 0.5 2.3 4.5 0.5 4.7 1.5 2.9 5.0 1.5 5.2 0.5 1.9 3.9 0.5 4.1 0.8 2.4 4.3 0.8 4.5 RL = 500 W, CL = 50 pF RL = 1 MW, CL = 15 pF 5.0 $ 0.5 RL = 500 W, CL = 50 pF http://onsemi.com 3 NL17SZ02 CAPACITIVE CHARACTERISTICS Symbol Parameter Condition Typical Unit CIN Input Capacitance VCC = 5.5 V, VI = 0 V or VCC u4 pF CPD Power Dissipation Capacitance (Note 6) 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 25 pF 10 MHz, VCC = 5.5 V, VI = 0 V or VCC 30 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. tf = 3 ns tf = 3 ns 90% INPUT A and B VCC 90% 50% 50% 10% 10% tPHL INPUT GND OUTPUT RL tPLH CL VOH OUTPUT Y 50% 50% A 1−MHz square input wave is recommended for propagation delay tests. VOL Figure 3. Switching Waveform Figure 4. Test Circuit ORDERING INFORMATION Package Shipping† NL17SZ02DFT2G SC−88A/SOT−353/SC−70−5 (Pb−Free) 3000 / Tape & Reel NLV17SZ02DFT2G* SC−88A/SOT−353/SC−70−5 (Pb−Free) 3000 / Tape & Reel NL17SZ02XV5T2G SOT−553 (Pb−Free) 4000 / Tape & Reel NL17SZ02P5T5G SOT−953 (Pb−Free) 8000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 4 NL17SZ02 PACKAGE DIMENSIONS SC−88A (SC−70−5/SOT−353) CASE 419A−02 ISSUE L A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. G 5 4 −B− S 1 2 DIM A B C D G H J K N S 3 D 5 PL 0.2 (0.008) M B M N INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 J C K H SOLDER FOOTPRINT* 0.50 0.0197 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 NL17SZ02 PACKAGE DIMENSIONS SOT−553 XV5 SUFFIX CASE 463B ISSUE B D −X− 5 A 4 1 e 2 E −Y− 3 b NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. L DIM A b c D E e L HE HE c 5 PL 0.08 (0.003) M X Y MILLIMETERS NOM MAX 0.55 0.60 0.22 0.27 0.13 0.18 1.60 1.70 1.20 1.30 0.50 BSC 0.10 0.20 0.30 1.50 1.60 1.70 MIN 0.50 0.17 0.08 1.50 1.10 SOLDERING FOOTPRINT* 0.3 0.0118 0.45 0.0177 1.35 0.0531 1.0 0.0394 0.5 0.5 0.0197 0.0197 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 INCHES NOM 0.022 0.009 0.005 0.063 0.047 0.020 BSC 0.004 0.008 0.059 0.063 MIN 0.020 0.007 0.003 0.059 0.043 MAX 0.024 0.011 0.007 0.067 0.051 0.012 0.067 NL17SZ02 PACKAGE DIMENSIONS SOT−953 CASE 527AE ISSUE E X D Y PIN ONE INDICATOR 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF THE BASE MATERIAL. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. A 4 HE E 1 2 3 DIM A b C D E e HE L L2 L3 C TOP VIEW SIDE VIEW e L 5X 5X L3 MILLIMETERS MIN NOM MAX 0.34 0.37 0.40 0.10 0.15 0.20 0.07 0.12 0.17 0.95 1.00 1.05 0.75 0.80 0.85 0.35 BSC 0.95 1.00 1.05 0.175 REF 0.05 0.10 0.15 −−− −−− 0.15 SOLDERING FOOTPRINT* 5X 0.35 5X 0.20 5X L2 5X BOTTOM VIEW b PACKAGE OUTLINE 0.08 X Y 1.20 1 0.35 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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