IRFS7530-7P Data Sheet (566 KB, EN)

StrongIRFET™
IRFS7530-7PPbF
HEXFET® Power MOSFET
Application
 Brushed Motor drive applications
 BLDC Motor drive applications
 Battery powered circuits
 Half-bridge and full-bridge topologies
 Synchronous rectifier applications
 Resonant mode power supplies
 OR-ing and redundant power switches
VDSS
60V
RDS(on) typ.
1.15m
max
1.4m
D
G
S
ID (Silicon Limited)
338A
ID (Package Limited)
240A
Benefits
 Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
 Fully Characterized Capacitance and Avalanche SOA
 Enhanced body diode dV/dt and dI/dt Capability
 Lead-Free, RoHS Compliant
G
Gate
Package Type
IRFS7530-7PPbF
D2Pak-7PIN
Standard Pack
Form
Quantity
Tube
50
Tape and Reel Left
800
6
5
300
4
250
3
TJ = 125°C
2
1
TJ = 25°C
Complete Part Number
IRFS7530-7PPbF
IRFS7530TRL7PP
Limited By Package
200
150
100
50
0
4
8
12
16
20
VGS, Gate-to-Source Voltage (V)
Fig 1. Typical On-Resistance vs. Gate Voltage
1
S
Source
350
ID = 100A
ID, Drain Current (A)
( )
RDS(on), Drain-to -Source On Resistance m
Base Part Number
D
Drain
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0
25
50
75
100
125
150
175
TC , Case Temperature (°C)
Fig 2. Maximum Drain Current vs. Case Temperature
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IRFS7530-7PPbF
Absolute Maximium Rating
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
VGS
TJ
TSTG
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
Pulsed Drain Current 
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Operating Junction and
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
Drain-to-Source Breakdown Voltage
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
IDSS
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Resistance
Typ. Max.
––– –––
33
–––
1.15 1.4
1.4
–––
–––
3.7
–––
1.0
––– 150
––– 100
––– -100
2.2
–––
A
W
W/°C
V
°C 300
526
1029
mJ
See Fig 14, 15, 23a, 23b
A
mJ
Typ.
–––
–––
Min.
60
–––
–––
–––
2.1
–––
–––
–––
–––
–––
Units
-55 to + 175 Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
Avalanche Characteristics EAS (Thermally limited)
Single Pulse Avalanche Energy 
EAS (Thermally limited)
Single Pulse Avalanche Energy 
IAR
Avalanche Current 
Repetitive Avalanche Energy 
EAR
Thermal Resistance Symbol
Parameter
Junction-to-Case 
RJC
Junction-to-Ambient 
RJA
RG
Max.
338
239
240
1450
375
2.5
± 20
Units
V
mV/°C
m
m
V
µA
nA
Max.
0.40
40
Units
°C/W Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA 
VGS = 10V, ID = 100A 
VGS = 6.0V, ID = 50A 
VDS = VGS, ID = 250µA
VDS = 60 V, VGS = 0V
VDS = 60V,VGS = 0V,TJ =125°C
VGS = 20V
VGS = -20V

Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A.
Note that current limitations arising from heating of the device leads may occur with some lead mounting
arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction temperature.
 Limited by TJmax, starting TJ = 25°C, L = 105µH, RG = 50, IAS = 100A, VGS =10V.
ISD  100A, di/dt  1575A/µs, VDD  V(BR)DSS, TJ 175°C.
Pulse width  400µs; duty cycle  2%.
 Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
 Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
 R is measured at TJ approximately 90°C.
 Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 45A, VGS =10V.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques
refer to application note #AN-994: http://www.irf.com/technical-info/appnotes/an-994.pdf
2
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IRFS7530-7PPbF
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Min.
249
–––
–––
–––
–––
–––
–––
Typ. Max. Units
Conditions
––– –––
S VDS = 10V, ID =100A
236 354
ID = 100A
62
–––
VDS = 30V
nC 73
–––
VGS = 10V
163 –––
24
–––
VDD = 30V
ID = 100A
102 –––
ns
168 –––
RG= 2.7
VGS = 10V
79
–––
td(off)
Turn-Off Delay Time
–––
tf
Ciss
Coss
Crss
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
––– 12960 –––
––– 1270 –––
––– 760 –––
Coss eff.(ER)
Effective Output Capacitance (Energy Related)
–––
1248
–––
VGS = 0V, VDS = 0V to 48V
Coss eff.(TR)
Output Capacitance (Time Related)
–––
1590
–––
VGS = 0V, VDS = 0V to 48V
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Min.
Typ. Max. Units
–––
––– 338
–––
–––
1450
VSD
Diode Forward Voltage
–––
–––
1.2
dv/dt
Peak Diode Recovery dv/dt
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
Reverse Recovery Current
–––
–––
–––
–––
–––
–––
8.5
48
50
72
83
2.5
–––
–––
–––
–––
–––
–––
VGS = 0V
VDS = 25V
pF ƒ = 1.0MHz
Diode Characteristics Symbol
IS
ISM
3
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A
V
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
D
G
S
TJ = 25°C,IS = 100A,VGS = 0V 
V/ns TJ = 175°C,IS =100A,VDS = 60V
TJ = 25°C
VDD = 51V
ns
TJ = 125°C
IF = 100A,
TJ = 25°C di/dt = 100A/µs 
nC
TJ = 125°C
A TJ = 25°C 
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IRFS7530-7PPbF
10000
10000
1000
BOTTOM
100
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
4.5V
1000
BOTTOM
100
4.5V
 60µs PULSE WIDTH
Tj = 175°C
 60µs PULSE WIDTH
Tj = 25°C
1
10
0.1
1
10
100
0.1
VDS, Drain-to-Source Voltage (V)
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000
TJ = 175°C
100
TJ = 25°C
10
1
VDS = 25V
 60µs PULSE WIDTH
0.1
2.0
4.0
6.0
ID = 100A
VGS = 10V
2.0
1.5
1.0
0.5
8.0
-60 -40 -20
VGS, Gate-to-Source Voltage (V)
1000000
Ciss
10000
Coss
1000
Fig 6. Normalized On-Resistance vs. Temperature
VGS, Gate-to-Source Voltage (V)
= C gd
C oss = C ds + C gd
100000
20 40 60 80 100 120 140 160 180
14
VGS = 0V,
f = 1 MHZ
C iss = Cgs + C gd , Cds SHORTED
C rss
0
TJ , Junction Temperature (°C)
Fig 5. Typical Transfer Characteristics
C, Capacitance (pF)
100
2.5
10000
Crss
ID= 100A
12
VDS= 48V
VDS= 30V
VDS= 12V
10
8
6
4
2
0
100
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Capacitance vs.
4
10
Fig 4. Typical Output Characteristics
Fig 3. Typical Output Characteristics
ID, Drain-to-Source Current (A)
1
VDS, Drain-to-Source Voltage (V)
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0
50
100
150
200
250
300
QG Total Gate Charge (nC)
Fig 8. Typical Gate Charge vs.
Gate-to-Source Voltage
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IRFS7530-7PPbF
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
10000
1000
TJ = 175°C
100
TJ = 25°C
10
1
1000
100µsec
100
Package
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
1
0.1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
DC
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.1
VSD, Source-to-Drain Voltage (V)
1
10
100
VDS, Drain-toSource Voltage (V)
Fig 10. Maximum Safe Operating Area
Fig 9. Typical Source-Drain Diode Forward Voltage
80
2.0
Id = 1.0mA
1.5
Energy (µJ)
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
1msec
Limited by
70
1.0
0.5
0.0
60
0
-60 -40 -20 0 20 40 60 80 100120140160180
20
30
40
50
60
VDS, Drain-to-Source Voltage (V)
TJ , Temperature ( °C )
Fig 12. Typical Coss Stored Energy
Fig 11. Drain-to-Source Breakdown Voltage
( )
RDS(on), Drain-to -Source On Resistance m
10
2.2
VGS = 5.5V
2.0
VGS = 6.0V
1.8
VGS = 8.0V
VGS = 7.0V
VGS = 10V
1.6
1.4
1.2
1.0
0
50
100
150
200
ID, Drain Current (A)
Fig 13. Typical On-Resistance vs. Drain Current
5
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IRFS7530-7PPbF
Thermal Response ( ZthJC ) °C/W
1
D = 0.50
0.1
0.20
0.10
0.05
0.01
0.02
0.01
0.001
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming  Tj = 150°C and
Tstart =25°C (Single Pulse)
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C. (Single Pulse)
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Avalanche Current vs. Pulse Width
EAS, Single Pulse Avalanche Energy (mJ)
2400
ID
TOP
21A
44A
BOTTOM 100A
2000
1600
1200
800
400
0
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy vs. Temperature
6
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Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1.Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for every
part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
23a, 23b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
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IRFS7530-7PPbF
16
IF = 60A
VR = 51V
3.5
TJ = 25°C
TJ = 125°C
12
3.0
IRRM (A)
VGS(th) Gate threshold Voltage (V)
4.0
ID = 250µA
ID = 1.0mA
2.5
8
ID = 1.0A
2.0
4
1.5
1.0
0
-75 -50 -25
0
25
50
75
100 125 150 175
0
200
TJ , Temperature ( °C )
600
800
1000
diF /dt (A/µs)
Fig 17. Threshold Voltage vs. Temperature
Fig 18. Typical Recovery Current vs. dif/dt
500
16
IF = 100A
VR = 51V
IF = 60A
VR = 51V
400
TJ = 25°C
TJ = 125°C
QRR (nC)
12
IRRM (A)
400
8
4
TJ = 25°C
TJ = 125°C
300
200
100
0
0
0
200
400
600
800
0
1000
200
400
600
800
1000
diF /dt (A/µs)
diF /dt (A/µs)
Fig 19. Typical Recovery Current vs. dif/dt
Fig 20. Typical Stored Charge vs. dif/dt
500
IF = 100A
VR = 51V
QRR (nC)
400
TJ = 25°C
TJ = 125°C
300
200
100
0
0
200
400
600
800
1000
diF /dt (A/µs)
Fig 21. Typical Stored Charge vs. dif/dt
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IRFS7530-7PPbF
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
tp
15V
L
VDS
D.U.T
RG
IAS
20V
tp
DRIVER
+
V
- DD
A
0.01
I AS
Fig 23a. Unclamped Inductive Test Circuit
Fig 23b. Unclamped Inductive Waveforms
Fig 24a. Switching Time Test Circuit
Fig 24b. Switching Time Waveforms
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Fig 25a. Gate Charge Test Circuit
8
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Qgd
Qgodr
Fig 25b. Gate Charge Waveform
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IRFS7530-7PPbF
D2Pak-7Pin Package Outline (Dimensions are shown in millimeters (inches))
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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IRFS7530-7PPbF
D2Pak-7Pin Part Marking Information
D2Pak-7Pin Tape and Reel
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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IRFS7530-7PPbF
Qualification Information† Industrial
(per JEDEC JESD47F) ††
Qualification Level Moisture Sensitivity Level
MSL1
(per JEDEC J-STD-020D††)
Yes
D2Pak-7Pin
RoHS Compliant
†
Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability/
††
Applicable version of JEDEC standard at the time of product release.
Revision History
Date
03/05/2015
Comment
Updated EAS (L =1mH) = 1029mJ on page 2
Updated note 9 “Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 45A, VGS =10V” on page 2
 Updated package outline on page 9 .
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
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