IRL1004S Data Sheet (210 KB, EN)

PD - 95575
Logic-Level Gate Drive
Advanced Process Technology
l Ultra Low On-Resistance
l Dynamic dv/dt Rating
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
l Lead-Free
Description
IRL1004SPbF
IRL1004LPbF
l
l
HEXFET® Power MOSFET
D
VDSS = 40V
RDS(on) = 0.0065Ω
G
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible onresistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRL1004L) is available for lowprofile application.
ID = 130A…
S
Fifth Generation HEXFET® power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast switching
speed and ruggedized device design that HEXFET power
MOSFETs are well known for, provides the designer with
an extremely efficient and reliable device for use in a wide
variety of applications.
D2Pak
IRL1004S
TO-262
IRL1004L
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TA = 25°C
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 10V†
Continuous Drain Current, VGS @ 10V†
Pulsed Drain Current †
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy†
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt Ġ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
130 …
92 …
520
3.8
200
1.3
± 16
700
78
20
5.0
-55 to + 175
Units
A
W
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case)
Thermal Resistance
Parameter
RθJC
RθJA
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Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)*
Typ.
Max.
Units
–––
–––
0.75
40
°C/W
1
07/19/04
IRL1004S/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
40
–––
–––
–––
1.0
63
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
V(BR)DSS
IGSS
Typ. Max. Units
Conditions
––– –––
V
VGS = 0V, ID = 250µA
0.04 ––– V/°C Reference to 25°C, ID = 1mA
––– 0.0065
VGS = 10V, ID = 78A „
Ω
––– 0.009
VGS = 4.5V, ID = 65A „
–––
V
VDS = VGS, ID = 250µA
––– –––
S
VDS = 25V, ID = 78A†
––– 25
VDS = 40V, VGS = 0V
µA
––– 250
VDS = 32V, VGS = 0V, TJ = 150°C
––– 100
VGS = 16V
nA
––– -100
VGS = -16V
––– 100
ID = 78A
––– 32
nC
VDS = 32V
––– 43
VGS = 4.5V, See Fig. 6 and 13 „†
16 –––
VDD = 20V,
210 –––
ID = 78A,
25 –––
ns
RG = 2.5Ω,
14 –––
RD = 0.18Ω, See Fig. 10 „†
Between lead,
7.5
nH
–––
and center of die contact
5330 –––
VGS = 0V
1480 –––
pF
VDS = 25V
320 –––
ƒ = 1.0MHz, See Fig. 5…†
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)‡
Pulsed Source Current
(Body Diode) ‡
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 130…
showing the
A
G
integral reverse
––– ––– 520
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 78A, VGS = 0V„
––– 78 120
ns
TJ = 25°C, IF = 78A
––– 180 270
nC di/dt = 100A/µs„†
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
‚ Starting TJ = 25°C, L = 0.23mH
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
…
Calculated continuous current based on maximum allowable
junction temperature; for recommended current-handing of the
package refer to Design Tip # 93-4
†
Uses IRL1004 data and test conditions
RG = 25Ω, I AS = 78A. (See Figure 12)
ƒ ISD ≤ 78A, di/dt ≤ 370A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
* When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
2
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IRL1004S/LPbF
10000
1000
VGS
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
BOTTOM 2.7V
1000
100
10
1
2.7V
20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
1
10
100
10
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 25 ° C
TJ = 175 ° C
10
1
V DS = 50V
20µs PULSE WIDTH
4.0
5.0
6.0
7.0
8.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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1
10
100
Fig 2. Typical Output Characteristics
1000
3.0
20µs PULSE WIDTH
TJ = 175 °C
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100
2.7V
1
0.1
100
VDS , Drain-to-Source Voltage (V)
0.1
2.0
VGS
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
BOTTOM 2.7V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
9.0
ID = 130A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRL1004S/LPbF
10000
VGS , Gate-to-Source Voltage (V)
8000
C, Capacitance (pF)
12
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Ciss
6000
Coss
4000
2000
Crss
0
ID = 78 A
10
8
6
4
2
FOR TEST CIRCUIT
SEE FIGURE 13
0
1
10
0
100
30
60
90
120
150
180
QG , Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
10000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
TJ = 175 ° C
100
1000
ID , Drain Current (A)
ISD , Reverse Drain Current (A)
VDS = 32V
VDS = 20V
10
TJ = 25 ° C
1
100us
100
1ms
10ms
10
0.1
0.0
V GS = 0 V
0.5
1.0
1.5
2.0
2.5
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10us
3.0
TC = 25 °C
TJ = 175 °C
Single Pulse
1
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRL1004S/LPbF
140
VGS
120
ID , Drain Current (A)
RD
VDS
LIMITED BY PACKAGE
D.U.T.
RG
+
-V DD
100
10V
80
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
60
Fig 10a. Switching Time Test Circuit
40
VDS
20
0
90%
25
50
75
100
125
150
175
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC)
1
D = 0.50
0.20
0.1
0.10
PDM
0.05
t1
0.02
0.01
t2
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRL1004S/LPbF
L
D.U.T.
RG
VDD
tp
BOTTOM
ID
32A
55A
78A
1200
IAS
4.5 V
TOP
1500
+
-
EAS , Single Pulse Avalanche Energy (mJ)
1800
VDS
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
900
600
300
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature ( °C)
VDD
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
VDS
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
4.5 V
QGS
QGD
D.U.T.
+
V
- DS
VGS
VG
3mA
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRL1004S/LPbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-channel HEXFET® Power MOSFETs
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7
IRL1004S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T H IS IS AN IR F 530S WIT H
LOT CODE 8024
AS S E MB L E D ON WW 02, 2000
IN T H E AS S E MB LY LINE "L"
INT E RNAT IONAL
RE CT IF IE R
LOGO
Note: "P" in as s embly line
pos ition indicates "L ead-F ree"
PART NUMB E R
F 530S
AS S E MB L Y
L OT CODE
OR
INT ERNAT IONAL
RE CT IF IER
LOGO
AS S EMB LY
L OT CODE
8
DAT E CODE
YE AR 0 = 2000
WE E K 02
LINE L
PART NU MB E R
F 530S
DAT E CODE
P = DE S IGNAT E S L E AD-F RE E
PRODUCT (OPT IONAL)
YEAR 0 = 2000
WEE K 02
A = AS S E MB L Y S IT E CODE
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IRL1004S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
E XAMPLE: THIS IS AN IRL 3103L
LOT CODE 1789
AS S EMBL ED ON WW 19, 1997
IN THE AS S E MB LY L INE "C"
Note: "P" in as s embly line
pos ition indicates "L ead-F ree"
INT ERNATIONAL
RE CTIF IE R
L OGO
AS S EMBLY
LOT CODE
PART NUMBE R
DAT E CODE
YE AR 7 = 1997
WE EK 19
LINE C
OR
INT ERNAT IONAL
RECT IF IER
L OGO
AS S EMBL Y
L OT CODE
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PART NUMB ER
DAT E CODE
P = DES IGNAT E S LEAD-F RE E
PRODUCT (OPT IONAL)
YE AR 7 = 1997
WE EK 19
A = AS S EMBL Y S IT E CODE
9
IRL1004S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
3
4
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/04
10
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/