STK544UC62K-E Application Note

STK544UC62K-E
Application Note
http://onsemi.com
1. Product synopsis
This application handbook is intended to provide practical guidelines for the STK544UC62K-E use.
The STK544UC62K-E is hybrid ICs based upon ONs Insulated Metal Substrate Technology (IMST) for 3-phase
motor drives which contain the main power circuitry and the supporting control circuitry. The key functions
are outlined below:
• Highly integrated device containing all High Voltage (HV) control from HV-DC to 3-phase outputs in a
single small SIP module.
• Output stage uses IGBT/FRD technology and implements Under Voltage Protection (UVP) and Over
Current Protection (OCP) with a Fault Detection output flag. Internal Boost diodes are provided for high
side gate boost drive.
• Option of a combined or individual shunt resistor per phase for OCP.
• Externally accessible embedded thermistor for substrate temperature measurement.
• All control inputs and status outputs are at low voltage levels directly compatible with microcontrollers.
• Single control power supply due to internal bootstrap circuit for high side pre-driver circuit.
• Mounting points are available on SIP package
A simplified block diagram of a motor control system is shown if Figure 1.
Figure 1. Motor Control System Block Diagram
Semiconductor Components Industries, LLC, 2013
June, 2013
1/17
Rev.0
STK544UC62K-E Application Note
2. Product description
Table1. Give an overview of the available devices, for a detailed description of the package refer to Chapter 6.
Device
Feature
Package
Voltage (VCEmax.)
Current (Ic)
Peak current (Ic)
Isolation voltage
Shunt resistance
STK544UC62K-E
triple shunts
SIP-23 56*21.8 (SIP1) - Vertical pins
600V
10A
20A
2000V
external
Vertical type models; STK544UC62K-E are available for pin forming option.
Table 1. Device Overview
VB3 (1)
W,VS3 (2)
VB2 (4)
V,VS2 (5)
VB1 (7)
V,VS1 (8)
V+ (10)
DB
DB
DB
U.V.
U.V.
U.V.
VRU (12)
VRV (13)
VRW (14)
Level
Shifter
Level
Shifter
Level
Shifter
HIN1 (15)
HIN2 (16)
HIN3 (17)
Logic
Logic
Logic
LIN1 (18)
LIN2 (19)
LIN3 (20)
Thermistor
T/ITRIP (21)
Shut down
VDD (22)
S
Under voltage
DETECT
VSS (23)
Vref
Q
Timer
R
Latch time about 9ms
Figure 2. STK544UC62K-E equivalent circuits
The high side drive is used with a bootstrap circuit to generate the higher voltage needed for gate drive. The
Boost diodes are internal to the part and sourced from VDD (15V). There is an internal level shift circuit for
the high side drive signals allowing all control signals to be driven directly from VSS levels common with the
control circuit such as the microcontroller without requiring external level shift such as opto-isolators.
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STK544UC62K-E Application Note
3. Performance test guidelines
The following Chapter gives performance test method shown in Figures 3 to 7.
3.1. Switching time definition and performance test method
trr
10%
90%
90%
VCE
HIN/LIN
Io
10%
10%
td(ON)
td(OFF)
tr
tf
tOFF
tON
IN
Figure 3. Switching time definition
Ex) Lower side U phase measurement
7
VD1=15V
10
8
4
VD2=15V
5
8
CS
1
VD3=15V
VCC
2
22
VD4=15V
Input signal
Io
18
12
23
Figure 4. Evaluation circuit (inductive load)
H-IC
Ho
HIN1,2,3
Driver
Lo
U,V,W
Input signal
LIN1,2,3
VCC
CS
Io
Input signal
Io
Figure 5. Switching loss circuit
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STK544UC62K-E Application Note
H-IC
Ho
HIN1,2,3
Driver
Lo
U,V,W
Input signal
LIN1,2,3
VCC
CS
Io
Input signal
Io
Figure 6. R.B.SOA circuit
H-IC
Ho
HIN1,2,3
Driver
Lo
U,V,W
Input signal
LIN1,2,3
VCC
CS
Io
Input signal
Io
Figure 7. S.C.SOA circuit
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STK544UC62K-E Application Note
3.2. Thermistor Characteristics
An integrated thermistor is used to sense the internal module temperature its electrical characteristic is
outlined below.
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Resistance
R25
Tc=25°C
97.0
100.0
103.0
kΩ
Resistance
R125
Tc=125°C
2.358
2.522
2.695
kΩ
B-Constant(25-50°C)
B
-
4207.5
4250
4292.5
K
Temperature Range
-
-
-40
-
+125
°C
Table 2. NTC Thermistor value
Rt is the value of the integrated NTC thermistor at Tc=25 °C. The resistance value is 100kΩ±3% and the value
of the B-Constant (25-50 °C) is 4250K±1%. The temperature depended value is calculated as shown in the
formula.
R t =R25 ×
The resulting in the NTC values over temperatures
10000
Case Temperature (Tc) - Thermistor Resistance (Rth)
Thermistor Resistance, Rth (kΩ)
Minimum
Nomal
1000
Maximum
100
10
1
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90 100 110 120 130
Case Temperature, Tc (°C)
Figure 8. NTC value vs temperature
4. Protective functions and Operation Sequence
This chapter describes the protection features
• over current protection
• under Voltage Lockout (UVLO) protection
• cross conduction prevention
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STK544UC62K-E Application Note
4.1. Over current protection
In difference to the internal single shunt series modules, the STK544UC62K-E module utilizes an external
shunt resistor for the OCP functionality. As shown in Figure 9 the emitters of all three lower side IGBTs
brought out to module pins. An external ‘over current protection circuitry’ consisting of the shunt resistor
and an RC filter network define the trip level.
Figure 9. Over-current protection circuit setting
The OCP function is implemented by comparing the voltage on the Itrip input to an internal reference of
4.17V (typ). In case the voltage on this terminal i.e. across the shunt resistor exceeds the trip level an OCP
fault is triggered.
Note: The current value of the OCP needs to be set by correctly sizing the external shunt resistor to less
than 2x of the modules rated current.
In case of an OCP event all internal gate drive signal for the IGBTs of all three phases become inactive and
the FLT/EN fault signal output is activated (low).
An RC filter is used on the Itrip input to prevent an erroneous OCP detection due to normal switching noise
and/or recovery diode current. The time constant of that RC filter should be set to a value between 1.5μ to
2μs. In any case the time constant must be shorter than the IGBTs short current safe operating area
(SCSOA) according to Figure 10. The resulting OCP level due to the filter time constant is shown in Figure
11.
SCSOA time(Gate-pulse) -Tc
SCSOA time [us]
10
8
6
4
2
0
0
20
40
60
Tc [℃ ]
80
100
120
Figure 10. IGBT SCSOA
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Collector Current Ic (A)
STK544UC62K-E Application Note
Over-current protective level
Collector Current
Waveform
Input pulse width tw (usec.)
Figure 11. filter time constant
For optimal performance all traces around the shunt resistor need to be kept as short as possible
Figure 12. shows the sequence of events in case of an OCP event.
Figure 12. Over current protection timing chart
4.2. Under Voltage Lockout Protection
The UVLO protection is designed to prevent unexpected operating behavior as described in Table 3. Both
High-side and Low-side have UV protecting function. However the fault signal output only corresponds to
the Low-side UVLO Protection. During the UVLO state the fault output is continuously driven (low).
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STK544UC62K-E Application Note
VDD Voltage (typ. Value)
Operation behavior
< 12.5V
As the voltage is lower than the UVLO threshold the control
circuit is not fully on.
A perfect function cannot be guaranteed.
12.5V - 13.5V
IGBTs can work, however conduction and switching losses
increase due to low voltage gate signal.
13.5V - 16.5V
Recommended conditions.
16.5V-20.0V
IGBTs can work. Switching speed is faster and saturation current
higher, increasing short-circuit broken risk.
> 20.0V
Control circuit is destroyed. Absolute max rating is 20V
Table 3. Module operation according to control supply voltage
The sequence of events in case of a low side UVLO event (IGBTs turned off and active fault output) is
shown in Figure 13. Figure 14 shows the same for a high side UVLO (IGBTs turned off and no fault output).
Figure 13. Low side UVLO timing chart
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STK544UC62K-E Application Note
Figure 14. High side UVLO timing chart
4.3. Cross conduction prevention
The STK544UC62K-E module implement a cross conduction prevention logic at the pre-driver to avoid
simultaneous drive of the low-side and high-side IGBTs as shown in Figure 15.
Figure 15. Cross input conduction prevention
In case of both high and low side drive inputs are active (Low) the logic prevents both gates from being
driven a corresponding timing diagram can be found in Figure 16 below.
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STK544UC62K-E Application Note
Figure 16. Cross conduction prevention timing chart
Even so cross conduction on the IGBTs due to incorrect external driving signals is prevented by the circuitry
the driving signals (HIN and LIN) need to include a “dead time”. This period where both inputs are inactive
between either one becoming active is required due to the internal delays within the IGBTs. Figure 17
shows the delay from the HIN-input via the internal HVG to high side IGBT, the similar path for the low side
and the resulting minimum dead time which is equal to the potential shoot through period:
Figure 17. Shoot trough period
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STK544UC62K-E Application Note
5. PCB design and mounting guidelines
This chapter provides guidelines for an optimized design and PCB layout as well as module mounting
recommendations to appropriately handle and assemble the HIC module.
5.1. Application (schematic) design
The following figures 18 give an overview of the external circuitry’s functionality when designing with the
STK544UC62K-E module.
Stability of VDD
Noise absorb
Prevention of voltage up by
the surge voltage
Noise absorb
+15V
Vz<
22V
To micro
control
Prevention of miss
operation by the noise
HIN1
Stability of VB
100μF
/25V
+5V
100
LIN2
100
LIN3
VSS
T/ITRIP
VB3
7
W, VS3
8
VB2
4
V, VS2
5
VB1
1
U, VS1
2
100nF
/25V
10μF
/25V
Vz<
22V
100nF
/25V
10μF
/25V
Vz<
22V
100nF
/25V
10μF
/25V
Vz<
22V
470μF
/630V
snubber
W
V
4.3k
100
LIN1
23
3.3k 3.3k 3.3k 3.3k 3.3k 3.3k
100
HIN3
VDD
21
100
100
HIN2
100nF
/25V
22
100
15
HIN1
16
HIN2
17
HIN3
18
LIN1
19
LIN2
20
LIN3
V+
DC IN
10
Rshunt
VRU
12
VRV
13
VRW
14
U
Restraint of surge voltage
and vibration voltage
DC OUT
From small voltage
to large voltage
To micro
control
Prevention of miss
operation by the noise
Amp.
Figure 18. STK544UC62K-E application circuit
5.2. Pin by pin design and usage notes
This section provides pin by pin PCB layout recommendations and usage notes. For a complete list of
module pins refer to the datasheet or Chapter 6.
V+ &
VRU, VRV, VRW
U, V, W
VDD, VSS
These pins are connected with the main DC power supply. The applied voltage is up to the Vcc level.
Overvoltage on these pins could be generated by voltage spikes during switching at the floating inductance of
the wiring. To avoid this behavior the wire traces need to be as short as possible to reduce the floating
inductance. In addition a snubber capacitor needs to be placed as close as possible to these pins to stabilize
the voltage and absorb voltage surges.
These terminals are the output pins for connecting the 3-phase motor. They share the same GND potential
with each of the high side control power supplies. Therefore they are also used to connect the GND of the
bootstrap capacitors. These bootstrap capacitors should be placed as close to the module as possible.
These pins connect with the circuitry of the internal protection and pre-drivers for the low -side power
elements and also with the control power supply of the logic circuitry. Voltage to input these terminals is
monitored by the under voltage protection circuit. The VSS terminal is the reference voltage for the control
inputs signals as well as Fault and ISO. VSS is connected with the ‘VRU, VRV, VRW’ terminal internally. The
main circuit does typically not draw current from VSS.
When the ‘VRU, VRV, VRW’ and ‘VSS’ pins are connected externally care must be taken to select a single
connection point as close as possible to the IC. In case of multiple connections to these pins and longer traces
being used, the over current protection level may become low. Therefore this should be avoided.
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STK544UC62K-E Application Note
VB1, 2, 3
The VBx pins are internally connected to the positive supply of the high-side drivers. The supply needs to be
floating and electrically isolated. The boot-strap circuit shown in Figure 19 forms this power supply
individually for every phase. Due to integrated boot resistor and diode (RB & DB) only an external boot
capacitor (CB) is required. There are two current path to charge CB – depicted as ① and ②.
① when the low side power IGBT is ON
② when motor current is flows in CB
The capacitor is discharged while the high-side driver is activated.
Thus CB needs to be selected taking the maximum on time of the high side and the switching frequency into
account.
DB
Driver
CB
RB
①
②
Driver
VDD
Figure 19. Boot strap circuit
To set an initial charge on CB a high ohmic resistor can be used between the motor and the ‘VRU, VRV, VRW’
pins – considering the max voltage rating of the device.
The voltages on the high side drivers are individually monitored by the under voltage protection circuit. In
case an UVP event is detected on a phase its operation is stopped.
HIN1, 2, 3
LIN1, 2, 3
Typically a CB value of less or equal 47uF (±20%) is used. In case the CB value needs to be higher an external
resistor (of apx. 20Ω or less) should be used in series with the capacitor to avoid high currents which can
cause malfunction of the hybrid IC.
These pins are the control inputs for the power stages. The inputs on HIN1/HIN2/HIN3 control the high-side
transistors of U/V/W, and the inputs on LIN1/LIN2/LIN3 control the low-side transistors of U/V/W
respectively. The input are active high and the input thresholds VIH and VIL are 5V compatible to allow direct
control with a microcontroller system
Simultaneous activation of both low and high side is prevented internally to avoid shoot through at the power
stage. However, due to IGBT switching delays the control signals must include a dead-time.
The equivalent input stage circuit is shown in Figure 20.
VDD
100kΩ
IN
VSS
Figure 20. Internal input circuit
For fail safe operation the control inputs are internally tied to VDD via a 100kΩ (typ) resistor. To avoid
switching captured by external wiring to influence the module behavior an additional external low-ohmic
pull-up resistor with a value of 2.2k to 3.3kΩ should be used.
The output might not respond when the width of the input pulse is less than 1µs (both ON and OFF).
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STK544UC62K-E Application Note
T/ITRIP
An internal thermistor to sense the substrate temperature is connected between “VDD” and the “T/ITRIP”
terminal. The substrate temperature is accessible externally by this terminal.
Figure 21. Internal input circuit
Figure 22. Variation of temperature sense voltage with internal thermistor
by using external bias resistance of 4.3kΩ ±1% and VDD=15V
This terminal also has the function for shutdown input. When the input voltage to “T/ITRIP exceed threshold,
al IGBTs are shut down. And Normal operation resumes 8ms after the condition of over current is removed.
Note:
with this mimic only the substrate temperature can be monitored.
5.3. Heat sink mounting and torque
If a heat sink is used, insufficiently secure or inappropriate mounting can lead to a failure of the heat sink to
dissipate heat adequately. This can lead to an inability of the device to provide its inherent performance, a
serious reduction in reliability, or even destruction, burst and burn of the device due to over-heating.
The following general points should be observed when mounting H-IC on a heat sink:
1. Verify the following points related to the heat sink:
- There must be no burrs on aluminum or copper heat sinks.
- Screw holes must be countersunk.
- There must be no unevenness in the heat sink surface that contacts H-IC.
- There must be no contamination on the heat sink surface that contacts H-IC.
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STK544UC62K-E Application Note
2. Highly thermal conductive silicone grease needs to be applied to the whole back (aluminum substrate
side) uniformly, and mount H-IC on a heat sink. Upon re-mounting apply silicone grease (100 to 200μm)
again uniformly.
3. For an intimate contact between the H-IC and the heat sink, the mounting screws should be tightened
gradually and sequentially while a left/right balance in pressure is maintained. Either a bind head screw or
a truss head screw is recommended. Please do not use tapping screw. We recommend using a flat washer
in order to prevent slack. The standard heat sink mounting condition of an STK544UC62K-E is as follows.
Item
Pitch
Screw
Washer
Heat sink
Torque
Grease
Recommended Condition
56.0 ± 0.1mm
Diameter :M3
Bind machine screw, Truss machine screw, Pan machine screw
Plane washer
The size is D : 7mm, d : 3.2mm and t : 0.5mm (Figure 23-b.) JIS B 1256
Material : copper or Aluminum
Warpage (the surface that contacts H-IC) : -50 to +100μm
Screw holes must be countersunk.
No contamination on the heat sink surface that contacts H-IC.
Final tightening : 0.6 to 0.9Nm
Temporary tightening : 20 to 30% of final tightening
Silicon grease
Thickness : 100 to 200μm
Uniformly apply silicon grease to whole back. (Figure 23-c.)
Table 4. Heat sink mounting
Figure 23-a. Mount H-IC on a heat sink
Figure 23-b. Size of washer
Figure 23-c. About uniformly application
steps to mount an HIC on a heat sink
1st: Temporarily tighten maintaining a left/right balance.
2nd : Finally tighten maintaining a left/right balance.
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STK544UC62K-E Application Note
5.4. Mounting and PCB considerations
In designs in which the printed circuit board and the heat sink are mounted to the chassis independently,
use a mechanical design which avoids a gap between H-IC and the heat sink, or which avoids stress to the
lead frame of H-IC by an assembly that a moving H-IC is forcibly fixed to the heat sink with a screw.
Figure 24-a. Fix to heat sink
Maintain a separation distance of at least 1.5 mm between the H-IC case and the printed circuit board. In
particular, avoid mounting techniques in which the H-IC substrate or case directly contacts the printed
circuit board.
Do not mount H-IC with a tilted orientation. This can result in stress being applied to the lead frame and
H-IC substrate could short out tracks on the printed circuit board. Always mount the H-IC vertically. If stress
is given by compulsory correction of a lead frame after the mounting, a lead frame may drop out. Be
careful of this point.
Figure 24-b. Lead frame after the mounting
When designing the PCB layout take care that the bent part portion of the lead frame pins does not
short-circuit to VIA holes or tracks on the PCB.
Figure 24-c. VIA holes or tracks on the PCB
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STK544UC62K-E Application Note
Since the use of sockets to mount H-IC can result in poor contact with H-IC leads, we strongly recommend
making direct connections to PCB.
H-IC modules are flame retardant. However, under certain conditions, it may burn, and poisonous gas may
be generated or it may explode. Therefore, the mounting structure of the H-IC module should also be
flame retardant.
Mounting on a Printed Circuit Board
1. Align the lead frame with the holes in the printed circuit board and do not use excessive force when
inserting the pins into the printed circuit board. To avoid bending the lead frames, do not try to force
pins into the printed circuit board unreasonably.
2. Do not insert H-IC into printed circuit board with an incorrect orientation, i.e. be sure to prevent
reverse insertion. H-IC may be destroyed, exploded, burned or suffer a reduction in their operating
lifetime by this mistake.
3. Do not bend the lead frame.
5.5. Cleaning
H-IC has a structure that is unable to withstand cleaning. As a basic policy, do not clean independent H-IC
or printed circuit boards on which an H-IC is mounted.
6. Package Outline
STK544UC62K-E is SIP23 56*21.8 (SIP1) package. (Single-inline-package)
Every second pin is bent forward to form two rows on the PCB see Figure 25.
6.1. Package outline and dimension and laser marking
missing pin ;3,6,9,11
note2
note3
①
4DB00
STK544UC62K
note1
23
1
③
②
note1:Mark for No.1 pin identification.
note2:The form of a character in this
drawing differs from that of HIC.
note3:This indicates the lot code.
The form of a character in this
drawing differs from that of HIC.
Figure 25.STK544UC62K-E package outline
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STK544UC62K-E Application Note
6.2. Pin Out Description
Pin
Name
Description
1
VB3
High Side Floating Supply Voltage 3
2
W, VS3
Output 3, High Side Floating Supply Offset Voltage 3
3
-
Without pin
4
VB2
High Side Floating Supply Voltage 2
5
V, VS2
Output 2, High Side Floating Supply Offset Voltage 2
6
-
Without pin
7
VB1
High Side Floating Supply Voltage 1
8
U, VS1
Output 1, High Side Floating Supply Offset Voltage 1
9
-
Without pin
10
V+
Positive Bus Input Voltage
11
-
Without pin
Pin
Name
Description
12
VRU
Low Side Emitter Connection – Phase 1
13
VRV
Low Side Emitter Connection – Phase 2
14
VRW
Low Side Emitter Connection – Phase 3
15
HIN1
Logic Input High Side Gate Driver – Phase 1
16
HIN2
Logic Input High Side Gate Driver – Phase 2
17
HIN3
Logic Input High Side Gate Driver – Phase 3
18
LIN1
Logic Input Low Side Gate Driver – Phase 1
19
LIN2
Logic Input Low Side Gate Driver – Phase 2
20
LIN3
Logic Input Low Side Gate Driver – Phase 3
21
T/ITRIP
Temperature Monitor and Shut-down Pin
22
VDD
+15V Main Supply
23
VSS
Negative Main Supply
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