STK5MFU3C1A E D

STK5MFU3C1A-E
Advance Information
30A/600V 2-in-1 PFC and Inverter
Intelligent Power Module
The STK5MFU3C1A-E is a fully-integrated PFC and inverter power
stage consisting of a high-voltage driver, six motor drive IGBT’s, one
PFC IGBT, one PFC rectifier and a thermistor, suitable for driving
permanent magnet synchronous (PMSM) motors, brushless-DC (BLDC)
motors and AC asynchronous motors.
The IGBT’s are configured in a 3-phase bridge with common emitter
connections for the lower legs.
An internal comparator and reference connected to the over-current
protection circuit allows the designer to set individual over-current
protection levels for the PFC and the inverter stages. Additionally, the
power stage has a full range of protection functions including crossconduction protection, external shutdown and under-voltage lockout
functions.
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PACKAGE PICTURE
Features
 Simple thermal design with PFC and inverter stage in one package.
 PFC operating frequency up to 40kHz
 Cross-conduction protection
 Adjustable over-current protection level
 Integrated bootstrap diodes and resistors
SIP23 70x31.1
MARKING DIAGRAM
Typical Applications
Heat Pumps
Home Appliances
Industrial Fans
Industrial Pumps
TBD
HINU
LINU
HINV
LINV
PFCIN
W
V
U
VP2
ORDERING INFORMATION
HS1
Three channel
half-bridge
driver
+
single-ended
PFC driver
HINW
LINW
VP1
PFCL
VDD
VBU
VBV
VBW




LS1
HS2
HS1
HS2
HS3
LS1
LS2
LS3
LS2
Device
Package
Shipping
(Qty / Packing)
STK5MFU3C1A-E
SIP23 70x31.1
(Pb-Free)
7 / Tube
HS3
with
protection
circuits
LS3
N
HVGND
ITRIP
PTRIP
FAULT/ TH
GND
Figure 1. Functional Diagram
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Semiconductor Components Industries, LLC, 2016
March 2016 - Rev. P1
1
Publication Order Number:
STK5MFU3C1A-E/D
STK5MFU3C1A-E
STK5MFU3C1A
PFCL (1)
VP1 (12)
C1
+
CS
From Op-amp
circuit
VP2 (13)
PTRIP (25)
RSPFC
RSINV
From HV
Power
Source
HVGND (15)
ITRIP (26)
N (16)
RC filtering for
HINx, LINx and
PFCIN not
shown.
Recommended
in noisy
environments.
HINU (17)
To Op-amp
circuit
HINV (18)
To Op-amp
circuit
HINW (19)
LINU (20)
LINV (21)
LINW (22)
PFCIN (23)
VBU (9)
+
U (10)
RP
Controller
VBV (6)
+
Motor
FAULT/ TH (24)
V (7)
VBW (3)
VDD (27)
VDD Supply
+
+
W (4)
GND (28)
From 15V
Power
Source
LV Ground
Star connection to HVGND
Figure 2. Application Schematic
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2
STK5MFU3C1A-E
VDD (27)
PFCL (1)
Bootstrap
VBU (9)
Bootstrap
VBV (6)
Bootstrap
VBW (3)
VP1 (12)
PFCIN(23)
VP2 (13)
W (4)
V (7)
U (10)
PFC
Driver
HVGND (15)
N (16)
Level
Shifter
HINU (17)
HINV (18)
HINW (19)
LINU (20)
LINV (21)
LINW (22)
Level
Shifter
Logic
VDD
Logic
VDD
undervoltage
shutdown
Level
Shifter
Logic
FAULT/ TH (24)
ITRIP (26)
VITRIP
Reset after
delay
PTRIP (25)
GND (28)
VPFCTRIP
Figure 3. Simplified Block Diagram
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3
STK5MFU3C1A-E
PIN FUNCTION DESCRIPTION
Pin
Name
Description
1
PFCL
PFC Inductor Connection to IGBT and Rectifier node
3
VBW
High Side Floating Supply voltage for W phase
4
W
V phase output. Internally connected to W phase high side driver ground
6
VBV
High Side Floating Supply voltage for V phase
7
V
V phase output. Internally connected to V phase high side driver ground
9
VBU
High Side Floating Supply voltage for U phase
10
U
U phase output. Internally connected to U phase high side driver ground
12
VP1
Positive PFC Output Voltage
13
VP2
Positive Inverter Output Voltage
15
HVGND
Negative PFC Output Voltage
16
N
Low Side Emitter Connection
17
HINU
Logic Input High Side Gate Driver - Phase U
18
HINV
Logic Input High Side Gate Driver - Phase V
19
HINW
Logic Input High Side Gate Driver - Phase W
20
LINU
Logic Input Low Side Gate Driver - Phase U
21
LINV
Logic Input Low Side Gate Driver - Phase V
22
LINW
Logic Input Low Side Gate Driver – Phase W
23
PFCIN
Logic Input PFC Gate Driver
24
FAULT / TH
FAULT output and thermistor output
25
PTRIP
Current protection pin for PFC
26
ITRIP
Current protection pin for inverter
27
VDD
+15V Main Supply
28
GND
Negative Main Supply
Note: Pins 2, 5, 8, 11 and 14 are not present
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4
STK5MFU3C1A-E
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Rating
Symbol
Conditions
Value
Unit
PFC Section
PFC
IGBT
PFC
Diode
Antiparallel
Diode
Collector-emitter voltage
VCE
PFCL to HVGND
600
V
Repetitive peak collector current
ICP
Duty cycle 10%, pulse width 1ms
TBD
A
Collector current
IC
TBD
A
TBD
A
Maximum power dissipation
PC
TBD
W
Tc=100C
Diode reverse voltage
VRM
VP1 to PFCL
600
V
Repetitive peak forward current
IFP1
Duty cycle 10%, pulse width 1ms
TBD
A
Diode forward current
IF1
TBD
A
TBD
A
Maximum power dissipation
PD1
TBD
W
Tc=100C
Repetitive peak forward current
IFP2
11
A
Diode forward current
IF2
Duty cycle 10%, pulse width 1ms
5
A
Maximum power dissipation
PD2
10
W
Maximum AC input voltage
VAC
Single-phase Full-rectified
264
V
Maximum output voltage
Vo
450
V
Input AC current (steady state)
Iin
In the Application Circuit
(VAC=200V)
TBD
Arms
Supply voltage
VCC
VP2 to N surge < 500V
(Note 3)
450
V
Collector-emitter voltage
VCE max
VP2 to U, V, W or U, V, W to N
600
V
VP2, U, V, W, N terminal current
±30
A
Output current
Io
±15
A
Output peak current
Iop
VP2, U, V, W, N terminal current at
Tc=100C
VP, U, V, W, N terminal current, pulse
width 1ms
TBD
A
Maximum power dissipation
Pd
IGBT per 1 channel
TBD
W
Gate driver supply voltage
VBS
0.3 to +20.0
V
Input signal voltage
VIN
VBU to U, VBV to V, VBW to W, VDD
to GND (Note 4)
HINU, HINV, HINW, LINU, LINV,
LINW, PFCIN
0.3 to VDD
V
FAULT terminal voltage
VFAULT
FAULT terminal
0.3 to VDD
V
ITRIP terminal voltage
VITRIP
ITRIP terminal
0.3 to +10.0
V
PFCTRIP terminal voltage
VPTRIP
PTRIP terminal
1.5 to 2.0
V
Junction temperature
Tj
IGBT, FRD, Gate driver IC
150
C
Storage temperature
Tstg
40 to +125
C
Operating case temperature
Tc
IPM case temperature
20 to +100
C
Tightening torque
MT
Case mounting screws
1.17
Nm
Inverter Section
Gate driver section
Intelligent Power Module
50Hz sine wave AC 1 minute
2000
Vrms
(Note 5)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for
Safe Operating parameters.
This surge voltage developed by the switching operation due to the wiring inductance between VP2 and N terminal.
VBS=VBU to U, VBV to V, VBW to W
Test conditions : AC2500V, 1 s
Isolation voltage
1.
2.
3.
4.
5.
Vis
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5
STK5MFU3C1A-E
RECOMMENDED OPERATING RANGES (Note 6)
Rating
Symbol
Supply voltage
VCC
VP1 to HVGND, VP2 to N
VBS
VDD
Gate driver supply voltage
ON-state input voltage
VIN(ON)
OFF-state input voltage
VIN(OFF)
PWM frequency(PFC)
fPWMp
Min
Typ
Max
Unit
0
280
400
V
VBU to U, VBV to V, VBW to W
12.5
15
17.5
V
VDD to GND (Note 6)
13.5
15
16.5
V
HINU, HINV, HINW, LINU, LINV, LINW,
PFCIN
2.5
-
5.0
V
0
-
0.3
V
1
-
40
kHz
PWM frequency(Inverter)
fPWMi
Dead time
DT
Turn-off to Turn-on (external)
Allowable input pulse width
PWIN
ON and OFF
Tightening torque
6.
‘M4’ type screw
1
-
20
kHz
1.5
-
-
μs
1
-
-
μs
0.79
-
1.17
Nm
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to
stresses beyond the Recommended Operating Ranges limits may affect device reliability.
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6
STK5MFU3C1A-E
ELECTRICAL CHARACTERISTICS
Tc=25C
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
PFC Section
Collector-emitter cut-off current
VCE=600V
ICE
-
-
0.2
mA
Reverse leakage current (PFC Diode)
VR=600V
IR
-
-
0.1
mA
-
1.6
2.2
V
-
1.4
-
V
-
2.8
3.4
V
-
1.7
-
Collector-emitter saturation voltage
Diode forward voltage (PFC Diode)
Diode forward voltage (Anti-parallel Diode)
Junction to case thermal resistance
IC=40A, Tj=25°C
VCE(sat)
IC=20A, Tj=100°C
IF=40A, Tj=25°C
VF1
IF=20A, Tj=100°C
IF=5A, Tj=25°C
VF2
-
1.8
2.4
V
IGBT
θj-c(T)
-
1.0
-
°C/W
PFC Diode
θj-c(D)
-
1.8
-
°C/W
tON
-
0.4
-
μs
tOFF
-
0.8
-
μs
trr
-
70
-
ns
-
-
0.1
mA
Switching characteristics
Switching time
IC=40A, VP=300V, Tj=25C
Diode reverse recovery time
Inverter section
Collector-emitter leakage current
VCE=600V
ICE
Bootstrap diode reverse current
VR(DB)=600V
IR(BD)
Collector to emitter saturation voltage
Diode forward voltage
IC=30A, Tj=25C
VCE(SAT)
IC=15A, Tj=100C
IF=30A, Tj=25C
VF
-
-
0.1
mA
-
1.9
2.5
V
-
1.6
-
V
-
2.2
2.7
V
-
1.8
-
V
Junction to case thermal resistance
IGBT
θj-c(T)
-
1.9
-
C/W
Junction to case thermal resistance
FRD
θj-c(D)
-
2.6
-
C/W
Switching time
IC = 30A, VCC=300V, Tj=25C
tON
-
0.6
-
μs
tOFF
-
0.9
-
μs
Reverse bias safe operating area
Ic=30A, VCE=450V
RBSOA
Short circuit safe operating area
VCE=400V
SCSOA
Allowable offset voltage slew rate
U, V, W to N
dv/dt
7.
IF=15A, Tj=100C
Full Square
4
-
-
μs
50
-
50
V/ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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7
STK5MFU3C1A-E
ELECTRICAL CHARACTERISTICS
Tc=25C
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
-
0.08
0.4
mA
Driver Section
Gate driver consumption current
High level Input voltage
Low level Input voltage
VBS=15V (Note 4), per driver
ID
VDD=15V, total
ID
-
0.85
2.4
mA
HINU, HINV, HINW, LINU, LINV, LINW,
PFCIN to GND
VIN H
2.5
-
-
V
VIN L
-
-
0.8
V
Logic 1 input current
VIN=+3.3V
IIN+
-
100
143
μA
Logic 0 input current
VIN=0V
IIN-
-
-
2
μA
Bootstrap diode forward voltage
IF=0.1A
VF(DB)
-
0.8
-
V
RBC
-
22
-
Ω
Bootstrap circuit resistance
Resistor value for common boot charge
line
Resister values for separate boot
charge lines
RBS
-
33
-
Ω
FAULT terminal sink current
FAULT : ON / VFAULT=0.1V
FAULT clearance delay time
-
2
-
mA
FLTCLR
IoSD
1.0
1.85
2.7
ms
ITRIP threshold voltage
ITRIP to GND
VITRIP
0.44
0.49
0.54
V
PTRIP threshold voltage
PTRIP to GND
VPTRIP
0.37
0.31
0.25
V
VDD and VBS supply undervoltage
VCCUV+
10.5
11.1
11.7
V
VBSUV+
positive going input threshold
VDD and VBS supply undervoltage
VCCUV10.3
10.9
11.5
V
VBSUVnegative going input threshold
VDD and VBS supply undervoltage Iockout
VCCUVH
0.14
0.2
V
VBSUVH
hysteresis
8. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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8
STK5MFU3C1A-E
APPLICATIONS INFORMATION
Input / Output Timing Chart
VBS undervoltage protection reset signal
HIN
LIN
VDD undervoltage protection reset voltage (Note 2)
VBS undervoltage protection reset voltage (Note 3)
VDD
Voltage ≥ 0.54V
VBU,VBV,VBW
Note 4
Voltage < 0.44V
ITRIP
PTRIP
Voltage ≤ -0.37V
FAULT driven
output
Cross-conduction prevention period (Note 1)
High side IGBT
Gate Drive
Low side IGBT
Gate Drive
Automatic reset after protection (FAULT clearance delay time)
Figure 18. Input / Output Timing Chart
Notes
1. This section of the timing diagram shows the effect of cross-conduction prevention.
2. This section of the timing diagram shows that when the voltage on VDD decreases sufficiently all gate output signals will go low,
switching off all six IGBTs. When the voltage on VDD rises sufficiently, normal operation will resume.
3. This section shows that when the bootstrap voltage on VBU (VBV, VBW) drops, the corresponding high side output U (V, W) is
switched off. When the voltage on VBU (VBV, VBW) rises sufficiently, normal operation will resume.
4. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBT’s are turned off. Normal operation resumes
later after the over-current condition is removed. Similarly, when the voltage on PTRIP exceeds the threshold, all IGBT’s are
turned off. Normal operation resumes later after the over-current condition is removed
Input / Output Logic Table
INPUT
OUTPUT
HIN
LIN
ITRIP
PTRIP
High side IGBT
Low side IGBT
U,V,W
FAULT
H
L
L
L
ON (Note 5)
OFF
VP
OFF
L
H
L
L
OFF
ON
N
OFF
L
L
L
L
OFF
OFF
High Impedance
OFF
H
H
L
L
OFF
OFF
High Impedance
OFF
X
X
H
X
OFF
OFF
High Impedance
ON
X
X
X
H
OFF
OFF
High Impedance
ON
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STK5MFU3C1A-E
Thermistor characteristics
Parameter
Resistance
B-Constant (25 to 50℃)
Symbol
Condition
Min
Typ
Max
Unit
R25
Tth=25℃
99
100
101
kΩ
R100
Tth=100℃
5.18
5.38
5.60
kΩ
4208
4250
4293
K
+125
℃
B
40
Temperature Range
Thermistor temperature(Tth) - Thermistor resistance(RTH)
RTH, Thermistor resistance (kΩ)
10000
min
typ
max
1000
100
10
1
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110 120 130
Tth, Thermistor temperature (C)
Figure 19. Thermistor Resistance versus Thermistor Temperature
Thermistor temperature(Tth) - TH to GND voltage characteristic(VTH)
VTH, TH-GND terminal voltage (V)
6.0
min
typ
max
5.0
4.0
3.0
2.0
1.0
0.0
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90 100 110 120 130
Tth, Thermistor temperature (C)
Figure 20. Thermistor Voltage versus Thermistor Temperature
Conditions: RTH=39kΩ, pull-up voltage 5.0V (see Figure 2)
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STK5MFU3C1A-E
Signal inputs
Calculation of bootstrap capacitor value
Each signal input has a pull-down resistor. An
additional pull-down resistor of between 2.2kΩ and
3.3kΩ is recommended on each input to improve noise
immunity.
The bootstrap capacitor value CB is calculated using
the following approach. The following parameters
influence the choice of bootstrap capacitor :

FAULT/ TH pin
The FAULT pin is connected to an open-drain FAULT
output requiring a pull-up resistor. If the pull-up
voltage is 5V, use a pull-up resistor with a value of
6.8kΩ or higher. If the pull-up voltage is 15V, use a
pull-up resistor with a value of 20kΩ or higher. The
FAULT output is triggered if there is a VDD
undervoltage or an overcurrent condition on either the
PFC or inverter stages.
VBS: Bootstrap power supply.
15V is recommended.
QG: Total gate charge of IGBT at VBS=15V.
266nC
UVLO: Falling threshold for UVLO.
Specified as 12V.
IDMAX: High side drive power dissipation.
Specified as 0.4mA
TONMAX: Maximum ON pulse width of
high side IGBT.




The FAULT/ TH pin is also connected to a grounded
thermistor. Thermal characteristics are shown in this
datasheet for a pull up value of 39kΩ.
Capacitance calculation formula:
CB = (QG + IDMAX * TONMAX)/(VBS  UVLO)
Undervoltage protection
CB is recommended to be approximately 3 times the
value calculated above. The recommended value of CB
is in the range of 1 to 47μF, however, the value needs
to be verified prior to production. When not using the
bootstrap circuit, each high side driver power supply
requires an external independent power supply. If the
capacitors selected are 47 μF or more, a series resistor
of 20Ω should be added in series with the three
capacitors to limit the current. The resistors should be
inserted between VBU and U, VBV and V and VBW
and W.
If VDD goes below the VDD supply undervoltage
lockout falling threshold, the FAULT output is
switched on. The FAULT output stays on until VDD
rises above the VDD supply undervoltage lockout
rising threshold. The hysteresis is approximately
200mV.
Overcurrent protection
An over-current condition is detected if the voltage on
the ITRIP/PTRIP pin is larger than the reference
voltage. There is a blanking time of typically 350ns to
improve noise immunity. After a shutdown
propagation delay of typically 0.6 us, the FAULT
output is switched on.
Bootstrap Capacitance Cb [μF]
80
The over-current protection threshold should be set to
be equal or lower to 2 times the module rated current
(IO).
An additional fuse is recommended to protect against
system level or abnormal over-current fault conditions.
60
40
20
0
0.1
Capacitors on High Voltage and VDD supplies
1
10
100
1000
Tonmax [ms]
Both the high voltage and VDD supplies require an
electrolytic capacitor and an additional high frequency
capacitor. The recommended value of the high
frequency capacitor is between 100nF and 10 μF.
Figure 21. Bootstrap capacitance versus Tonmax
Minimum input pulse width
When input pulse width is less than 1μs, an output may
not react to the pulse. (Both ON signal and OFF signal)
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11
STK5MFU3C1A-E
Mounting Instructions
Item
Recommended Condition
Pitch
70.0±0.1mm (Please refer to Package Outline Diagram)
Screw
diameter : M4
Bind machine screw, Truss machine screw, Pan machine screw
Washer
Plane washer
The size is D:9mm, d:4.3mm and t:0.8mm JIS B 1256
Heat sink
Material: Aluminum or Copper
Warpage (the surface that contacts IPM ) : 50 to 100 μm
Screw holes must be countersunk.
No contamination on the heat sink surface that contacts IPM.
Torque
Temporary tightening : 20 to 30 % of final tightening on first screw
Temporary tightening : 20 to 30 % of final tightening on second screw
Final tightening : 0.79 to 1.17Nm on first screw
Final tightening : 0.79 to 1.17Nm on second screw
Grease
Silicone grease.
Thickness : 100 to 200 μm
Uniformly apply silicon grease to whole back.
Thermal foils are only recommended after careful evaluation. Thickness, stiffness and
compressibility parameters have a strong influence on performance.
Screw
First
Second
t
Washer
Module
Module
Grease
Heatsink
showing
warpage
D
d
+
‐
Mounting components
Washer details
Silicone grease
Recommended
Aluminum
substrate
Not recommended
Thermal grease must be spread
evenly (left is correct)
Figure 22. Module Mounting details: components; washer drawing; need for even spreading of thermal grease
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12
STK5MFU3C1A-E
TEST CIRCUITS
■ ICE, IR(DB)
U+
V+
W+
U-
V-
PFC
IGBT
W-
A
13
13
13
10
7
4
1
B
10
7
4
16
16
16
15
U+,V+,W+ : High side phase
U-,V-,W- : Low side phase
9
VBS=15V
10
ICE, IR
A
A
6
VBS=15V
VCE, VR
7
3
VBS=15V
4
U(DB)
V(DB)
W(DB)
PFC
Diode
A
9
6
3
12
B
28
28
28
1
27
VDD=15V
B
28, 15, 16
Figure 23. Test Circuit for ICE
■ VCE(sat) (Test by pulse)
U+
V+
W+
U-
V-
W-
PFC
IGBT
A
13
13
13
10
7
4
1
B
10
7
4
16
16
16
15
C
17
18
19
20
21
22
23
9
VBS=15V
10
A
6
VBS=15V
7
V
3
VBS=15V
IC
VCE(sat)
4
27
VDD=15V
C
5V
B
28, 15, 16
Figure 24. Test circuit for VCE(SAT)
■ VF (Test by pulse)
U+
V+
W+
U-
V-
W-
A
13
13
13
10
7
4
B
10
7
4
16
16
16
A
V
U(DB)
V(DB)
W(DB)
PFC
Diode
Anti-parallel
Diode
A
9
6
3
12
1
B
28
28
28
1
15
B
Figure 25. Test circuit for VF
■ ID
VBS U+
VBS V+
VBS W+
VDD
A
9
6
3
27
B
10
7
4
28
ID
A
A
VD*
B
Figure 26. Test circuit for ID
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IF
STK5MFU3C1A-E
■ VITRIP, VPTRIP
VITRIP(U-)
VPTRIP
A
10
1
B
16
15
C
20
23
D
26
A
VDD=15V
27
V
25
Input Signal
C
VITRIP/VPFCTRIP
D
Io
B
28, 15, 16
Input Signal
(0 to 5V)
Figure 27. Test circuit for ITRIP.PTRIP
ITRIP
/PFCTRIP
lo
■ Switching time (The circuit is a representative example of the lower side U phase.)
U+
V+
W+
U-
V-
W-
PFC
IGBT
A
13
13
13
13
13
13
12
B
16
16
16
16
16
16
15
C
10
7
4
13
13
13
VBS=15V
VBS=15V
16
16
16
10
7
4
1
E
17
18
19
20
21
22
23
10
A
6
C
7
12
D
9
VBS=15V
4
VDD=15V
Input Signal
VCC
D
27
E
28, 15, 16
Input Signal
(0 to 5V)
CS
3
B
Io
Figure 28. Test circuit for switching time
lo
90%
10%
tON
tOFF
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14
STK5MFU3C1A-E
Package Dimensions
unit : mm
SIP23 70x31.1
CASE 127DG
ISSUE O
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