LV8829LFQA
Brushless Motor Drive
PWM Driver
Application Note
http://onsemi.com
Overview
The LV8829LFQA is a PWM-type driver IC designed for 3-phase brushless motors. The rotational speed
can be controlled by inputting the PWM pulse from the outside, and changing Duty. The IC incorporates a
latch-type constraint protection circuit.
Function
IO max = 1.5A (built-in output Tr)
Speed control and synchronous rectification using direct PWM input (supports 3.3V inputs)
1-Hall FG output
Latch type constraint protection circuit (the latch is released by S/S and F/R.)
Forward/reverse switching circuit, Hall bias pin
Power save circuit (Power save in stop mode)
Current limiter circuit, Low-voltage protection circuit, Thermal Shutdown circuit
Charge pump circuit, 5V regulator output.
Start/stop circuit (short brake when motor is to be stopped)
Typical Applications
Laser Beam Printers
Plain Paper Copiers
Industrial Printers
White Goods
Security cameras
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Supply voltage
Symbol
Conditions
Ratings
Unit
VCC max
VCC pin
36
V
VG max
VG pin
42
V
Output current
IO max
t 500ms *1
1.5
A
Allowable power dissipation
Pd max
Mounted on a circuit board.*2
Junction temperature
Tj max
Operating temperature
Storage temperature
1.35
W
150
C
Topr
-40 to +80
C
Tstg
-55 to +150
C
*1 : Tj cannot exceed Tj max = 150C
*2 : Specified circuit board : 40mm 50mm 0.8mm, glass epoxy (four-layer board)
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
December, 2013
1/13
LV8829LFQA Application Note
Package Dimensions
Unit: mm(typ)
BOTTOM VIEW
SIDE VIEW
(2.5)
24
0.4
4.0
(2.5)
4.0
1 2
2 1
0.25
0.8 MAX
0.5
(0.75)
0.035
SIDE VIEW
Pd max - Ta
2
Allowable power dissipation, Pd max -- W
TOP VIEW
Specified board : 40 × 50 × 0.8mm3
glass epoxy
(four-layer board)
1.5
1.35
1
0.76
0.5
0
--40
--20
0
20
40
60
80
100
Ambient temperature, Ta -- °C
SANYO : VQFN24N(4.0X4.0)
Caution: The package dimension is a reference value, which is not a guaranteed value.
Recommended Soldering Footprint
(unit: mm)
Reference symbol
VQFN24N
eD
3.7
eE
3.7
e
0.50
b3
0.30
l1
0.70
X
(2.5)
Y
(2.5)
2/19
HB
PWMIN
CSD
F/R
FG
S/S
LV8829LFQA Application Note
24
23
22
21
20
19
IN3+
2
17
RF
IN2-
3
16
OUT2
IN2+
4
15
OUT3
IN1-
5
14
OUT1
IN1+
6
13
VG
8
SGND
VREG
7
9
10
11
12
VCC2
PGND
VCC1
18
CP1
1
CP2
IN3-
Figure1. Pin Assignment
F/R input
PWMIN input
F/R
F/R
S/S input
PWMIN
S/S
PWMIN
S/S
VREG
CSD
CSD
OSC
VCC
LVSD
VCC1
VG
TSD
CONTROL
CIRCUIT
LDA
CHARGE
PUMP
CP1
CP2
3FG
FG
+
VCC2
MOSC
FG output
VREG
OUT1
FG
DRIVER
HALL HYS AMP
IN1+ IN1- IN2+ IN2- IN3+ IN3-
HB
CURF
LIM
HB
OUT2
OUT3
RF
SGND PGND
VCC
Figure2. Block Diagram
3/19
LV8829LFQA Application Note
Recommended Operating Conditions at Ta 25C
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
Supply voltage range
VCC
8.0
35
V
5V constant voltage output current
IREG
0
-10
mA
HB pin output current
IHB
0
-200
A
FG pin applied voltage
VFG
0
6
V
FG pin output current
IFG
0
10
mA
Electrical Characteristics at Ta 25C, VCC = 24V
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
Supply current 1
ICC1
3.3
4.0
mA
Supply current 2
ICC2
At stop
0.7
0.8
mA
Low-side output ON resistance
RON (L1)
High-side output ON resistance
RON (H1)
IO = 1.0A
0.47
0.65
IO = -1.0A
0.67
0.9
Low-side output leak current
IL (L)
High-side output leak current
IL (H)
50
A
Low-side diode forward voltage
VD (L1)
ID = -1.0A
1.0
1.2
V
High-side diode forward voltage
VD (H1)
ID = 1.0A
1.1
1.3
V
Output voltage
VREG
IO = -5mA
5.1
5.4
V
Line regulation
V (REG1)
VCC = 8 to 35V, IO = -5mA
50
mV
Load regulation
V (REG2)
IO = -5m to -10mA
100
mV
Output block
A
-50
5V Constant-voltage Output
4.8
Hall Amplifier
A
Input bias current
IB (HA)
Common-mode input voltage range 1
VICM1
When using Hall elements
-2
Common-mode input voltage range 2
VICM2
At one-side input bias (Hall IC application)
Hall input sensitivity
VHIN
SIN wave
Hysteresis width
VIN (HA)
9
20
35
mV
Input voltage Low High
VSLH
3
9
16
mV
Input voltage High Low
VSHL
-19
-11
-5
mV
High level output voltage
VOH (CSD)
2.7
3.0
3.3
V
Low level output voltage
VOL (CSD)
0.9
1.1
1.3
V
0.3
VREG-1.7
V
0
VREG
V
80
mVp-p
CSD oscillator circuit
Amplitude
V (CSD)
1.6
1.9
2.2
Vp-p
External capacitor charge current
ICHG1 (CSD) VCHG1 = 2.0V
-14
-11.5
-9
A
External capacitor discharge current
ICHG2 (CSD) VCHG2 = 2.0V
9.5
12
14.5
A
Oscillation frequency
f (CSD)
C = 0.022F (Design target value)
130
Hz
VCC+4.5
V
Charge pump output (VG pin)
Output voltage
VGOUT
CP1 pin
Output ON resistance (High level)
VOH (CP1)
ICP1 = -2mA
500
700
Output ON resistance (Low level)
VOL (CP1)
ICP1 = 2mA
350
500
Charge pump frequency
f (CP)
82
103
124
kHz
f (PWM)
41
51.5
62
kHz
0.19
0.21
0.23
V
150
165
180
C
Internal PWM frequency
Oscillation frequency
Current limiter operation
Limiter voltage
VRF
Thermal shutdown operation
Thermal shutdown operation
TSD
*Design target value (junction temperature)
TSD
*Design target value (junction temperature)
temperature
Hysteresis width
30
C
Continued on next page.
4/19
LV8829LFQA Application Note
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
HB pin
Output voltage
VHB
IHB = -100A
3.4
3.6
3.8
V
3.95
4.15
4.35
V
0.2
0.3
0.4
V
40
60
10
A
Low-voltage protection (5V constant-voltage output detection)
Operation voltage
VSD
Hysteresis width
VSD
FG pin (3FG pin)
Output ON resistance
VOL (FG)
IFG = 5mA
Output leak current
IL (FG)
VO = 5V
S/S pin
High level input voltage
VIH (SS)
2.0
VREG
V
Low level input voltage
VIL (SS)
0
1.0
V
Input open voltage
VIO (SS)
VREG-2.2
VREG-2.0
VREG-1.8
V
0.25
0.33
0.4
V
45
60
75
A
-115
-90
-65
A
kHz
Hysteresis width
VIS (SS)
High level input current
IIH (SS)
VSS = VREG
Low level input current
IIL (SS)
VSS = 0V
PWMIN pin
Recommended input frequency
f(PWIN)
0.5
60
High level input voltage
VIH (PWIN)
2.0
VREG
V
1.0
V
Low level input voltage
VIL (PWIN)
0
Input open voltage
VIO (PWIN)
VREG-2.2
VREG-2.0
VREG-1.8
V
Hysteresis width
VIS (PWIN)
0.25
0.33
0.4
V
High level input current
IIH (PWIN)
VPWIN = VREG
Low level input current
IIL (PWIN)
VPWIN = 0V
45
60
75
A
-115
-90
-65
A
F/R pin
High level input voltage
VIH (FR)
*Design target value
2.0
VREG
V
Low level input voltage
VIL (FR)
*Design target value
0
1.0
V
Input open voltage
VIO (FR)
Hysteresis width
VIS (FR)
*Design target value
High level input current
IIH (FR)
VF/R = VREG
Low level input current
IIL (FR)
VF/R = 0V
VREG-2.2
VREG-2.0
VREG-1.8
V
0.25
0.33
0.4
V
45
60
75
A
-115
-90
-65
A
* : Design target value and no measurement is made.
6
5
ICC(mA)
4
3
2
ICC
1
0
0
10
20
30
40
VCC (V)
Figure 3. VCC Current Drain
vs VCC Voltage
5/19
1
1
0.8
0.8
0.6
0.6
0.4
OUT1
0.2
OUT2
0
OUT3
0
0.5
1
1.5
Ron (Ω)
Ron (Ω)
LV8829LFQA Application Note
OUT1
0.4
OUT2
0.2
OUT3
0
2
0
0.5
Iout (mA)
2
Figure 5. High-side Output on Resistance
vs Output Current (VM= 24V)
1.4
5.5
1.2
5
1
0.8
VREG (V)
VD (V)
1.5
Iout (mA)
Figure 4. Low-side Output on Resistance
vs Output Current (VM= 24V)
0.6
0.4
VD(H1)
0.2
VD(L1)
0
0
0.5
1
1.5
4.5
4
3.5
3
2
0
10
Iout (A)
20
30
40
VCC (V)
Figure 6. Diode Forward Voltage
vs Output Current
Figure 7. VREG Output Voltage
vs VCC Voltage (Io=-5mA)
4
45
40
35
30
25
20
15
10
5
0
3.8
VIHB (V)
VG (V)
1
3.6
3.4
3.2
3
0
10
20
30
40
VCC (V)
‐250
‐200
‐150
‐100
‐50
0
IHB (uA)
Figure 8. VG Output Voltage
vs VCC Voltage
Figure 9. HB pin output Voltage
vs HB current
60
50
IIN (uA)
40
30
20
10
0
0
1
2
3
4
5
VIN (V)
Figure 10. Logic Pin Input Current
vs Input Voltage
6/19
LV8829LFQA Application Note
Pin Functions
Pin No.
1
2
3
4
5
6
Pin Name
IN3IN3+
IN2IN2+
IN1IN1+
Pin function
Equivalent Circuit
Hall input pin.
VREG
•High when IN+ IN-.
Low in reverse relationship.
The input amplitude of over 100mVp-p
(differential) is desirable in the Hall
inputs. Insert a capacitor between the
IN+ and IN- pins if the noise on the Hall
signal is a problem.
1
3
5
500Ω
500Ω
2
4
6
Please refer to P.11-12 for detail.
7
SGND
8
VREG
Control circuit block ground pin.
5V regulator output pin (control circuit
power supply).
VCC
Insert a capacitor between this pin and
50Ω
ground for stabilization.
About 0.1F is necessary.
(Refer to P.11 “5” is Low-voltage
Protection Circuit, P.12 “10” is VREG
8
Stabilization.)
9
CP2
Charge pump capacitor connection pin.
10
CP1
Insert capacitor between CP1 and CP2.
11
VCC1
VCC2
For Control (Pin 11) and for output (Pin
12
12) power pin.
Insert a capacitor between this pin and
ground to prevent the influence of noise,
etc.
(Refer to P.12 “9” is Power Supply
Stabilization.)
13
VG
Charge pump output pin.
(Upper-side FET gate power supply)
VCC
Insert a capacitor between this pin and
VCC.
(Refer to P.12 “11” is Charge pump
300Ω
Circuit.)
10
200Ω
CP
CG
13
9
Continued on next page.
7/19
LV8829LFQA Application Note
Continued from preceding page.
Pin No.
Pin Name
Pin function
14
OUT1
Output pin.
15
OUT3
PWM is controlled by the upper-side
16
OUT2
FET.
Equivalent Circuit
VCC
14 15 16
17
17
RF
Output current detection pin.
VREG
Insert a low resistance resistor (Rf)
between this pin and ground.
(Refer to P.10 “2” is Current Limiter
Circuit.)
17
18
PGND
Out circuit block ground pin.
19
S/S
Pin to select the start/stop type.
Stop = High or open
5kΩ
VREG
Start = Low
(Refer to P.12 “8” is Power Saving
50kΩ
Circuit.)
5kΩ
19
75kΩ
20
FG
1-Hall FG signal output pin.
Open drain output.
VREG
20
Continued on next page.
8/19
LV8829LFQA Application Note
Continued from preceding page.
Pin No.
21
Pin Name
F/R
Pin function
Pin to select the forward/reverse type.
This pin goes to the high level when
Equivalent Circuit
VREG
open.
50kΩ
5kΩ
21
75kΩ
22
CSD
Pin to set the constraint protection circuit
operating time and initial reset pulse.
VREG
Insert a capacitor between this pin and
ground.
Insert a resistor in parallel with the
capacitor if the protection circuit is not to
500Ω
be used.
(Refer to P.11 “4” is Constraint
22
Protection Circuit.)
23
PWMIN
External PWM input pin.
Apply an external PWM input signal to
VREG
this pin.
(Input frequency range is from 0.5 to
50kΩ
60kHz.)
PWM ON = Low
5kΩ
PWM OFF = High or open
(Refer to P.11 “3” is Speed control
23
method.)
75kΩ
24
HB
HALL bias pin (3.6V output).
Connect an NPN transistor.
(Refer to P.11 “7” Hall Input Signal.)
VREG
300Ω
250Ω
24
9/19
LV8829LFQA Application Note
Three-phase logic truth table (IN = “High” indicates the state where IN+ > IN-.)
("H" = SOURCE, "L" = SINK, and "M" = output OFF are shown with OUT1 to 3.)
F/R = H
Output
F/R = L
IN1
IN2
IN3
IN1
IN2
IN3
OUT1
OUT2
OUT3
H
L
H
L
H
L
L
H
M
H
L
L
L
H
H
L
M
H
H
H
L
L
L
H
M
L
H
L
H
L
H
L
H
H
L
M
L
H
H
H
L
L
H
M
L
L
L
H
H
H
L
M
H
L
IN1
IN2
IN3
FG
H
L
H
L
H
L
L
L
H
H
L
L
L
H
L
H
L
H
H
H
L
L
H
H
FG output
S/S pin, PWMIN pin
Input state
S/S pin
PWMIN pin
High or Open
Stop (short brake)
Output OFF
Low
Start
Output ON
CSD function
When the S/S pin is in a STOP state
When the F/R pin is switched
When 0% duty is detected at the PWMIN pin input
When low-voltage condition is detected
When TSD condition is detected
Protection released and count reset (Initial reset)
Protection released and count reset
Protection released and count reset
Protection released and count reset (Initial reset)
Stop counting
Description of LV8829LFQA
1. Output Drive Circuit
This IC adopts a direct PWM drive method to reduce power loss in the output. It regulates the drive force of
the motor by changing the output on duty. The output PWM switching is performed by the upper-side output
transistor.
The current regeneration route during the normal PWMOFF passes through the parasitic diode of the output
DMOS. This IC performs synchronous rectification, and is intended to reduce heat generation compared to
diode regeneration.
2. Current Limiter Circuit
The current limiter circuit limits the output current peak value to a level determined by the equation I =
VRF/Rf (VRF = 0.21V (typical), Rf: current detection resistor). This circuit suppresses the output current by
reducing the output on duty.
The current limiter circuit has an operation delay (approx. 700ns) to detect reverse recovery current flowing
in the diode due to the PWM operation, and prevent a malfunction of the current limiting operation. If the coil
resistance of the motor is small, or the inductance is low, the current at startup (the state in which there is no
back electromotive force generated in the motor) will change rapidly. As a result, the operation delay may
sometimes cause the current limiting operation to take place at a value above the set current. In such a case,
it is necessary to set the current limit value while taking into consideration the increase in current due to the
delay.
* Regarding the PWM frequency in the current limiter circuit
The PWM frequency in the current limiter circuit is determined by the internal reference oscillator, and is
approximately 50 kHz.
10/19
LV8829LFQA Application Note
3. Speed control method
Pulses are input to the PWMIN pin, and the output can be controlled by varying the duty cycle of these
pulses.
When a low-level input voltage is applied to the PWMIN pin, the output at the PWM side (upper side) is set to
ON.
When a high-level input voltage is applied to the PWMIN pin, the output at the PWM side (upper side) is set
to OFF.
If it is necessary to input pulses using inverted logic, this can be done by adding an external transistor (NPN).
When the input to the PWMIN pin remains high-level for a certain period, the IC judges that the duty is 0%,
causing the CSD circuit count to be reset and the output from the HB pin to become low level.
4. Constraint Protection Circuit
The LV8829LFQA includes a constraint protection circuit for protecting the IC and the motor in a motor
constraint mode.
This circuit operates when the motor is in an operation condition and the Hall signal does not switch over for
a certain period. Note that while this constraint protection is operating, the upper-side output transistor will be
OFF.
Time setting is performed according to the capacitance of the capacitor connected to the CSD pin.
Set time (s) 90 C (F)
When a 0.022F capacitor is connected, the protection time becomes approximately 2.0 seconds. The set
time must be selected to a value that provides adequate margin with respect to the motor startup time.
Conditions for releasing the constraint protection state:
• When the S/S pin is in a STOP state
Protection released and count reset(Initial reset)
• When the F/R pin is switched
Protection released and count reset
• When 0% duty is detected at the PWMIN pin input Protection released and count reset
• When low-voltage condition is detected
Protection released and count reset (Initial reset)
(• When TSD condition is detected
Stop counting)
The CSD pin also functions as the initial reset pulse generation pin. If it is connected to ground, the logic
circuit will go into a reset state, preventing speed control from taking place. Consequently, when not using
constraint protection, connect a resistor of approximately 220k and a capacitor of about 4700pF in parallel
to ground.
5. Low-voltage Protection Circuit
The LV8829LFQA incorporates a comparator that uses the band gap voltage as the reference. The circuit
monitors the voltage at the VREG pin (5V) while the S/S pin is low and activates the protection circuit when
the voltage at the VREG pin falls below 4.15V (typ.).
When this happens, the state of the output transistors for all phases set to OFF.
In order to ensure that the IC does not exhibit any unstable behavior when the VREG voltage has increased
or decreased around 4.15V, a hysteresis of 0.3V (typ.) is provided. As a result, when the VREG voltage
recovers to 4.45V (typ.) after the low-voltage protection circuit has been activated, all output transistors
return to their operating state.
6. Thermal shutdown Circuit
When the IC junction temperature exceeds 165°C (design target value), the thermal shutdown circuit is
activated, and all the output transistors are set to OFF.
When the IC junction temperature goes below the hysteresis temperature of 30°C (design target value) or
more, all the output transistors return to their operating state.
However, as the thermal shutdown circuit is activated only when the junction temperature of the IC has
exceeded the rating, its activation does not constitute a guarantee that the product that incorporates this
circuit will be protected from damage or destruction.
7. Hall Input Signal
A pulse input with the amplitude in excess of the hysteresis (35mV maximum) is required for the Hall inputs.
It is desirable that the amplitude of the Hall input signal be 100mVp-p or more in consideration of the effect of
noise and phase displacement.
If disturbances to the output waveform (during phase switching) occur due to noise, connect a capacitor
between the Hall input pins to prevent such disturbances. In the constraint protection circuit, the Hall input is
utilized as a judgment signal. Although the circuit ignores a certain amount of noise, caution is necessary.
If all three phases of the Hall input signal go to the same input state (HHH or LLL), the outputs are all set to
the OFF state.
11/19
LV8829LFQA Application Note
If the Hall IC is used, fixing one side of the inputs (either the + or – side) at a voltage within the
common-mode input voltage range (between 0.3V and VREG-1.7V) allows the other input side to be used
as an input over the 0V to VREG range.
(1)
Method of connecting Hall elements
VCC
Type (1) connection (three Hall elements connected in series)
Advantages
HB
Because the current flowing in Hall elements can be shared by
3V Constant-voltage Output
connecting the Hall elements in series, the current consumption is
less than that of a parallel-connected arrangement.
The use of a current limiting resistor can be eliminated.
Fluctuations of amplitude with temperature are reduced.
Disadvantages
Because only 1V can be applied to one Hall device, there is a
possibility that adequate amplitude cannot be obtained.
The current flowing in the Hall elements varies with temperature.
HALL element unevenness (input resistance in particular) is easy
to influence the amplitude.
(2)
Type (2) connection (three Hall elements connected in parallel)
Advantages
The current flowing in the Hall elements can be determined by the
current limiting resistor.
The voltage applied to the Hall elements can be varied, enabling
adequate amplitude to be obtained.
Disadvantages
Because it is necessary to supply current separately to each Hall
element, the current consumption becomes large.
A current limiting resistor is necessary.
The amplitude varies with temperature.
VCC
HB
3V Constant-voltage Output
Figure11. Method of connecting Hall elements
HB pin
The HB pin is used for cutting off the current flowing in the Hall elements during standby (for saving
electricity).
The output from the HB pin is set to OFF in the following cases.
When the S/S pin is in a STOP state
When 0% duty is detected at the PWMIN pin input
8. Power Saving Circuit (Start/Stop circuit)
To save power when the LV8829LFQA is in the stop state, most of the circuit is stopped, aiming at reducing
current consumption. If the Hall bias pin is used, the current consumption in the power-saving mode will be
approximately 700A. Even in the power-saving mode, a 5V regulator voltage is output. Also, in the
power-saving mode, the IC is in a short break state. (lower-side shorted)
9. Power Supply Stabilization
This IC generates a large output current, and employs a switching drive method, so the power supply line
level can be disturbed easily. For this reason, it is necessary to connect a capacitor (electrolytic) of sufficient
capacitance between the VCC pin and ground to ensure a stable voltage. Connect the ground side of the
capacitor to the PGND pin, which is the power ground, as close as possible to the pin. If it is not possible to
connect a capacitor of sufficiently large capacitance close to the pin, connect a ceramic capacitor of
approximately 0.1F to the vicinity of the pin.
If diodes are inserted in the power supply line to prevent IC destruction resulting from reverse-connecting the
power supply, the power supply lines are even more easily disrupted. And even larger capacitor is required.
10. VREG Stabilization
To stabilize the VREG voltage, which is the power supply for the control circuit, connect a capacitor of 0.1F
or larger.
Connect the ground of this capacitor as close as possible to the control block ground (SGND pin) of the IC.
12/19
LV8829LFQA Application Note
11. Charge pump Circuit
The voltage is stepped-up by the charge pump circuit, causing the gate voltage of the upper-side output FET
to be generated. The voltage is stepped-up by capacitor CP connected between pins CP1 and CP2, causing
charge to accumulate in capacitor CG connected between pins VG and VCC. The capacitance of CP and
CG must always satisfy the following relationship.
CG 4 CP
Charging and discharging of capacitor CP take place based on a frequency of 100k Hz. When the
capacitance of capacitor CP is large, the current supply capability of power supply VG will increase.
However, if the capacitance is too large, the charging and discharging operations will be insufficient. The
larger the capacitance of capacitor CG, the more stable voltage VG will become. However, if the
capacitance is made too large, the period during which voltage VG is generated when the power is switched
ON will become long, so caution is necessary.
The capacitance settings of CP and CG should be the following.
CP = 0.01F
CG = 0.1F
12. Difference point of LV8829LFQA and LV8827LFQA
This difference that IC is the more following compared with LV8827LFQA exists.
When Duty=0% of PWM input is
detected
LV8829LFQA
LV8827LFQA
Synchronous rectification OFF
Short brake
(Free run)
At the low frequency number of
Synchronous rectification OFF
Like synchronous rectification ON
Synchronous rectification OFF
Like synchronous rectification ON
It is.
non
PWM input
(About 7.5kHz under)
At low ON Duty of the PWM input
(ex. frequency: 20kHz, ON Duty:
3% under)
Backflow
function
current
detecting
(At detection -> Synchronous rectification
OFF)
13. Metal part at the rear of the IC
The metal part at the rear of the IC (exposed die-pad) constitutes the sub ground of the IC, so connect it to
the control ground (SGND pin) and power ground pin (PGND) at points close to the IC.
14. Notes on Using the IC
This IC performs synchronous rectification in order to achieve high-efficiency drive.
The synchronous rectification operation reduces the output transistor loss so it has the effect of reducing
heat generation and improving efficiency.
However, the synchronous rectification operation may cause the supply voltage to rise depending on the
conditions under which the IC is used, such as:
When the output duty ratio has suddenly decreased
When the PWM input frequency is low, etc.
Protective measures must be taken to ensure that the maximum ratings are not exceeded even when the
supply voltage has risen. These measures include:
Appropriate selection of the capacitance of the capacitor inserted between the power supply and the
ground
Insertion of a zener diode between the power supply and the ground
13/19
LV8829LFQA Application Note
Typical Application Circuit
(Hall IC)
It is a bypass capacitor.
The setting range is
10μF to 100μF
(Electrolytic capacitor
etc.)
It is a bypass capacitor.
The setting range is
0.1μF to 1μF
(Layer ceramic capacitor
etc.)
It is “CP”; a capacitor for
the charge pump.
The setting range depends
on “CG”.
Please refer to P.12-13 for detail.
10µF
They are resistors
to pull up hall IC
each “+” output.
The setting range is
10kΩ to100kΩ
0.1µF
0.1µF
It is “CG”; a
capacitor for the
charge pump.
The setting range
depends on “CP”.
Please refer to
P.12-13 for detail.
It is a stabilization capacitor of the
internal regulator output voltage.
The setting range is
10μF to 100μF
(Electrolytic capacitor etc.)
0.01µF
12
11
10
9
8
7
0.1µF
10kΩ
13
IN1+
VG
6
HUP
U
M
W
V
14
OUT1
IN1-
5
15
OUT3
IN2+
4
6800pF
10kΩ
HVP
LV8829LFQA
16
OUT2
IN2-
3
17
RF
IN3+
2
18
PGND
IN3-
1
6800pF
10kΩ
HWP
0.255Ω
It is a resistor to pull
up FG output.
The setting range is
1kΩ to 10kΩ
22
23
24
It is a capacitor for
a constraint
protection circuit.
The setting range is
0.01μF to 0.48μF
Please refer to P.11
for detail.
10kΩ
21
10kΩ
20
VREG
0.022μF
19
10kΩ
It is a current
detection resistor.
The setting range is
0.15Ω to 1Ω
Please refer to P.10
for detail.
6800pF
They are stabilization
capacitors of the hall IC
each “+” output.
The setting range is
1000pF to 0.01μF
Each hall “-” input pin
should be inputted
middle voltage of
VREG. These resistors
make the voltage.
The setting range is
10kΩ to 100kΩ
Please refer to P.11-12
for detail.
Figure12. Typical application Circuit for a motor with Hall ICs
14/19
LV8829LFQA Application Note
(Hall Elements)
It is a bypass capacitor.
The setting range is
0.1μF to 1μF
(Layer ceramic capacitor
etc.)
It is “CP”; a capacitor for
the charge pump.
The setting range depends
on “CG”.
Please refer to P.12-13 for detail.
0.1µF
10µF
0.1µF
6800pF
SGND
CP2
CP1
VCC1
0.1µF
It is a stabilization capacitor of the
internal regulator output voltage.
The setting range is
10μF to 100μF
(Electrolytic capacitor etc.)
0.01µF
VCC2
It is “CG”; a
capacitor for the
charge pump.
The setting range
depends on “CP”.
Please refer to
P.12-13 for detail.
VREG
It is a bypass capacitor.
The setting range is
10μF to 100μF
(Electrolytic capacitor
etc.)
U
6800pF
W
6800pF
V
It is a resistor to pull
up FG output.
The setting range is
1kΩ to 10kΩ
It is a capacitor for
the constraint
protection circuit.
The setting range is
0.01μF to 0.48μF
Please refer to P.11
for detail.
HUP
HVN
HVP
HWN
HWP
HB
PWMIN
CSD
F/R
0.022μF
10kΩ
S/S
It is a current
detection resistor.
The setting range is
0.15Ω to 1Ω
Please refer to P.10
for detail.
FG
0.255Ω
HUN
They are stabilization
capacitors of the hall
elements output.
The setting range is
1000pF to 0.01μF
It is a resistor for when
three Hall elements are
connected in parallel.
The setting range depends
on Hall elements.
Please refer to P.12 for
detail.
Figure13. Typical application Circuit for a motor with Hall elements
15/19
LV8829LFQA Application Note
Evaluation Board (“M-DrAGON means Motor-Driver And GUI produced by ON semiconductor)
C4:
VG Stabilization
Capacitor
C2:
VCC Bypass
Capacitor
C3:
Capacitor for
Charge pump
C5:
VREG Stabilization
Capacitor
R1:
Output current
Sensing resistor
R7-14, C10-12:
Resistors and Capacitors
for Hall IC
R2:
Resistor to pull-up FG output
R4-6:
Interface resistors for
daughter board
C6:
Capacitor for the constraint
protection circuit
“VCC”
Power Supply
C1:
VCC Bypass
Capacitor
Figure14. “M-DrAGON” overview (Top view)
Daughter Board
IC2:
Level shifter
C13:
VDD Stabilization
Capacitor
C14:
VREG Stabilization
Capacitor
Figure15. “M-DrAGON” overview (Bottom view)
Controller
Tachometer
Graph
Figure16. Images of GUI
16/19
LV8829LFQA Application Note
Bill of Materials for LV8829LFQA Evaluation Board
Designator
Quantity
Description
Value
Tolerance
Footprint
Manufacturer
Manufacturer Part Number
Substitution
Allowed
Lead
Free
IC1
1
Motor Driver
-
-
VQFN24N
ON Semiconductor
LV8829LFQA
No
Yes
IC2
1
Level Shifter
-
-
TSSOP16
ON Semiconductor
MC14504B
No
Yes
R1
2
Thick film Resistor
0.51Ω,0.25W
±5%
2012(0805Inch)
Rohm
MCR10EZHJLR51
Yes
Yes
R2
1
Thick film Resistor
10kΩ,0.1W
±5%
1608(0603Inch)
Rohm
MCR03ERTJ103
Yes
Yes
R4-6
3
Thick film Resistor
200Ω,0.1W
±5%
1608(0603Inch)
Rohm
MCR03ERTJ201
Yes
Yes
R7-9
3
Jumper
0Ω,0.1W
±5%
1608(0603Inch)
Rohm
MCR03ERTJ000
Yes
Yes
R10-14
5
Thick film Resistor
10kΩ,0.1W
±5%
1608(0603Inch)
Rohm
MCR03ERTJ103
Yes
Yes
C1
1
Electrolytic Capacitor
10µF, 50V
±20%
F2.0-5
SUN Electronic Industries
50ME10HC
Yes
Yes
C2
1
Ceramic multilayer Capacitor
0.1µF, 100V
±10%
1608(0603Inch)
Murata
GRM188R72A104KA35*
Yes
Yes
C3
1
Ceramic multilayer Capacitor
0.01µF, 50V
±10%
1608(0603Inch)
Murata
GRM188B11H103KA01*
Yes
Yes
C4
1
Ceramic multilayer Capacitor
0.1µF, 100V
±10%
1608(0603Inch)
Murata
GRM188R72A104KA35*
Yes
Yes
C5
1
Ceramic multilayer Capacitor
0.1µF, 100V
±10%
1608(0603Inch)
Murata
GRM188R72A104KA35*
Yes
Yes
C6
1
Ceramic multilayer Capacitor
0.022µF, 50V
±10%
1608(0603Inch)
Murata
GRM188B11H223KA01*
Yes
Yes
C10-12
3
Ceramic multilayer Capacitor
6800pF, 50V
±10%
1608(0603Inch)
Murata
GRM188B11H682KA01*
Yes
Yes
C13,14
2
Ceramic multilayer Capacitor
0.1µF, 100V
±10%
1608(0603Inch)
Murata
GRM188R72A104KA35*
Yes
Yes
Daughter
Board
1
Interface board
-
-
-
ON Semiconductor
-
No
Yes
CN-A1,A2,B
3
Female Socket
-
-
-
MAC8
PM-61
Yes
Yes
CON_M1
1
Socket to Motor
-
-
-
JST
B3B-EH
No
Yes
CON_M2
1
Socket to Motor
-
-
-
JST
BM05B-SRSS-TB
No
Yes
P1
1
Test Point
-
-
-
MAC8
ST-1-3
Yes
Yes
USB cable
1
A-MiniB
-
-
-
-
-
Yes
Yes
Ref Motor
1
BLDC motor
18V-1A
-
-
Minebea
BLIM2430H-A01
Yes
Yes
17/19
LV8829LFQA Application Note
Evaluation Board circuit
MOTOR
CONNECTOR1
MOTOR
CONNECTOR2
15pin 16pin 14pin
(OUT3) (OUT2) (OUT1)
2pin 4pin 6pin 7pin 11pin
(IN3+) (IN2+) (IN1+) (SGND)(VCC1)
C2
P1
LV8829
VCC
C3
C1
C4
12
11
10
C5
9
8
7
R10
13
IN1+
VG
P12
6
C10
14
IN1-
OUT1
P11
5
R7
15
IN2+
OUT3
R11
P10
4
C11
LV8829LFQA
16
IN2-
OUT2
P9
3
R8
17
IN3+
RF
R12
P8
2
C12
R1
18
IN3-
PGND
P7
1
R9
R13
19
20
21
22
23
24
VREG
IC1
VCC
R14
C6
R2
Q1
R4
P2
Daughter Board
A2-15
(ST-Bar)
P3
R5
R6
R3
P4
P5
P6
MC14504 Daughter Board
A1-17
15pin
(FR1)
Daughter Board
A1-10
(PWM1)
Daughter Board
C13
B-3
(3.3V)
B-19
(FG)
16
15
LV8829
20pin
(FG)
14
13
12
11
10
9
IC2
MC14504BDT
VREG
1
2
3
4
5
6
7
8
C14
Figure17. Evaluation Board Circuit Schematic
18/19
LV8829LFQA Application Note
Operation Guide
Connect a 3-phase Blush less DC motor with MOTOR CONNECTOR1 and MOTOR CONNECTOR2
or P7-12.
(When we provide the Evaluation Board, it is mounted periferal parts for Hall ICs.
Because the BLDC motor that we provide is builtin Hall ICs.
When you drive the BLDC with Hall elements, please remove R7-14, C10-12 and mount R3, C7-9,
connect + terminal of the Hall elements to P6. Refer to P.11-12 for detail.
When you control LV8829LFQA by your DSP, please remove the Daughter Board and input signals to
P2-5.)
Please start up the system in following procedure.
1. Plug an USB cable into the Daughter Board.
2. Start up the GUI for LV8829LFQA.
3. Apply input voltage to the terminal P1 “VCC”.
Don’t apply voltage before plugging USB into the Daughter Board and starting the GUI.
4. Input drive signals by GUI.
When you unplug the daughter board, turn “VCC” off at first.
The points of attention to design applications
Do not exceed the absolute maximum ratings under no circumstance.
VCC, and each OUT, where large current flows should be laid out as fat and short as possible.
The metal part at the rear of the IC (exposed die-pad) constitutes the sub ground of the IC, so connect
it to the control ground (SGND pin) and power ground pin (PGND) at points close to the IC.
VCC bypass capacitor, especially Ceramic multilayer Capacitor should be mounted as near as
possible to VCC pin of LV8829LFQA.
VREG should be used in the IC as reference voltage. Capacitor should be connected between VREG
pin and GND to stabilize VREG. Therefore, the capacitor should be mounted as near as possible to
VREG pin.
The impedance of the island of GND needs to be as low as possible by making through-holes, for
example.
We recommend that the GND lines to connect a motor and the GND area of MCUs are laid out
independently and single-point-grounded at VM bypass capacitor
VREG can not be recommended to use for peripheral circuits because their output voltage are not so
high in precision.
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performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
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19/19