P3P76Z11D, P3P76Z11DH Low Voltage, Timing-Safe] Peak EMI reduction IC Functional Description P3P76Z11D/DH is a versatile low voltage peak EMI reduction IC based on Timing−Safe technology. P3P76Z11D/DH accepts one input from an external reference, and locks on to it delivering a 1x Timing−Safe output clock. P3P76Z11D/DH has a Frequency Selection (FS) control that facilitates selecting one of the two frequency ranges within the operating frequency range. Refer frequency Selection table. The device has an SSEXTR pin to select different deviations depending upon the value of an external resistor connected at this pin to GND. P3P76Z11D/DH has a DLY_CTRL for adjusting the Input−Output clock delay, depending upon the value of the capacitor connected at this pin to GND. PD# / OE provide the Power Down option. Outputs will be tri−stated when power down is active. P3P76Z11D is a Low drive part and P3P76Z11DH is a High drive part. Refer to DC/AC Electrical characteristic table. P3P76Z11D/DH operates over a supply voltage range of 1.8 V ± 0.2 V, and is available in an 8 Pin WDFN (2 mm x 2 mm) Package. http://onsemi.com MARKING DIAGRAMS 1 1 CCMG G WDFN8 CASE 511AQ CC = Specific Device Code M = Date Code G = Pb−Free Device PIN CONFIGURATION General Features • 1x , LVCMOS Timing−Safe Peak EMI Reduction • Input Clock Frequency: • • • • • • • • 15 MHz − 75 MHz Output Clock Frequency( Timing−Safe): 15 MHz − 75 MHz Analog Frequency Deviation Selection Analog Input−Output Delay Control Power Down option for Power Save Low and High drive parts Supply Voltage: 1.8 V ± 0.2 V 8 pin WDFN(2 mm x 2 mm) package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant CLKIN 1 PD#/OE 2 P3P76Z11D/DH 8 VDD 7 SSEXTR FS 3 6 DLY_CTRL GND 4 5 ModOUT ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. Application • P3P76Z11D/DH is targeted for use in consumer electronic applications like mobile phones, Camera modules, MFP and DPF. © Semiconductor Components Industries, LLC, 2011 March, 2011 − Rev. 0 1 Publication Order Number: P3P76Z11D/D P3P76Z11D, P3P76Z11DH DLY_CTRL VDD SSEXTR ModOUT (Timing−Safe) CLKIN PLL PD#/OE GND FS Figure 1. Block Diagram Table 1. PIN DESCRIPTION Pin# Pin Name Type Description 1 I CLKIN 2 I PD# / OE 3 I FS 4 P GND 5 O ModOUT 6 O DLY_CTRL 7 I SSEXTR 8 P VDD External reference Clock input. Power Down. Pull LOW to enable Power Down. Outputs will be tri−stated when power down is enabled. Pull HIGH to disable power down and enable output.Has NO default state. Frequency Select (see Frequency Selection table for details). Has NO default state. Ground Buffered modulated Timing−Safe clock output External Input−Output Delay control Analog Spread Selection through external resistor to GND. Supply Voltage Table 2. FREQUENCY SELECTION TABLE FS Frequency (MHz) 0 15 − 30 1 30 − 75 Table 3. OPERATING CONDITIONS Symbol VDD Description Supply Voltage Min Max Unit 1.6 2 V 0 +70 °C TA Operating Temperature CL Load Capacitance 15 pF CIN Input Capacitance 7 pF http://onsemi.com 2 P3P76Z11D, P3P76Z11DH Table 4. ABSOLUTE MAXIMUM RATING Min Max Unit Supply Voltage to Ground Potential Parameter −0.3 +2.7 V DC Input Voltage(CLKIN) −0.3 +2.7 V DC Input Voltage (Except CLKIN) −0.3 VDD + 0.3 V Storage Temperature −65 +150 °C 260 °C Junction Temperature 150 °C Static Discharge Voltage (As per JEDEC STD22− A114−B) 2000 V Max. Soldering Temperature (10 sec) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. DC ELECTRICAL CHARACTERISTICS FOR VDD = 1.8 V + 0.2 V Symbol Parameter VDD Supply Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current IIL Input LOW Current VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions Min Typ Max Unit 1.6 1.8 2 V 0.65 * VDD V 0.35 * VDD V VIN = VDD 5 mA VIN = 0 V 5 mA IOH = −8 mA (P3P76Z11D) IOH = −16 mA (P3P76Z11DH) 0.75 * VDD V IOL = 8 mA (P3P76Z11D) IOL = 16 mA (P3P76Z11DH) ICC Static Supply Current IDD Dynamic Supply Current Zo PD# pin pulled to GND Unloaded Output Output Impedance V 10 mA FS = 0, @ 15 MHz 3 FS = 0, @ 30 MHz 5 FS = 1, @ 30 MHz 4 FS = 1, @ 75 MHz 10 P3P76Z11D 23 P3P76Z11DH 17 http://onsemi.com 3 0.25 * VDD mA W P3P76Z11D, P3P76Z11DH Table 6. AC ELECTRICAL CHARACTERISTICS FOR VDD = 1.8 V + 0.2 V Parameter Input Frequency ModOUT Duty Cycle (Notes 1 and 2) Rise Time (Notes 1 and 2) Test Conditions Min Max Unit FS = 0 15 30 MHz FS = 1 30 75 FS = 0 15 30 FS = 1 30 75 Measured at VDD / 2 45 Measured between 20% to 80% Fall Time (Notes 1 and 2) Measured between 80% to 20% Cycle−to−Cycle Jitter (Note 2) Unloaded output with SSEXTR = OPEN Load line PLL Lock Time (Note 2) 1.7 P3P76Z11D 1.3 2.1 P3P76Z11DH 1 1.7 15 MHz ±150 30 MHz ±100 30 MHz ±150 75 MHz ±100 on DLY_CTRL −35 ps/pF on ModOUT 35 t1 VDD/2 OUTPUT Figure 2. Duty Cycle Timing 80% 20% OUTPUT t3 t4 Figure 3. Output Rise/Fall Time http://onsemi.com 4 ps ns SWITCHING WAVEFORMS 20% ns 1.1 1. All parameters are specified with 15 pF loaded output. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. 80% ns 2.1 1 Stable power supply, valid clock presented on CLKIN pin, PD# toggled from Low to High VDD/2 % 1.3 SSEXTR = OPEN, No load on DLY_CTRL and ModOUT t2 55 P3P76Z11D FS = 0 Change in Input−Output delay (with capacitive load ≤ 15 pF), SSEXTR = OPEN (49−51) P3P76Z11DH FS = 1 Input−Output propagation Delay (Note 2) Typ VDD/2 1 ms P3P76Z11D, P3P76Z11DH TSKEW Input ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ TSKEW/2 Timg−Safe Output ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ TSKEW/2 One Clock Cycle (T) TSKEW represents input−output skew when spread spectrum is ON For example, TSKEW / 2= 0.20 * T for an Input clock of 24 MHz, translates in to (1/24 MHz) * 0.20 = 8.33 ns Figure 4. Input−Output Skew INPUT INPUT ModOUT with SSOFF Timing−Safe ModOUT Figure 5. Typical Example of Timing−Safe Waveform http://onsemi.com 5 P3P76Z11D, P3P76Z11DH 3.0 3.0 2.5 2.5 DEVIATION (±%) DEVIATION (±%) DEVIATION CHARTS 2.0 1.5 1.0 1.5 1.0 0.5 0.5 0.0 2.0 0 100 200 300 400 500 600 RESISTENCE (kW) 700 0.0 800 0 3.0 3.0 2.5 2.5 2.0 1.5 1.0 700 800 1.5 1.0 0 100 200 300 400 500 600 700 0.0 800 0 Figure 9. Deviation vs. SSEXTR @ FS = 1, 30 MHz 3.0 2.5 2.5 DEVIATION (±%) 3.0 2.0 1.5 1.0 100 200 300 400 500 600 700 800 900 1000 RESISTENCE (kW) Figure 8. Deviation vs. SSEXTR @ FS = 0, 30 MHz DEVIATION (±%) 600 2.0 RESISTENCE (kW) 0.5 0.0 300 400 500 RESISTENCE (kW) 0.5 0.5 0.0 200 Figure 7. Deviation vs. SSEXTR @ FS = 0, 24 MHz DEVIATION (±%) DEVIATION (±%) Figure 6. Deviation vs. SSEXTR @ FS = 0, 15 MHz 100 2.0 1.5 1.0 0.5 0 0.0 100 200 300 400 500 600 700 800 900 1000 RESISTENCE (kW) 0 Figure 10. Deviation vs. SSEXTR @ FS = 1, 40 MHz 100 200 300 400 500 RESISTENCE (kW) 600 Figure 11. Deviation vs. SSEXTR @ FS = 1, 48 MHz http://onsemi.com 6 700 P3P76Z11D, P3P76Z11DH 3.0 2.5 2.5 DEVIATION (±%) 3.0 2.0 1.5 1.0 0.5 0.0 2.0 1.5 1.0 0.5 0 100 200 300 400 500 0.0 700 600 0 RESISTENCE (kW) 50 100 150 200 250 300 350 400 450 RESISTENCE (kW) Figure 12. Deviation vs. SSEXTR @ FS = 1, 54 MHz Figure 13. Deviation vs. SSEXTR @ FS = 1, 72 MHz 3.0 2.5 DEVIATION (±%) DEVIATION (±%) DEVIATION CHARTS 2.0 1.5 1.0 0.5 0.0 0 50 100 150 200 RESISTENCE (kW) 250 300 Figure 14. Deviation vs. SSEXTR @ FS = 1, 74.25 MHz NOTE: Device−to−Device variation of Deviation and I/O delay is ±15%. http://onsemi.com 7 500 P3P76Z11D, P3P76Z11DH Recommended Noise VDDIN Reduction Filter R 1 CLKIN VDD 0.1 mF C1 2.2 mF C2 8 VDD ModOUT 5 Frequency Selection Control ModOUT Clock Rx 3 FS Analog Deviation Control. SSEXTR can be pulled HIGH to turn OFF SS SSEXTR 7 P3P76Z11D/DH VDD Power Down Control Rs 2 PD# DLY_CTRL 6 GND Analog Input−Output Delay Control 4 NOTE: Refer Pin Description table for Functionality details. Figure 15. PCB Layout Recommendation For optimum device performance, following guidelines are recommended. • Dedicated VDD and GND planes. • The device must be isolated from system power supply noise. A 0.1 mF and a 2.2 mF decoupling capacitor should be • mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible. All the VDD pins should have decoupling capacitors. In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers. A typical layout is shown in the figure As short as possible R As short as possible CLKIN VDD PD# SSEXTR FS DLY_CTRL GND ModOUT Figure 16. http://onsemi.com 8 RS P3P76Z11D, P3P76Z11DH ORDERING INFORMATION Part Number P3P76Z11DHG−08CR Top Marking Temperature Package Type Shipping† FE 0°C to +70°C 8−pin (2 mm x 2 mm) WDFN (Pb−Free) Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free. http://onsemi.com 9 P3P76Z11D, P3P76Z11DH PACKAGE DIMENSIONS WDFN8 2x2, 0.5P CASE 511AQ−01 ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. L L L1 PIN ONE REFERENCE 2X ÍÍÍ ÍÍÍ DETAIL A E OPTIONAL CONSTRUCTIONS 0.10 C 2X 0.10 C ÉÉ ÉÉ TOP VIEW EXPOSED Cu A3 DETAIL B 0.05 C 0.05 C MOLD CMPD DETAIL B A 8X DIM A A1 A3 b D E e L L1 OPTIONAL CONSTRUCTION A1 C SIDE VIEW RECOMMENDED SOLDERING FOOTPRINT* SEATING PLANE 7X 0.78 DETAIL A 1 MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 2.00 BSC 0.50 BSC 0.50 0.60 --0.15 8X 4 L PACKAGE OUTLINE 2.30 0.88 8 5 e/2 e 8X b 0.10 C A 0.05 C 8X B 0.35 NOTE 3 1 0.50 PITCH DIMENSIONS: MILLIMETERS BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Timing−Safe is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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