P3PS550AH D

P3PS550AH
High Drive General Purpose
Peak EMI Reduction IC
Product Description
The P3PS550AH is a versatile 2.3 V to 3.6 V, Timing−Safe™, high
drive spread spectrum frequency modulator designed specifically for a
wide range of clock frequencies. The P3PS550AH reduces
electromagnetic interference (EMI) at the clock source, allowing
system wide reduction of EMI of all clock dependent signals. The
P3PS550AH allows significant system cost savings by reducing the
number of circuit board layers ferrite beads, shielding that are
traditionally required to pass EMI regulations.
Features
•
•
•
•
•
•
•
•
High Drive, LVCMOS Peak EMI reduction IC
Input Clock Frequency: 18 MHz − 36 MHz
Output Clock Frequency: 18 MHz − 36 MHz
Eight different selectable Spread options
Power Down option for power save
Supply Voltage: 2.3 V − 3.6 V
8−pin WDFN, 2 mm x 2 mm (TDFN) Package
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• The P3PS550AH is targeted towards consumer electronic
applications.
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MARKING
DIAGRAMS
1
1
WDFN8
CASE 511AQ
CCMG
G
CC = Specific Device Code
M = Date Code
G
= Pb−Free Device
PIN CONFIGURATION
CLKIN
1
SR2
2
PD#
VSS
8
VDD
7
SR0
3
6
SR1
4
5
ModOUT
P3PS550AH
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
July, 2010 − Rev. 1
1
Publication Order Number:
P3PS550AH/D
P3PS550AH
VDD
SR1
SR0
SR2
ModOUT
PLL
CLKIN
PD#
VSS
Figure 1. Block Diagram
P3PS550AH accepts an input from an external reference
clock and locks to a 1x modulated clock output. SR0, SR1
and SR2 pins enable selecting one of the eight different
frequency deviations (Refer Frequency Deviation Selection
table). P3PS550AH also features power down option for
power save. P3PS550AH operates over a supply voltage
range of 2.3 V to 3.6 V. P3PS550AH is available in an 8 Pin
WDFN, (2 mm x 2 mm) Package.
P3PS550AH modulates the output of a single PLL in
order to “spread” the bandwidth of a synthesized clock, and
more importantly, decreases the peak amplitudes of its
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
Table 1. PIN DESCRIPTION
Pin#
Pin Name
Type
Description
1
CLKIN
I
External reference clock input.
2
SR2
I
Digital logic input used to select Spreading Range. There is NO default state.
Refer Frequency Deviation Selection Table.
3
PD#
I
Power−down control pin. Powers down the entire chip. There is NO default state. Pull low to enable power−down mode. Connect to VDD to disable Power Down.
Output Clock will be LOW when power down is enabled
4
VSS
P
Ground connection.
5
ModOUT
O
Spread Spectrum Clock Output.
6
SR1
I
Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor. Refer
Modulation Selection Table.
7
SR0
I
Digital logic input used to select Spreading Range. There is NO default state.
Refer Frequency Deviation Selection Table.
8
VDD
P
Power supply for the entire chip
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2
P3PS550AH
Table 2. FREQUENCY DEVIATION SELECTION TABLE
Spreading Range ($ %)
SR2
SR1
SR0
(@ 24 MHz)
0
0
0
1
0
0
1
2.5
0
1
0
1.25
0
1
1
1.5
1
0
0
0.4
1
0
1
0.75
1
1
0
1.75
1
1
1
2
Table 3. OPERATING CONDITIONS
Symbol
Min
Max
Unit
Supply Voltage with respect to VSS
2.3
3.6
V
TA
Operating temperature
−20
+85
°C
CL
Load Capacitance
15
pF
CIN
Input Capacitance
7
pF
VDD
Parameter
Table 4. ABSOLUTE MAXIMUM RATING
Symbol
VDD, VIN
TSTG
Parameter
Rating
Unit
Voltage on any input pin with respect to VSS
−0.5 to +4.6
V
Storage temperature
−65 to +125
°C
Ts
Max. Soldering Temperature (10 sec)
260
°C
TJ
Junction Temperature
150
°C
2
kV
TDV
Static Discharge Voltage (As per JEDEC STD22−A114−B)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
Table 5. DC ELECTRICAL CHARACTERISTICS
Symbol
VDD
Parameter
Supply Voltage with respect to VSS
VIH
Input high voltage
VIL
Input low voltage
IIH
IIL
Min
Typ
Max
Unit
2.3
2.8
3.6
V
0.65 * VDD
V
0.3 * VDD
V
Input high current (SR1 control pin)
50
mA
Input low current (SR1 control pin)
50
mA
VOH
Output high voltage (IOH = − 16 mA)
VOL
Output low voltage (IOL = 16 mA)
ICC
Static supply current (PD# pulled to VSS)
IDD
Dynamic supply current (Unloaded Output @ 24 MHz)
6
Output impedance
20
ZOUT
0.75 * VDD
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3
V
0.2 * VDD
V
1
mA
9
mA
W
P3PS550AH
Table 6. AC ELECTRICAL CHARACTERISTICS
Symbol
CLKIN
ModOUT
tLH (Note 1)
Min
Typ
Max
Unit
Input Clock frequency
Parameter
18
24
36
MHz
Output Clock frequency
18
24
36
MHz
ns
Output rise time
(Measured between 20% to 80%)
Unloaded Output
0.4
0.8
CL = 15 pF
1.4
2.2
tHL (Note 1)
Output fall time
(Measured between 80% to 20%)
Unloaded Output
0.3
0.6
tJC (Note 1)
Jitter (cycle to cycle) Unloaded Output
tD (Note 1)
Output duty cycle
tON (Note 1)
fdvar
CL = 15 pF
1.1
1.9
$175
$250
ps
50
55
%
3
ms
$5
%
45
PLL lock Time
(Stable power supply, valid clock presented on CLKIN pin,
PD# toggled from Low to High)
Frequency Deviation Variation across PVT
ns
$2.5
1. Parameter is guaranteed by design and characterization. Not 100% tested in production
VDDIN
R
C1
0.1mF
C2
2.2mF
8
M Clock
VDD
1 CLKIN
P3PS550AH
Rs
ModOUT
VDD
SR2, SR1, SR0
Frequency Deviation
Selection Control
VDD
0W
0W
ModOUT Clock
5
2,6,7
SR2/SR1/SR0
0W
PD#
3
VSS
0W
Power Down
Control
4
NOTE:
Refer Pin Description table for Functionality details.
Figure 2. Typical Application Schematic
PCB Layout Recommendation
For optimum device performance, following guidelines are recommended.
• Dedicated VDD and GND planes.
• The device must be isolated from system power supply noise. A 0.1mF and a 2.2 mF decoupling capacitor should be
mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the
decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible.
All the VDD pins should have decoupling capacitors.
• In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers.
A typical layout is shown in the figure
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4
P3PS550AH
As short as
possible
R
As short as
possible
CLKIN
VDD
SR2
SR0
PD#
SR1
GND
VSS
Modout
Rs
Figure 3.
ORDERING INFORMATION
Part Number
P3PS550AHG−08CR
Top Marking
Temperature
Package Type
Shipping†
CC
−20°C to +85°C
8−pin (2 mm x 2 mm)
WDFN
Tape & Reel
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5
P3PS550AH
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AQ−01
ISSUE A
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
L
L
L1
PIN ONE
REFERENCE
2X
ÍÍÍ
ÍÍÍ
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
0.10 C
2X
0.10 C
ÉÉ
ÉÉ
TOP VIEW
EXPOSED Cu
A3
DETAIL B
0.05 C
0.05 C
MOLD CMPD
DETAIL B
A
8X
DIM
A
A1
A3
b
D
E
e
L
L1
OPTIONAL
CONSTRUCTION
A1
C
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
7X
0.78
DETAIL A
1
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
2.00 BSC
0.50 BSC
0.50
0.60
--0.15
8X
4
L
PACKAGE
OUTLINE
2.30
0.88
8
5
e/2
e
8X
b
0.10 C A
0.05 C
8X
B
0.35
NOTE 3
1
0.50
PITCH
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Timing−Safe is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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PUBLICATION ORDERING INFORMATION
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Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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For additional information, please contact your local
Sales Representative
P3PS550AH/D