P3P85R01A 3.3V, 75 MHz to 200 MHz LVCMOS TIMING SAFE] Peak EMI Reduction Device Functional Description P3P85R01A is a versatile, 3.3 V, LVCMOS, wide frequency range, TIMING SAFE Peak EMI reduction device. TIMING SAFE technology is the ability to modulate a clock source with Spread Spectrum technology and maintain synchronization with any associated data path. Refer to Figure 3. P3P85R01A has an SSEXTR pin that selects different frequency deviations depending upon the value of the resistor connected between this pin and GND. P3P85R01A has a DLY_CTRL pin used for adjusting the Input-Output clock delay, depending upon the value of capacitor connected at this pin to GND. The DLY_CTRL output phase is complementary to that of ModOUT clock. This signal enables better EMI management. P3P85R01A has a Bypass pin to bypass PLL. The device works from 100 Hz to 200 MHz with a fixed input to output delay when in Bypass mode. P3P85R01A has a PLLOUT_DLY for adjusting the PLL Output clock delay during power up time depending upon the value of capacitor connected at this pin to VDD. During power up time, ModOUT will be of the same frequency as CLKIN with a fixed input to output delay. http://onsemi.com MARKING DIAGRAMS 1 1 DEMG G WDFN8 CASE 511AQ DE = Specific Device Code M = Date Code G = Pb−Free Device (Note: Microdot may be in either location) PIN CONFIGURATION CLKIN 1 Bypass 2 8 VDD 7 PLLOUT_DLY P3P85R01A SSEXTR 3 6 DLY_CTRL GND 4 5 ModOUT General Features • • • • • • • • • • • 1x, LVCMOS Peak EMI Reduction Input Frequency Range: 75 MHz − 200 MHz Output Frequency Range: 75 MHz − 200 MHz Analog Deviation Selection Analog Input−Output Delay Control Analog PLL Output Delay Control Low Cycle−to−Cycle Jitter Supply Voltage: 3.3 V ± 0.3 V 8 pin, WDFN, 2 mm x 2 mm (TDFN) Package Operating Temperature Range: 0°C to +70°C These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Application • P3P85R01A is targeted for use in Displays, Giga LAN and SDRAM applications. © Semiconductor Components Industries, LLC, 2011 May, 2011 − Rev. 1 1 Publication Order Number: P3P85R01A/D P3P85R01A Bypass SSEXTR VDD CLKIN ModOUT PLL DLY_CTRL GND PLLOUT_DLY Figure 1. Block Diagram Table 1. PIN DESCRIPTION Pin# Pin Name Type Description 1 CLKIN Input External reference Clock Input 2 Bypass Input Bypass mode. When LOW device is in PLL Bypass mode. When HIGH PLL, mode is enabled 3 SSEXTR Input Analog Deviation Selection through an external resistor to GND. 4 GND Power Ground 5 ModOUT Output Buffered Modulated Clock output 6 DLY_CTRL Output Analog Input−Output Delay Control through an external capacitor to GND. Output used for EMI management 7 PLLOUT_DLY Input 8 VDD Power Analog PLL output delay control during power−up time, through an external capacitor to VDD Supply Voltage Table 2. OPERATING CONDITIONS Symbol VDD Description Supply Voltage TA Operating Temperature (Ambient Temperature) CIN Input Capacitance Min Max Unit 3.0 3.6 V 0 70 °C 7 pF Table 3. ABSOLUTE MAXIMUM RATING Symbol VDD, VIN TSTG Parameter Rating Unit Voltage on any input pin with respect to Ground −0.5 to +4.6 V Storage temperature −65 to +125 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C 2 kV TDV Static Discharge Voltage (As per JEDEC STD22−A114−B) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 P3P85R01A Table 4. ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Unit 3.0 3.3 3.6 V 0.8 V VDD Supply Voltage VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current VIN = 0 V 50 mA IIH Input HIGH Current VIN = VDD 50 mA 0.4 V 2.0 VOL Output LOW Voltage (Note 1) IOL = 8 mA VOH Output HIGH Voltage (Note 1) IOH = −8 mA ICC Static Supply Current IDD Dynamic Supply Current CL Load Capacitance Zo Output Impedance V 2.4 V CLKIN pin pulled LOW 100 mA Unloaded output 50 mA @ 200 MHz 10 pF 27 W 1. Parameter is guaranteed by design and characterization. Not tested in production Table 5. SWITCHING CHARACTERISTICS Max Unit Input Frequency Parameter 75 200 MHz Output Frequency 75 200 MHz 60 % Duty Cycle (Note 2) = (t2 / t1) * 100 Test Conditions Min Measured at VDD / 2 40 Typ 49 − 51 Output Rise Time (t3) (Notes 2 and 3) Measured between 20% to 80% 2 ns Output Fall Time (t4) (Notes 2 and 3) Measured between 80% to 20% 1.8 ns Delay, CLKIN Rising Edge to ModOUT Rising Edge (t5) (Notes 2 and 4) Load line @ 133 MHz, Variable Delay mode Fixed Delay mode Change in Input−Output delay, SSEXTR = OPEN −500 1.4 on DLY_CTRL −40 on ModOUT 40 ps 1.7 ns ps/pF PLL OUT Delay Time (Note 5) PLLOUT_DLY pin left OPEN 1 ms Cycle−to−cycle Jitter (Note 2) Unloaded Outputs @ 133 MHz ±100 ps PLL Lock Time (Note 2) Stable power supply, valid clock presented on CLKIN Device−to−Device variation of Deviation and I/O delay 2. 3. 4. 5. 1 ±20 Parameter is guaranteed by design and characterization. Not tested in production All parameters are specified with 10 pF − loaded outputs. 10 pF load on ModOUT, DLY_CTRL and SSEXTR pins left OPEN. Parameter is guaranteed by design. http://onsemi.com 3 ms % P3P85R01A Noise Reduction Filter VDD R3 C1 0.1 mF CLKIN 1 VDD VDD CLKIN VDD 8 C Analog Deviation Control SSEXTR can be Pulled HIGH to turn OFF Deviation 2 BYPASS 3 SSEXTR 4 GND Analog PLL Output delay Control PLLOUT_DLY 7 DLY_CTRL 6 ModOUT 5 R1 NOTES: Refer to Pin Description table for Functionality details. Figure 2. Application Schematic TSKEW Input ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ TSKEW/2 TIMING SAFEt Output ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ TSKEW/2 One clock cycle (T) TSKEW represents input-output skew when spread spectrum is ON For example, TSKEW/2= 0.20 x T for an Input clock of 75 MHz, translates into (1/75 MHz) x 0.20=2.66 nS Input Input ModOUT with SSOFF TIMINIG SAFEt ModOUT Figure 3. Typical Example of TIMING SAFE Waveform http://onsemi.com 4 P3P85R01A SWITCHING WAVEFORMS t1 t2 VDD/2 VDD/2 VDD/2 OUTPUT Figure 4. Duty Cycle Timing 80% 80% 20% 20% OUTPUT t3 t4 Figure 5. Output Rise/Fall Time VDD/2 INPUT VDD/2 OUTPUT t5 Figure 6. Input − Output Propagation Delay http://onsemi.com 5 P3P85R01A 2.0 2.0 1.5 1.5 DEVIATION (±%) DEVIATION (±%) CHARTS 1.0 0.5 0.5 0.0 1.0 0 50 100 RESISTOR (kW) 150 0.0 0 200 50 2.0 2.0 1.5 1.5 1.0 150 100 RESISTOR (kW) 150 1.0 50 100 RESISTOR (kW) 150 0.0 0 200 Figure 9. Deviation vs. SSEXTR @ 133 MHz 50 200 Figure 10. Deviation vs. SSEXTR @ 145 MHz 1.5 2.0 1.5 DEVIATION (±%) DEVIATION (±%) 100 RESISTOR (kW) 200 0.5 0.5 0.0 0 150 Figure 8. Deviation vs. SSEXTR @ 125 MHz DEVIATION (±%) DEVIATION (±%) Figure 7. Deviation vs. SSEXTR @ 106 MHz 100 RESISTOR (kW) 1.0 1.0 0.5 0.5 0.0 0 50 100 150 0.0 200 RESISTOR (kW) 0 50 Figure 12. Deviation vs. SSEXTR @ 166 MHz Figure 11. Deviation vs. SSEXTR @ 156 MHz http://onsemi.com 6 200 P3P85R01A DEVIATION (±%) PLLOUT−DLY TIME (s) 1 0 50 100 RESISTOR (kW) 150 200 0.1 0.01 0.001 0.0001 1.0E−12 Figure 13. Deviation vs. SSEXTR @ 175 MHz 1.0E−11 1.0E−10 1.0E−09 CAPACITOR (F) 1.0E−08 Figure 14. PLLOUT−DLY Time vs. Capacitor ORDERING INFORMATION Part Number P3P85R01AG−08CR Top Marking Temperature Package Type Shipping† DE 0°C to +70°C WDFN8 (2mm x 2mm) (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free. http://onsemi.com 7 P3P85R01A PACKAGE DIMENSIONS WDFN8 2x2, 0.5P CASE 511AQ−01 ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. L L L1 PIN ONE REFERENCE 2X ÍÍÍ ÍÍÍ DETAIL A E OPTIONAL CONSTRUCTIONS 0.10 C 2X 0.10 C ÉÉ ÉÉ TOP VIEW EXPOSED Cu A3 DETAIL B 0.05 C 0.05 C MOLD CMPD DETAIL B A 8X DIM A A1 A3 b D E e L L1 OPTIONAL CONSTRUCTION A1 C SIDE VIEW RECOMMENDED SOLDERING FOOTPRINT* SEATING PLANE 7X 0.78 DETAIL A 1 MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 2.00 BSC 0.50 BSC 0.50 0.60 --0.15 8X 4 L PACKAGE OUTLINE 2.30 0.88 8 5 e/2 e 8X b 0.10 C A 0.05 C 8X B 0.35 NOTE 3 1 0.50 PITCH DIMENSIONS: MILLIMETERS BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. TIMING SAFE is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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