High Efficiency Switch Mode Li-Ion Battery Charger

ADP3808A
High Efficiency Switch
Mode Li-Ion Battery
Charger
The ADP3808A is a complete Li-Ion battery charging controller for
3− or 4−cell battery packs. The device combines accurate final battery
charge voltage control with constant current control to simplify the
implementation of constant-current, constant-voltage (CCCV)
chargers.
The final battery charge voltage is programmable between 4.0 V to
4.5 V per cell, allowing the charging of various cell types. The charge
current is programmable over a wide range from trickle charging to
full charging. The system current sense amplifier includes an ac
adapter detection output to signal that the adapter is connected. The
bootstrapped synchronous driver controls two N−channel MOSFET
transistors for high efficiency charging at a low system cost.
The ADP3808A is specified over the extended commercial
temperature range of 0°C to 100°C and is available in a 24−lead
LFCSP package.
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ADP
3808A
JPZ
#YYWW
xx
= Device Code
#
= Pb−Free Package
YYWW = Date Code
19 BST
24 SYSP
20 DRVH
PIN ASSIGNMENT
21 SW
±0.4% @ 25°C
♦ ±0.6% @ 5°C to 55°C
♦ ±0.8% @ 0°C to 100°C
Programmable Charge Current, Including Trickle Charge
Bootstrapped Synchronous Drive for External N−Channel MOSFETs
Programmable Oscillator Frequency
This is a Pb−Free Device
♦
22 VCC
• Selectable 3−Cell or 4−Cell Operation
• Adjustable 4.0 V to 4.5 V Per Cell
• High End-of-Charge Voltage Accuracy
23 SYSM
Features
•
•
•
•
MARKING
DIAGRAM
LFCSP24
CASE 932AG
ISYS 1
18 DRVREG
LIMSET 2
17 DRVL
ADP3808A
LIMIT 3
16 PGND
TOP VIEW
EXTPWR 4
15 CSP
(Not to Scale)
RT 5
14 CSM
CELLSEL 12
BAT 11
AGND 10
• Portable Computers
• Portable Equipment
COMP 9
13 CSADJ
BATADJ 7
Applications
EN 8
REFIN 6
ORDERING INFORMATION
Device*
Package
Shipping†
ADP3808AJCPZ−RL LFCSP24 5000/Tape & Reel
*The “Z’ suffix indicates Pb−Free package.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
January, 2009 − Rev. 1
1
Publication Order Number:
ADP3808A/D
ADP3808A
VCC
22
EN
LOW−SIDE
DRIVE
REGULATOR
UVLO
AND BIAS
8
DRVREG
EN
REFERENCE
IN
AGND 10
RT
CELLSEL 12
BAT 11
REFIN
6
BATADJ
7
COMP
9
3−/4−
CELL
20
DRVH
21
SW
18
DRVLSD
OSCILLATOR
BST
DRVREG
CONTROL
LOGIC
5
19
DRVREG
17
DRVL
16
PGND
15
CSP
14
CSM
13
CSADJ
4
EXTPWR
VTH
BATTERY
VOLTAGE
ADJUST
gm
gm
SYSM 23
SYSP 24
CMP
CHARGE
CURRENT
SETPOINT
1V
CMP
SYS+
CMP
18.25V
1
2
3
ISYS LIMSET
LIMIT
Figure 1. Functional Block Diagram
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2
ADP3808A
ABSOLUTE MAXIMUM RATINGS
Description
Supply Voltage Input
Power Ground
Bootstrap Supply Voltage Input
BST to Switching Node
Switching Node
Symbol
Value
Unit
VCC
−0.3 to +25
V
PGND
−0.3 to +0.3
V
BST
−0.3 to +30
V
BST to SW
−0.3 to +6
V
SW
−4 to +25
V
High−Side Driver Output
DRVH
SW − 0.3 to BST + 0.3
V
Low−Side Driver Output
DRVL
PGND − 0.3 to DRVREG + 0.3
V
System Sense Inputs to Analog Ground
DC
< 50 msec
Battery Input, Current Sense Inputs to Analog
Ground
SYSP, SYSM to AGND
−25 to +30
−25 to +35
V
BAT, CSP, CSM to AGND
−0.3 to VCC + 0.3
V
Positive System Sense Input to Negative System
Sense Input
SYSP to SYSM
−5 to +5
V
Positive Current Sense Input to Negative Current
Sense Input
CSP to CSM
−5 to +5
V
DRVREG, CSADJ, EN,
CELLSEL, REFIN, BATADJ,
LIMSET, LIMIT, ISYS, EXTPWR
−0.3 to +6
V
2-Layer Board
4-Layer Board
qJA
125
83
°C/W
Operating Ambient Temperature Range
TA
0 to 100
°C
Junction Temperature Range
TJ
0 to 150
°C
Storage Temperature Range
TS
−65 to +150
°C
300
215
220
°C
All Other Inputs and Outputs
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
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3
ADP3808A
PIN DESCRIPTION
Pin No.
Symbol
1
ISYS
Description
2
LIMSET
3
LIMIT
4
EXTPWR
5
RT
6
REFIN
7
BATADJ
8
EN
9
COMP
Output of Error Amplifiers and Compensation Point.
10
AGND
Analog Ground. Reference point for the battery sense and all analog functions.
11
BAT
12
CELLSEL
13
CSADJ
14
CSM
Negative Current Sense Input. This pin connects to the battery side of the battery current sense
resistor.
15
CSP
Positive Current Sense Input. This pin connects to the inductor side of the battery current sense
resistor.
16
PGND
Power Ground. This pin should closely connect to the source of the lower MOSFET.
17
DRVL
Synchronous Rectifier Drive. Output drive for the lower MOSFET.
18
DRVREG
19
BST
20
DRVH
21
SW
Switch Node Input. This pin is connected to the buck-switching node, close to the source of the upper
MOSFET, and is the floating return for the upper MOSFET drive signal.
22
VCC
Input Supply. This pin does not power the SYS amplifier section.
23
SYSM
Negative System Current Sense Input. This pin connects to the battery side of the system current
sense resistor.
24
SYSP
Positive System Current Sense Input. This pin connects to the adapter side of the system current
sense resistor. This pin also provides power to the system amplifier section.
25
Paddle
This pin should be connected to AGND.
Output for System Current Sense Amplifier.
System Current Limit Set Point Input.
System Current Limit Output. This is an open-drain pin and requires a pull-up resistor to a maximum
of 6.0 V.
External Adapter Sense Open-Drain Output. This pin pulls low when the ac adapter voltage is
present. A pullup resistor is required to a maximum of 6 V.
Frequency Setting Resistor Input. An external resistor connected between this pin and AGND sets
the oscillator frequency of the device.
Reference Input for BATADJ and CSADJ.
Battery Voltage Adjust Input. This pin uses an analog voltage referenced to REFIN to program
voltage from 4.0 V to 4.5 V per cell.
Charger Enable Input. Pulling this pin to AGND disables the DRVH and DRVL outputs and puts the
circuitry powered by VCC into a low power state. The system amplifier and EXTPWR are still active.
Battery Sense Input.
Battery Cell Selection Input. Pulling this pin high selects 3-cell operation; pulling it low selects 4-cell
operation.
Charge Current Programming Input. This pin uses an analog voltage referenced to REFIN to program
the battery charge current. (VCSP − VCSM) = 96 mV x CSADJ/REFIN.
Driver Supply Output. A bypass capacitor should be connected from this pin to PGND to provide
filtering for the low−side supply.
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins
holds this bootstrapped voltage for the high−side MOSFET as it is switched.
Main Switch Drive. Output drive for the upper MOSFET.
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4
ADP3808A
ELECTRICAL CHARACTERISTICS
VCC = 20 V, EN = 5.0 V, REFIN = 3.0 V, TA = 0°C to 100°C; unless otherwise noted. (Note 1)
Parameter
Symbols
Symbol
Min
Typ
Max
Unit
Battery Voltage Sensing
Accuracy
Input Resistance
ΔVBAT
TA = 25°C, 13 V ≤ VCC ≤ 21 V,
BATADJ = 0 V or BATADJ = REFIN
−0.4
+0.4
%
5°C ≤ TA ≤ 55°C, 13 V ≤ VCC ≤ 21 V,
BATADJ = 0 V or BATADJ = REFIN
−0.6
+0.6
%
13 V ≤ VCC ≤ 21 V,
BATADJ = 0 V or BATADJ = REFIN
−0.8
+0.8
%
RBAT
Shutdown Leakage Current
IBAT(SD)
Overvoltage Threshold
VBAT(OV)
Overvoltage Response Time
tBAT(OV)
170
EN = 0 V
0.2
120
VBAT(OV) to COMP < 1 V
kW
1.0
mA
135
%
1
ms
Battery Voltage Adjust
BATADJ Input Range
VBATADJ
0
REFIN
V
REFIN Input Range
VREFIN
2.0
3.5
V
3-Cell Voltage Low
VBAT
BATADJ = 0 V, CELLSEL = 3.3 V
12.0
V
3-Cell Voltage High
VBAT
BATADJ = REFIN, CELLSEL = 3.3 V
13.5
V
4-Cell Voltage Low
VBAT
BATADJ = 0 V, CELLSEL = 0 V
16.0
V
4-Cell Voltage High
VBAT
BATADJ = REFIN, CELLSEL = 0 V
18.0
V
Battery Current Sense Amplifier
Accuracy (Note 2)
Input Common Mode Range
CSADJ = REFIN, 3 V ≤ VCS(CM) ≤ 21 V
−5
+5
%
CSADJ = REFIN / 5, 3 V ≤ VCS(CM) ≤
21 V
−9
+9
%
0°C ≤ TA ≤ 55°C, CSADJ = REFIN / 32,
3 V ≤ VCS(CM) ≤ 12 V
−33
+33
%
0°C ≤ TA ≤ 55°C, CSADJ = REFIN / 32,
12 V < VCS(CM) ≤ 21 V
−40
+40
%
0
VCC
V
VCM(CS)
Input Bias Current, Operating
IB(CSP)
Input Bias Current, Shutdown
IB(CSP,SD)
40
EN = 0 V
mA
0.1
1
2
mA
Input Bias Current, CSM
IB(CSM)
0.1
Gain
AV(CS)
31.25
IB(CSADJ)
1
2
mA
100
110
mV
CSADJ Bias Current
Overcurrent Threshold (Note 2)
VCS(OC)
Overcurrent Response Time
tDC
DRVL Shutdown Threshold
VCS(DRVLSD)
90
VOC > 130 mV to COMP < 1 V
mA
V/V
1
ms
28
mV
System Current Sense Amplifier
Input Common Mode Range
VCM(SYS)
SYSP and SYSM to AGND
Input Bias Current, SYSP
IB(SYSP)
VSYS(CM) = 19 V
Input Bias Current, SYSM
IB(SYSM)
VSYS(CM) = 19 V
Voltage Gain
VISYS/(VSYSP − VSYSM)
ISYS Output Current
LIMIT Threshold
LIMSET Input Range
LIMIT Output Voltage Low
1.
2.
3.
4.
10
300
SYSP to SYSM, LIMSET = 2.5 V
VLIMSET
VOL(LIMIT)
0.1
1
mA
50
51.5
V/V
48
53
58
mV
5
0
ILIMIT = −100 mA
V
mA
49.5
VISYS = 2.5 V
VTH(LIMIT)
22
400
30
mA
3.5
V
75
mV
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
Measured between CSP and CSM. (VCSP − VCSM) = 96 mV x CSADJ/REFIN.
For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.
The turn−on of DRVL is initiated after DRVH turns off by either SW crossing a ~1.0 V threshold or by examination of the timeout delay.
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5
ADP3808A
ELECTRICAL CHARACTERISTICS
VCC = 20 V, EN = 5.0 V, REFIN = 3.0 V, TA = 0°C to 100°C; unless otherwise noted. (Note 1)
Parameter
LIMIT Propagation Delay Time
Symbols
tpdl(LIMIT)
Symbol
Min
(SYSP) − (SYSM) rising > 55 mV to
LIMIT going low
Typ
Max
1
Unit
ms
EXTPWR Current Threshold
VTH(EXTPWR)
SYSP to SYSM
17.5
22.5
27.5
mV
EXTPWR Voltage Threshold
VTH(EXTPWR)
SYSP to AGND
18.0
18.25
18.5
V
EXTPWR Output Voltage Low
VTH(EXTPWR)
IEXTPWR = −100 mA
5
50
mV
EXTPWR Propagation Delay
Time
Vdpl(EXTPWR)
SYSP Rising > 18.5 V to EXTPWR
going low
1
ms
Oscillator
Maximum Frequency
fOSC
Frequency Variation
ΔfOSC
RT Output Voltage
1
RT = 150 kW
VRT
MHz
250
290
340
kHz
1.9
2
2.1
V
Zero Duty Cycle Threshold
Measured at COMP
1
V
Maximum Duty Cycle Threshold
Measured at COMP
2
V
Logic Inputs (EN, CELLSEL)
Input Voltage High
VIH
Input Voltage Low
VIL
Input Current
IIN
2.0
Inputs = 0 V or 5 V
V
–1
0.8
V
+1
mA
High−Side Driver
Output Resistance, Sourcing
Current
BST to SW = 5 V
3
8
W
Output Resistance, Sinking
Current
BST to SW = 5 V
3
8
W
Output Resistance, Unbiased
BST to SW = 0 V
10
trDRVH, tfDRVH
BST to SW = 5 V, CLOAD = 1 nF
20
40
ns
tpdhDRVH
BST to SW = 5 V, CLOAD = 1 nF
45
70
ns
Output Resistance, Sourcing
Current
3.8
8
W
Output Resistance, Sinking
Current
1.5
8
W
Transition Time
Propagation Delay Time
25
kW
Low−Side Driver
Output Resistance, Unbiased
Transition Time
Propagation Delay Time (Note 3)
VCC = PGND
10
trDRVL, tfDRVL
CLOAD = 1 nF
20
40
ns
tpdhDRVL
CLOAD = 1 nF
15
35
ns
Timeout Delay (Note 4)
SW = 5 V
SW = PGND
150
150
kW
300
300
ns
Supply VCC
Supply Voltage Range
VCC
10
22
V
Supply Current
Normal Mode
Shutdown Mode
Undervoltage Lockout Threshold
IVCC
EN = 5 V
9.8
14
mA
IVCC(SD)
EN = 0 V
1
10
mA
VUVLO
VCC rising
9.5
10
9
Undervoltage Lockout Hysteresis
600
DRV Regulator Output Voltage
VDRVREG
DRV Regulator Output Current
IDRVREG
1.
2.
3.
4.
CL = 100 nF
5.0
10
5.25
V
mV
5.5
V
mA
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
Measured between CSP and CSM. (VCSP − VCSM) = 96 mV x CSADJ/REFIN.
For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.
The turn−on of DRVL is initiated after DRVH turns off by either SW crossing a ~1.0 V threshold or by examination of the timeout delay.
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6
ADP3808A
TYPICAL CHARACTERISTICS
30
0.15
VCC = 16V
TA = 255C
VCC = 16V
0.1
25
VBAT ACCURACY (%)
NUMBER OF PARTS
0.05
20
15
10
0
–0.05
–0.1
–0.15
–0.2
5
–0.25
0
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
–0.3
0.5
0
10
20
30
VBAT ACCURACY (%)
Figure 2. VBAT Accuracy Distribution
80
100
90
Figure 3. VBAT Accuracy vs. Temperature
0.07
12
TA = 255C
0.06
NO LOADS
TA = 05C
11
ON SUPPLY CURRENT (mA)
0.05
VBAT ACCURACY (%)
40
50
60
70
TEMPERATURE (5C)
0.04
0.03
0.02
0.01
0
–0.01
TA = 255C
10
9
TA = 1005C
8
–0.02
7
–0.03
–0.04
13
14
15
16
17
VCC (V)
18
19
6
12
20
Figure 4. VBAT Accuracy vs. VCC
14
15
16
VCC (V)
17
18
20
19
Figure 5. On Supply Current vs. VCC
20
126
VCC = 16V
TA = 255C
fOSC = 300kHz
TA = 1005C
18
SUPPLY CURRENT (mA)
106
OFF SUPPLY CURRENT (nA)
13
86
TA = 255C
66
46
TA = 05C
16
14
12
10
26
6
12
13
14
15
16
VCC (V)
17
18
19
0
20
Figure 6. Off Supply Current vs. VCC
0
500
1000
1500
2000
2500
DRIVER LOAD CAPACITANCE (pF)
3000
3500
Figure 7. Supply Current vs. Driver Load
Capacitance
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7
ADP3808A
TYPICAL CHARACTERISTICS
6
ISYS RISING
ISYS FALLING
5
4
350
VLIMIT (V)
OSCILLATOR FREQUENCY (kHz)
400
300
3
2
250
1
200
90
110
130
150
170
190
0
210
0.5
0
RT (kW )
Figure 8. Oscillator Frequency vs. RT
2
2.5
3.0
4.5
VCC = 16V
VCC = 16V
4
DRIVER ON RESISTANCE ( W)
3.2
DRIVER ON RESISTANCE ( W)
1.5
VISYS (V)
Figure 9. VLIMIT vs. VISYS
3.3
3.1
SINK
3.0
2.9
SOURCE
2.8
2.7
1
SOURCE
3.5
3
2.5
2
SINK
1.5
0
20
40
60
TEMPERATURE (5C)
80
1
100
Figure 10. DRVH On Resistance vs. Temperature
20
0
40
60
TEMPERATURE (5C)
80
100
Figure 11. DRVL On Resistance vs. Temperature
VCC = 16V
TA = 255C
DRVH
5V/DIV
DRVL 5V/DIV
200ns/DIV
Figure 12. Driver Waveforms
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ADP3808A
TYPICAL CHARACTERISTICS
100
VCC = 19V
VBAT = 12.4V
TA = 255C
CONVERSION EFFICIENCY (%)
95
90
85
80
75
70
65
60
0
0.5
1.0
1.5
2.0
2.5
3.0
CHARGE CURRENT (A)
Figure 13. Conversion Efficiency vs. Charge Current
97
CONVERSION EFFICIENCY (%)
96
ICHARGE = 2A
95
ICHARGE = 3A
94
93
92
91
90
VCC = 19V
TA = 255C
89
88
3
4
5
6
7
8
9
10
11
12
13
VBAT (V)
Figure 14. Conversion Efficiency vs. Battery Voltage
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ADP3808A
Theory of Operation
drives two external power NMOS transistors for a simple,
lower cost power stage.
The ADP3808A also provides an uncommitted current
sense amplifier. This amplifier provides an analog output
pin for monitoring the current through an external sense
resistor. The amplifier can be used anywhere in the system
that high-side current sensing is needed. The sense amplifier
output is compared to a programmable voltage limit. If the
limit is exceeded, the LIMIT pin is asserted. The system
sense amplifier is also used to detect the presence of an ac
adaptor. If the adaptor is detected, the ADP3808A asserts a
logic pin to signal the detection.
The ADP3808A combines a bootstrapped synchronous
switching driver with programmable current control and
accurate final battery voltage control in a constant-current,
constant-voltage (CCCV) Li-Ion battery charger. High
accuracy voltage control is needed to safely charge Li-Ion
batteries, which are typically specified at 4.2 V ± 1% per
cell. For a typical notebook computer battery pack, three or
four cells are in series, giving a total voltage of 12.6 V or
16.8 V. The ADP3808A allows the final battery voltage to
be programmed. The programmable range is 4.0 V to 4.5 V
per cell. The total number of cells to be charged can be set
to either 3 or 4 via a control pin.
Another requirement for safely charging Li-Ion batteries
is accurate control of the charge current. The actual charge
current depends on the number of cells in parallel within the
battery pack. Typically, this is in the range of 2.0 A to 3.0A.
The ADP3808A provides flexibility in programming the
charge current over a wide range. An external resistor is used
to sense the charge current. The charge current can be set by
programming the sense resistor voltage drop. The voltage
drop can be set to a maximum of 96 mV. This
programmability allows the current to be changed during
charging. For example, the charge current can be reduced for
trickle charging.
The synchronous driver provides high efficiency when
charging at high currents. Efficiency is important mainly to
reduce the amount of heat generated in the charger, but also
to stay within the power limits of the ac adapter. With the
addition of a bootstrapped high-side driver, the ADP3808A
Setting the Charge Current
The charge current is measured across an external sense
resistor, RCS, between the CSP and CSM pins. The input
common-mode range is from ground to VCC, allowing
current control in short-circuit and low dropout conditions.
The voltage between CSP and CSM is programmed by a
ratio of the voltages at CSADJ and REFIN according to
Equation 1.
V CSP * V CSM + 96 mV CSADJ
REFIN
(eq. 1)
For example, using a 20 mW sense resistor gives a range
from 150 mA with CSADJ = REFIN/32 to 4.8 A maximum
when CSADJ = REFIN.
The power dissipation in RCS should be kept below
500 mW. Components R4 and C13 in Figure 15 provide high
frequency filtering for the current sense signal.
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ADP3808A
RSS
10mR
C15 +
22uF –
22uH
+
C16
–
22uF
C13
22nF
C9
BST
100nF
DRV
SW
DRVL
PGND
CSP
EN
SYSP
CSM
BOOTSTRAPPED
SYNCHRONOUS
DRIVER
BATTERY
12.6V/16.8V
C1
2.2uF
3.3V
ISYS
SYSM
LIMIT
3.3V
+ –
AMP1
IN DRVLSD
+
VCC
R2
510R
R4
510R
–
C14
2.2uF
1/2 Q1
FD56990A
AMP2
–
R13
10R
SYSTEM
DC/DC
RCS
20mR
L1
DRVLSD
+
VIN
1/2 Q1
FD56990A
R9
LIMSET
–
VTH
SYSP
–
18.25V
+
–
+
LOGIC
CONTROL
EXTPWR
CSADJ
CHARGE
CURRENT
SETPOINT
OSCILLATOR
RT
3.3V
3−/4−CELL
SELECTION
–
+
150k
BAT
gm2
ADP3808A
AGND
1V
gm1
+
–
EN
R10
–
+
+
DRVREG
5.25V
C10
0.1uF
VREF + VREG
UVLO
BIAS
BATTERY
VOLTAGE
ADJUST
R11
REFIN
BATADJ
COMP
C8
0.22uF
R12
CELLSEL
R8
56R
C11
Figure 15. Typical Application Circuit
Final Battery Voltage Control
BATADJ pin and is ratioed to the REFIN pin. The battery
voltage VBAT is set according to Equation 2 and Equation 3.
For CELLSEL > 2 V:
As the battery approaches its final voltage, the
ADP3808A switches from CC mode to CV mode. The
change is achieved by the common output node of gm1 and
gm2. Only one of the two outputs controls the voltage at the
COMP pin. Both amplifiers can only pulldown on COMP,
such that when either amplifier has a positive differential
input voltage, its output is not active. For example, when the
battery voltage, VBAT, is low, gm2 does not control VCOMP.
When the battery voltage reaches the desired final voltage,
gm2 takes control of the loop, and the charge current is
reduced.
Amplifier gm2 compares the battery voltage to a
programmable level set by pins BATADJ and REFIN. The
target battery voltage is dependent on the state of the
CELLSEL pin as CELLSEL sets the number of cells to be
charged. Pulling CELLSEL high sets the ADP3808A to
charge three cells. When CELLSEL is tied to ground, four
cells are selected. CELLSEL has a 2 mA pullup current as a
fail−safe to select three cells when it is left open.
The final battery voltage is programmable from 4.0 V to
4.5 V per cell. The programming voltage is applied to the
V BAT + 12 V ) 1.5 V BATADJ
REFIN
(eq. 2)
For CELLSEL < 0.8 V:
V BAT + 16 V ) 2.0 V BATADJ
REFIN
(eq. 3)
Oscillator and PWM
The oscillator generates a triangle waveform between
1.0 V and 2.0 V, which is compared to the voltage at the
COMP pin, setting the duty cycle of the driver stage. When
VCOMP is below 1.0 V, the duty cycle is zero. Above 2.0 V,
the duty cycle reaches its maximum. The oscillator
frequency is set by the external resistor at the RT pin, ROSC,
and is given by Equation 4.
9
f OSC + 41 10
R OSC
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(eq. 4)
ADP3808A
DRVREG
ADP3808A
BOOTSTRAPPED
SYNCHRONOUS DRIVER
BST
CMP3
CBST
MIN
OFF
TIME
IN
DRVH
Q1
EN
SW
–
CMP2
+
DELAY
1V
1V
DRVL
–
CMP1
+
Q2
PGND
DELAY
DRVLSD
Figure 16. Bootstrapped Synchronous Driver
5.25 V Bootstrap Regulator
Overlap protection is included in the driver to ensure that
both external MOSFETs are not on at the same time. When
DRVH turns off the upper MOSFET, the SW node goes low
due to the inductor current. The ADP3808A monitors the
SW voltage, and DRVL goes high to turn on the lower
MOSFET when SW goes below 1.0 V. When DRVL turns
off, an internal timer adds a delay of 50 ns before turning
DRVH on. When the charge current is low, the DRVLSD
comparator signals the driver to turn off the low-side
MOSFET and DRVL is held low. The DRVLSD threshold
is set to 0.8 V corresponding to a 32 mV differential between
the CS pins.
The driver stage monitors the voltage across the BST
capacitor with CMP3. When this voltage is less than 4.0 V,
CMP3 forces a minimum off time of 200 ns. This ensures
that the BST capacitor is charged even during DRVLSD.
However, because a minimum off time is only forced when
needed, the maximum duty cycle is greater than 99%.
The driver stage is powered by the internal 5.25 V
bootstrap regulator, which is available at the DRVREG pin.
Because the switching currents are supplied by this
regulator, decoupling must be added. A 0.1 mF capacitor
should be placed close to the ADP3808A, with the ground
side connected close to the power ground pin, PGND. This
supply is not recommended for use externally due to high
switching noise.
Bootstrapped Synchronous Driver
The PWM comparator controls the state of the
synchronous driver shown in Figure 16. A high output from
the PWM comparator forces DRVH on and DRVL off. The
drivers have an on resistance of less than 4.0 W for fast rise
and fall times when driving external MOSFETs.
Furthermore, the bootstrapped drive allows an external
NMOS transistor for the main switch instead of a PMOS. A
boost capacitor of 0.1 mF must be added externally between
BST and SW.
The DRVL pin switches between DRVREG and PGND.
The 5.25 V output of DRVREG drives the external NMOS
with high VGS to lower the on resistance. PGND should be
connected close to the source pin of the external
synchronous NMOS. When DRVL is high, this turns on the
lower NMOS and pulls the SW node to ground. At this point,
the boost capacitor is charged up through the internal boost
diode. When the PWM switches high, DRVL is turned off
and DRVH turns on. DRVH switches between BST and SW.
When DRVH is on, the SW pin is pulled up to the input
supply (typically 16 V), and BST rises above this voltage by
approximately 4.75 V.
System Current Sense
An uncommitted differential amplifier is provided for
additional high-side current sensing. This amplifier, AMP2,
has a fixed gain of 50 V/V from the SYSP and SYSM pins
to the analog output at ISYS. The common-mode range of
the input pins is from 10 V to 22 V. This amplifier is the only
part of the ADP3808A that remains active during shutdown.
The power to this block is derived from the bias current on
the SYSP and SYSM pins.
LIMIT
The LIMIT pin is an open-drain output that signals when
the voltage at ISYS exceeds the voltage at LIMSET. The
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ADP3808A
comparator limits the maximum voltage. Neither of these
comparators affects the loop under normal charging
conditions.
internal comparator produces the function shown in
Figure 9. This is a graph of VLIMIT vs. VISYS where
LIMSET is set to 1.5 V. The LIMIT pin should be pulled up
to a maximum of 6.0 V through a resistor. When ISYS is
below LIMSET, the LIMIT pin has high output impedance.
The open-drain output is capable of sinking 100 mA when
the threshold is exceeded. This comparator is turned off
during shutdown to conserve power.
Application Information
Design Procedure
Refer to Figure 15, the typical application circuit, for the
following description. The design follows that of a buck
converter. With Li-Ion cells it is important to have a regulator
with accurate output voltage control.
AC Adaptor Detection
The EXTPWR pin on the ADP3808A is an open−drain
active low output used to signal that an ac adaptor is
connected. If the ISYS voltage level is greater than 1.0 V or
the SYSP sense pin voltage is greater then 18.25 V, the
EXTPWR pin is driven low. A pullup resistor must be
connected when this function is required. The maximum
pullup voltage is 6.0 V.
Battery Voltage Settings
Inductor Selection
Usually the inductor is chosen based on the assumption
that the inductor ripple current is ±15% of the maximum
output dc current at maximum input voltage. As long as the
inductor used has a value close to this, the system should
work fine. The final choice affects the trade−offs between
cost, size, and efficiency. For example, the lower the
inductance, the size is smaller but ripple current is higher.
This situation, if taken too far, leads to higher ac losses in the
core and the windings. Conversely, a higher inductance
results in lower ripple current and smaller output filter
capacitors, but the transient response will be slower. With
these considerations, the required inductance can be
calculated using Equation 5.
EN
A high impedance CMOS logic input is provided to turn
off the ADP3808A. When the voltage on EN is less than
0.8 V, the ADP3808A is placed in low power shutdown.
With the exception of the system current sense amplifier,
AMP2, all other circuitry is turned off. The reference and
regulators are pulled to ground during shutdown and all
switching is stopped. During this state, the supply current is
less than 5.0 mA. In addition, the BAT, CSP, CSM, and SW
pins go to high impedance to minimize current drain from
the battery.
L1 +
V IN,
MAX * V BAT
D MIN
DI
TS
(eq. 5)
where the maximum input voltage VIN, MAX is used with the
minimum duty ratio DMIN. The duty ratio is defined as the
ratio of the output voltage to the input voltage, VBAT/VIN.
The ripple current is calculated using Equation 6.
UVLO
Undervoltage lock−out, UVLO, is included in the
ADP3808A to ensure proper startup. As VCC rises above
1.0 V, the regulator tracks VCC until it reaches its final
voltage. However, the rest of the circuitry is held off by the
UVLO comparator. The UVLO comparator monitors the
regulator to ensure that it is above 5.0 V before turning on
the main charger circuitry. This occurs when VCC reaches
9.5 V. Monitoring the regulator outputs makes sure that the
charger circuitry and driver stage have sufficient voltage to
operate normally. The UVLO comparator includes 600 mV
of hysteresis to prevent oscillations near the threshold.
DI + 0.3
I BAT,
(eq. 6)
MAX
The maximum peak-to-peak ripple is 30%, that is 0.3, and
maximum battery current, IBAT, MAX, is used.
For example, with VIN, MAX = 19 V, VBAT = 12.6 V, IBAT,
MAX = 3.0 A, and TS = 4 ms, the value of L1 is calculated as
18.9 mH. Choosing the closest standard value gives L1 = 22 mH.
Output Capacitor Selection
An output capacitor is needed in the charger circuit to
absorb the switching frequency ripple current and smooth
the output voltage. The rms value of the output ripple current
is given by:
Loop Feed Forward
As the startup sequence discussion shows, the response
time at COMP is slowed by the large compensation
capacitor. To speed up the response, two comparators can
quickly feed forward around the normal control loop and
pull the COMP node down to limit any overshoot in either
short-circuit or overvoltage conditions. The overvoltage
comparator has a trip point set to 35% higher than the final
battery voltage. The overcurrent comparator threshold is set
to 100 mV across the CS pins. When these comparators are
tripped, a normal soft−start sequence is initiated. The
overvoltage comparator is valuable when the battery is
removed during charging. In this case, the current in the
inductor causes the output voltage to spike up, and the
I rms +
V IN,
MAX
f L1 Ǹ12
D (1 * D )
(eq. 7)
The maximum value occurs when the duty cycle is 0.5. Thus,
I rms_MAX + 0.072
V IN,
MAX
f L1
(eq. 8)
For an input voltage of 19 V and a 22 uH inductance, the
maximum rms current is 0.26 A. A typical 10 mF or 22 mF
ceramic capacitor is a good choice to absorb this current.
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13
ADP3808A
Input Capacitor Ripple
MOSFET Selection
As is the case with a normal buck converter, the pulse
current at the input has a high rms component. Therefore,
because the input capacitor has to absorb this current ripple,
it must have an appropriate rms current rating. The maximum
input rms current is given by
One of the features of the ADP3808A is that it allows use of
a high-side NMOS switch instead of a more costly PMOS
device. The converter also uses synchronous rectification for
optimal efficiency. To use a high-side NMOS, an internal
bootstrap regulator automatically generates a 5.25 V supply
across C10.
Maximum output current determines the RDS(ON)
requirement for the two power MOSFETs. When the
ADP3808A is operating in continuous mode, the simplifying
assumption can be made that one of the two MOSFETs is
always conducting the load current. The power dissipation for
each MOSFET is given by:
Upper MOSFET:
I rms +
P BAT
h DV IN
ǸD(1 * D)
D
(eq. 9)
where h is the estimated converter efficiency (approximately
90%, 0.9) and PBAT is the maximum battery power consumed.
This is a worst−case calculation and, depending on total
charge time, the calculated number could be relaxed.
Consult the capacitor manufacturer for further technical
information.
P DISS + R DS(ON)
Decoupling the VCC Pin
T SW
It is a good idea to use an RC filter (R13 and C14) from the
input voltage to the IC both to filter out switching noise and
to supply bypass to the chip. During layout, this capacitor
should be placed as close to the IC as possible. Values
between 0.1 mF and 2.2 mF are recommended.
2
ǒIBAT
ǸDǓ ) V
IN
f
I BAT
ǸD
(eq. 10)
Lower MOSFET:
P DISS + R DS(ON)
ǒIBAT
Current Sense Filtering
Ǹ1 * DǓ
2
2
ǒIBAT
ǸDǓ ) V
IN
T SW
f
(eq. 11)
where f is the switching frequency and tSW is the switch
transition time, usually 10 ns.
The first term accounts for conduction losses while the
second term estimates switching losses. Using these
equations and the manufacturer’s data sheets, the proper
device can be selected.
During normal circuit operation, the current sense signals
can have high frequency transients that need filtering to
ensure proper operation. In the case of the CSP and CSM
inputs, Resistor R4 is set to 510 W and the filter capacitor C13
is 22 nF. For the system current sense filter on SYSP, SYSM,
R2 is set to 510 W, C1 is 2.2 mF.
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ADP3808A
PACKAGE DIMENSIONS
LFCSP24 4x4, 0.5P
CASE 932AG−01
ISSUE O
A
D
D1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
PIN ONE
REFERENCE
E1
E
0.15 C
DIM
A
A1
A3
b
D
D1
D2
E
E1
E2
e
H
K
L
M
0.15 C TOP VIEW
H
0.10 C
(A3)
A
NOTE 4
0.08 C
4X
A1
SIDE VIEW
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
4.00 BSC
3.75 BSC
1.95
2.25
4.00 BSC
3.75 BSC
1.95
2.25
0.50 BSC
−−−
12 °
0.20
−−−
0.30
0.50
−−−
0.60
M
K
D2
4X
M
SOLDERING FOOTPRINT*
7
4.30
13
PIN 1
INDICATOR
2.30
E2
24X
1
L
24X
0.63
1
24
e
BOTTOM VIEW
24X
b
0.10 C A B
0.05 C
4.30
2.30
NOTE 3
PACKAGE
OUTLINE
24X
0.50
PITCH
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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ADP3808A/D