IRIS or Auto Focus (AF) Controller & Driver with 40 KB Flash Memory

LC898123F40XC
IRIS or Auto Focus (AF) Controller &
Driver with 40 KB Flash Memory
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1. Overview
LC898123F40XC is a system LSI integrating an onchip 32bit DSP, a Flash
Memory and peripherals including analog circuits for IRIS or AF (Auto
Focus) control and H-bridge and linear drivers.
2. Features
WLCSP35, 3.22x2.3
 Onchip 32 bit DSP
 Built-in software digital servo filter
 Built-in software Gyro filter
 Motor Driver
 OP-AF(unidirection)
Constant current linear driver (1 ch, Ifull = 150 mA)
 OP-AF(bidirection)
Constant current linear driver (1 ch, Ifull = 150 mA)
 CL-AF
Constant current linear driver (1 ch, Ifull = 150 mA)
H-bridge PWM driver (1 ch, Iomax 150 mA)
 Flash Memory
 40 kByte Flash memory to store data and DSP
program
 Peripherals
 Hall AD converter
 14 bit
 Input 4 ch
 DA converter for Hall Offset setting
 8 bit / 1 ch
 DA converter for Hall Bias
 8 bit
 Output 1 ch
 Built-in Serial I/F circuit
(2-wire Bus with clock stretch function) (1MHz)
 Built-in Hall Amp
(Gain of Opamp : 5, 10, 13, 20, 40, 60)
 Built-in OSC(Oscillator)
 typ 41 MHz
 Built-in LDO (Low Drop-Out regulator)
 Digital Gyro I/F for various types of gyro (SPI Bus)
 Power supply voltage
 AD/DA/VGA/LDO/OSC :
AVDD30 = 2.6V to 3.3V
 Digital I/O (except Gyro I/F) :
AVDD30 = 2.6V to 3.3V
 Driver :
VM = Constant current : 1.75 to 3.3V
H Bridge PWM : 2.6 to 3.3V
 Core Logic / Gyro I/F IO :
generated by onchip LDO
DVDD15 = typ 1.55V output
 Package
 WLP35
(3.22mm  2.30mm , thickness : 0.45mm w/ BC)
 Pb-Free
 Halogen Free
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
May 2016 - Rev. 0
1
Publication Order Number :
LC898123F40XC/D
LC898123F40XC
3. Block Diagram
LPDSP32
8bit DAC
HLXBO
1.5Kbyte
(384word*32bit)
Work RAM: DMA0
1.5Kbyte
(384word*32bit)
Work RAM: DMA1
3Kbyte
(768word*32bit)
Work RAM: DMB
HLYBO
DMA0
Program
Data
8bit DAC
4Kbyte
(832word*40bit)
Program ROM
DMA1
DMB
DMIO
40Kbyte
FLASH
FLASH I/F
HLAFBO
OPINPX
OPINMX
SCL
SCL
SDA
SDA
I2C
(master)
SCL
WPB
SDA
EIRQ1
I2C
(slave)
SCL
SDA
SCL2
(TXD)
SDA2
(RXD)
UART
RXD
HOST
CPU
(master)
TXD
DAC Ctrl
OPINPY
I2C
(slave)
Timer
OPINMY
DGSSB
Port
SPI
(master/slave)
(D-Gyro I/F)
DGSCLK
DGDATA
DGDIN
Hall
AF
OPINPA
F
OPINMA
F
OUT1
OUT2
OUT3
VGAAF
PWM/Current
Linear Ctrl
ADC Ctrl
H-Bridge
Driver
MON1
WPB
AIN0
VM
PGND
EIRQ1
System Ctrl
OUT5
OUT6
HSYNC
14bit ADC
OUT4
EXCLK
AIN1
MONA
Monitor
AIN2
MON2
MONB
MONC
MOND
AIN3
WPB
PWMREFCLK
EIRQ1
EXCLK
PLL
EXCLK
30M to
42MHz
EIRQ1
POR
EXCLK
AVDD30
AVSS
OSC/PLL
OSC Typ.
41MHz(2.8V)
PLL 20M to 42MHz
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2
Clock Divider
1.5V±10%
LDO
LDOPO(DVDD15
)
DVSS
LC898123F40XC
4. Application Diagram
Camera Module
Lens
Hall
Sensor
IRIS or AF
Actuator
VCM
LC898123F40XC
EEPROM
Digital
Gyro
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3
Image
Sensor
AP/ISP
LC898123F40XC
5. Package Dimensions
unit : mm
WLCSP35, 3.22x2.3
CASE 567LJ
ISSUE O
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
A B
PIN A1
REFERENCE
DIM
A
A1
b
D
E
e
D
MILLIMETERS
MIN
MAX
0.45
0.03
0.13
0.15
0.25
3.22 BSC
2.30 BSC
0.40 BSC
0.10 C
2X
0.10 C
2X
TOP VIEW
A
0.10 C
A1
0.08 C
C
SIDE VIEW
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
A1
e
35X
b
0.05 C A B
0.03 C
PACKAGE
OUTLINE
G
F
e
E
0.40
PITCH
D
35X
C
0.20
B
0.40
PITCH
A
DIMENSIONS: MILLIMETERS
1
2
3
4
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
5
BOTTOM VIEW
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4
LC898123F40XC
6. Pin Assign
OUT4
OUT3
OUT2
OUT1
VM
MON1
SDA2
(RXD)
WPB
PGND
OUT6
MON2
SCL2
(TXD)
DVSS
EXCLK
OUT5
DVDD15
EIRQ1
AVSS
SDA
SCL
AVDD30
HLAFBO
AVSS
HLYBO
HLXBO
DGDATA
DGSSB
OPINMAF
OPINMY
OPINMX
DGSCLK
DGDIN
OPINPAF
OPINPY
OPINPX
1
2
3
4
5
G
F
E
D
C
B
A
BOTTOM VIEW
Analog VDD
Driver output
Driver VDD
Analog GND
Digital GND
Logic Core VDD (Output)
Driver GND
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5
LC898123F40XC
7. Pin Desctiption
Pin
Num
Pin
I/O
Atr
I/O
Pwr (V)
Primary Function
(just after Reset)
Digital Gyro I/F Clock Input
Digital Gyro I/F Clock Output
Sub Functions
Digital Gyro Clock Output
Internal Signal Monitor
I2C Data I/O for DAC Monitor
Internal Signal Monitor
Init
A1
DGSCLK
B
1.55
A2
DGDIN
B
1.55
I
2.8
AF Hall Opamp Input Plus


A4
A5
OPINPA
F
OPINPY
OPINPX
I
I
2.8
2.8
connect to OPINMY(B4)
connect to OPINMX (B5)


B1
DGDATA
B
1.55
GPIO Input
Z
B2
DGSSB
B
1.55
Digital Gyro I/F Chip Select Input
DigitalGyro I/F Chip Select Output


Digital Gyro I/F Data Output (4 Wired)
Digital Gyro I/F Data I/O (3 Wired)
Internal Signal Monitor
Digital Gyro I/F Chip Select Output
Internal Signal Monitor
A3
Digital Gyro Data Input (4 Wired)
Z
Z
Z
I
2.8
AF Hall OpAmp Input Minus


B4
B5
C1
C2
C3
C4
C5
D1
OPINMA
F
OPINMY
OPINMX
AVDD30
HLAFBO
AVSS
HLYBO
HLXBO
DVDD15
I
I
P
O
P
O
O
P
2.8
2.8

2.8
connect to OPINPY(A4)
connect to OPINPX (A5)
Analog Power (2.6 to 3.3V)
AF Hall Bias Output
Analog GND
Open
Open
Internal LDO Power Output








D2
EIRQ1
B
2.8








I2C Data I/O for DAC Monitor
UART Data Output (TXD)
SPI I/F Chip Select Output
Internal Signal Monitor
Servo Monitor Analog Input



I2C Data I/O for DAC Monitor
UART Data Input (RXD)
Servo Monitor Analog Out
Internal Signal Monitor
I2C Data I/O for DAC Monitor
UART Data Output
Internal Signal Monitor

I2C Data I/O for DAC Monitor
Internal Signal Monitor

I2C Data I/O for DAC Monitor
UART Data Output (TXD)
Servo Monitor Analog Out
Internal Signal Monitor
I2C Data I/O for DAC Monitor
UART Data Input
Internal Signal Monitor








B3
2.8
2.8
-
External IRQ1
External Clock Input
D3
D4
D5
AVSS
SDA
SCL
P
B
B

2.8
2.8
Analog GND
I2C Data
I2C Clock
E1
MON2
B
2.8
(Debugger Data Input)
E2
SCL2
(TXD)
B
2.8
I2C Clock for 2nd I2C
E3
DVSS
P

E4
EXCLK
B
2.8
E5
OUT5
O
2.8
Logic GND
External Clock Input
External IRQ1
AF Driver Output (H-Bridge, Linear)
F1
MON1
B
2.8
(Debugger Data Output)
F2
SDA2
(RXD)
B
2.8
I2C Data for 2nd I2C
F3
F4
F5
G1
G2
G3
G4
G5
WPB
PGND
OUT6
OUT4
OUT3
OUT2
OUT1
VM
I
P
O
O
O
O
O
P
2.8

2.8
2.8
2.8
2.8
2.8

Write Protect for Flash
Driver GND
AF Driver Output (H-Bridge, Linear)
Open
Open
Open
Open
Driver Power (2.6V to 3.3V)
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D

Z
Z
Z
Z

D

L
Z
D







LC898123F40XC
8. Electrical Characteristics
8-1 Logic
1) Absolute Maximum Rating at VSS=0V
Parameter
Power supply
voltage
Input voltage
(Except
DGDATA,DGSSB,DGSCLK,DGDIN)
Input voltage
(DGDATA,DGSSB,DGSCLK,DGDIN)
Storage temperature
Operating temperature
Symbol
Conditions
Ratings
Unit
VAD30 max
Ta  25C
0.3 to +4.6
V
VAI30
Ta  25C
0.3 to VAI30+0.3
V
VLDO18
Ta = 30 to +85C
0.3 to +1.872
V
Tstg
55 to +125
C
Topr
30 to +85
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
2) Allowable Operating Ratings at Ta=30 to +85C, VSS=0V
3.0V Power Supply (AVDD30)
Parameter
Power supply voltage
Input voltage range
Symbol
VAD30
VIN
Min
2.6
0
Typ
2.8

Max
3.3
VAD30
Unit
V
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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LC898123F40XC
3) DC Characteristics : Input/Output level at VSS= 0V, VDD=2.6 to 3.6V, Ta =30 to +85C
Parameter
High-level
voltage
Low-level
voltage
High-level
voltage
Low-level
voltage
High-level
voltage
Low-level
voltage
High-level
voltage
Low-level
voltage
High-level
voltage
Low-level
voltage
Symbol
input
input
input
input
input
input
input
input
input
input
High-level
voltage
output
High-level
voltage
output
Low-level
voltage
output
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
Conditions
CMOS
schmitt
CMOS
schmitt
CMOS
schmitt
CMOS
schmitt
CMOS
supported
Min
Typ
Max
Unit
1.36
V
0.39
V
1.26
V
0.35
Applicable Pin
SCL2(TXD), SDA2(RXD),
EXCLK
DGDIN, DGSSB,
DGSCLK, DGDATA
1.40
SCL, SDA
0.40
V
1.48
EIRQ1, WPB
0.37
1.40
MON1, MON2
0.51
AVDD30
0.4
V
1.32
V
SCL2(TXD), SDA2(RXD),
EXCLK, EIRQ1, MON1,
MON2
DGDIN, DGSSB,
DGSCLK, DGDATA
SCL2(TXD), SDA2(RXD),
DGDIN, DGSSB,
DGSCLK, DGDATA,
EXCLK, SDA, SCL
VOH
IOH=2mA
VOH
IOH=0.1mA
VOL
IOL=2mA
0.2
V
VOL
IOL=2mA
0.4
V
MON1,MON2,EIRQ1
OPINPAF, OPINMAF
MON1, MON2, EIRQ1,
SCL2(TXD), SD2(RXD)
DGDATA, DGDIN,
DGSSB, DGSCLK
MON1, MON2, EIRQ1,
SCL2(TXD), SDA2(RXD),
EXCLK, WPB
DGDATA, DGDIN,
DGSSB, DGSCLK
Low-level
output
voltage
Analog input voltage
VAI
AVSS
AVDD30
V
PullUp resistor
Rup
50
200
kΩ
PullUp resistor
Rup
180
800
kΩ
PullDown resistor
Rdn
50
220
kΩ
PullDown resistor
Rdn
120
500
kΩ
4) Non-volatile Memory Characteristics
Parameter
Endurance
Data retention
Symbol
EN
RT
Condition
Min
10
Typ
Max
1000
Unit
Cycles
Years
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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LC898123F40XC
8-2 Driver
1) Absolute Maximum Rating
Parameter
Power supply voltage
Symbol
VMmax
Condition
Output peak current
Iopeak
OUT5, OUT6
t  10ms,
ON-duty  20%
Output continuous current
Iomax
OUT5, OUT6
Ratings
4.6
Unit
V
200
mA
157.5
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
2) Allowable Operating Ratings
Parameter
Ambient temperature
Symbol
Topg
Power supply voltage
VM
Condition
Ratings
30 to +85
1.75 to 3.3
2.6 to 3.3
Constant Current
H-Bridge PWM
Unit
C
V
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
3) H-Bridge Driver Output at Ta=25C, AVDD30=VM=2.8V
Parameter
Output ON resistance
OUT1 to OUT4
Output ON resistance
OUT5, OUT6
Symbol
Ronu
Rond
Ronu
Rond
Condition
typ
0.5
1.0 (*1)
1.1
1.3 (*1)
Unit
Ω
Ω
Ω
Ω
4) Constant Current Driver Output at Ta=25C, AVDD30=VM=2.8V
Parameter
Output Current
OUT5, OUT6
Compliance Voltage
OUT5, OUT6
Symbol
Ifull
Condition
OP-AF (unidirection)
Full code
OP-AF (bidirection)
CL-AF
Full code
Typ
Max
150
157.5
142.5
150
157.5
Unit
mA
mA
mA
0.4
OP-AF (unidirection)
Vcomp
Min
142.5
V
OP-AF (bidirection)
CL-AF
0.5
V
OP-AF (unidirection)
VCM resistance (Rvcm) = (VM  Vcomp_Min) / Io []
OP-AF(bidirection) / CL-AF
VCM resistance (Rvcm) = (VM  (Ronu*Io + Vcomp_Min)) / Io []
Output ON resistance (Ron) = VM/Io  Rvcm []
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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9
LC898123F40XC
9. AC Characteristics
9-1 Power Sequence
Item
Symbol
Rise time
tR
Wait time
tW
Bottom Voltage
Min
Typ
Max
Units
3
ms
100
Vbot
ms
0.2
V
Injection order between AVDD30 and VM is below.
tVMrd
tAVfd
2.6V
2.6V
AVDD30
VM ≤ AVDD30 +
0.5V
(VM ≤ 3.3V)
VM
tVMrd > 0ms
tAVfd > 0ms
WPB
WPB must be open or pull down normally. When Erase or Program is made to Flash, WPB have to be High.
SDA, SCL, EXCLK, WPB tolerate 3V input at the time of power off.
The data in the flash memory may be rewritten unintentionally if you do not keep specifications.
And it is forbidden to power off during flash access. The data in the flash memory may be rewritten unintentionally.
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LC898123F40XC
9-2 Two Wire Serial Interface Timing
The communication protocol is compatible with I2C (Fast mode Plus).
This circuit has clock stretch function.
SD
SCL
Item
SCL clock frequency
START condition
hold time
SCL clock
Low period
SCL clock
High period
Setup time for repetition START
condition
Symbol
Min
Typ
Max
Units
1000
kHz
Fscl
SCL
tHD,STA
SCL
SDA
0.26
s
tLOW
SCL
0.5
s
tHIGH
SCL
0.26
s
0.26
s
tSU,STA
Data hold time
tHD,DAT
Data setup time
tSU,DAT
SDA, SCL
rising time
SDA, SCL
falling time
Pin name
tr
tf
STOP condition setup time
tSU,STO
Bus free time between STOP
and START
tBUF
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
0 (*1)
0.9
50
s
ns
120
ns
120
ns
0.26
s
0.5
s
(*1) Although the I2C specification defines a condition that 300 ns of hold time is required internally,
LC898123F40XC is designed for a condition with typ. 40 ns of hold time. If SDA signal is unstable
around falling point of SCL signal, please implement an appropriate treatment on board, such as
inserting a resistor.
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LC898123F40XC
ORDERING INFORMATION
Device
LC898123F40XC-VH
Package
Shipping (Qty / Packing)
WLCSP35, 3.22x2.3
(Pb-Free / Halogen Free)
4000 / Tape & Reel
† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
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