View detail for SAM3S Microcontroller Series Schematic Check List

SAM3S Microcontroller Series
Schematic Check List
1. Introduction
This Application Note is a schematic review check list for systems embedding Atmel’s
SAM3S series of ARM® Cortex™-M3, Thumb®2-based microcontrollers.
It gives requirements concerning the different pin connections that must be considered before starting any new board design and describes the minimum hardware
resources required to quickly develop an application with the SAM3S Series. It does
not consider PCB layout constraints.
It also gives advice regarding low-power design constraints to minimize power
consumption.
This Application Note is not intended to be exhaustive. Its objective is to cover as
many configurations of use as possible.
AT91 ARM
Thumb-based
Microcontrollers
Application Note
The Check List table has a column reserved for reviewing designers to verify that the
line item has been checked.
11061A–ATARM–28-Jul-10
2. Associated Documentation
Before going further into this Application Note, it is strongly recommended to check the latest
documents for the SAM3S Series Microcontrollers on Atmel’s Web site.
Table 2-1 gives the associated documentation needed to support full understanding of this application note.
Table 2-1.
2
Associated Documentation
Information
Document Title
User Manual
Electrical/Mechanical Characteristics
Ordering Information
Errata
SAM3S Series Product Datasheet
Internal architecture of processor
Thumb2 instruction sets
Embedded in-circuit-emulator
This part is integrated and formated according to the core integration in the
SAM3S series. This information is fully detailed in the SAM3S Series Product
Datasheet.
Cortex-M3 Technical Reference Manual (available from ARM Ltd.)
Evaluation Kit User Guide
SAM3S-EK Evaluation Board User Guide
Application Note
11061A–ATARM–28-Jul-10
Application Note
3. Schematic Check List
Single Power Supply Strategy
VDDIO
USB
Transceivers
ADC, DAC,
Analog Comparator
Main Supply (1.8V-3.6V)
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDPLL
Single Power Supply Schematic Example:
;
Signal Name
Recommended Pin Connection
Description
VDDIN
1.8V to 3.6V
Decoupling/Filtering capacitor
(10μF or higher ceramic capacitor)(1)(2)
Powers the voltage regulator, ADC, DAC and Analog
comparator power supply.
Powers the peripheral I/Os, USB transceiver, Backup
VDDIO
1.62V to 3.6V
Decoupling/Filtering capacitors
(100 nF and 2.2µF)(1)(2)
VDDOUT
Decoupling/Filtering capacitors
(100 nF and 2.2µF)(1)(2)
part, 32kHz crystal oscillator and oscillator pads.
Decoupling/Filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
Warning: At power-up VDDIO needs to reach 0.6V
before VDDIN reaches 1.0V
1.8V Output of the main voltage regulator.
Decoupling/Filtering capacitors must be added to
guarantee stability.
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11061A–ATARM–28-Jul-10
;
Signal Name
Recommended Pin Connection
Description
VDDCORE
Must be connected directly to VDDOUT
pin.
1.62V to 1.95V
Decoupling capacitor (100 nF)(1)(2)
Power the Core, the embedded memories and the
peripherals power supply.
VDDPLL
1.62V to 1.95V
Decoupling capacitor (100 nF)(1)(2)
Powers PLLA, PLLB, the Farst RC and the 3-20 MHz
oscillator.
GND
Ground
Ground pins GND are common to VDDIO, VDDPLL and
VDDCORE
Note: Restrictions
With Main Supply < 2.0 V, USB and ADC/DAC and Analog comparator are not usable.
With Main Supply ≥ 2.0V and < 3V, USB is not usable.
With Main Supply ≥ 3V, all peripherals are usable.
4
Application Note
11061A–ATARM–28-Jul-10
Application Note
Core Externally Supplied.
VDDIO
USB
Transceivers
ADC, DAC,
Analog Comparator
Main Supply (1.8V-3.6V)
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE Supply (1.62V-1.95V)
VDDCORE
VDDPLL
Core externally supplied Schematic Example:
Main Supply on VDDIO, and VDDIN (1.8V to 3.6V).
VDDCORE Supply is between 1.62V and 1.95V.
;
Signal Name
Recommended Pin Connection
Description
VDDIN
1.8V to 3.6V
Decoupling/Filtering capacitor
(10μF or higher ceramic capacitor)(1)(2)
Powers the voltage regulator, ADC, DAC and Analog
comparator power supply.
VDDIO
1.62V to 3.6V
Connected to Main Supply
Decoupling/Filtering capacitors
(100 nF and 2.2 µF)(1)(2)
Powers the peripheral I/Os.
Decoupling/Filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
Warning: At power-up VDDIO needs to reach 0.6V
before VDDIN reaches 1.0V
VDDOUT
Decoupling/Filtering capacitors
(100 nF and 2.2µF)(1)(2)
1.8V Output of the main voltage regulator.
Decoupling/Filtering capacitors must be added to
guarantee stability.
5
11061A–ATARM–28-Jul-10
;
Signal Name
Recommended Pin Connection
Description
VDDCORE
1.62V to 1.95V
Connected to VDDCORE Supply
Decoupling capacitor (100 nF and
2.2µF)(1)(2)
Core, embedded memories and peripherals power supply
VDDPLL
1.62V to 1.95V
Connected to VDDCORE Supply
Decoupling capacitor (100 nF and
2.2µF)(1)(2)
Powers PLLA, PLLB, the Farst RC and the 3-20 MHz
oscillator.
GND
Ground
Ground pins GND are common to VDDIO, VDDPLL and
VDDCORE
Note: Restrictions
With Main Supply < 2.0 V, USB and ADC/DAC and Analog comparator are not usable.
With Main Supply ≥ 2.0V and < 3V, USB is not usable.
With Main Supply ≥ 3V, all peripherals are usable.
6
Application Note
11061A–ATARM–28-Jul-10
Application Note
Backup Unit Externally Supplied
VDDIO
Backup
Battery
USB
Transceivers
+
-
ADC, DAC,
Analog Comparator
VDDIN
Main Supply
Voltage
Regulator
OUT
IN
3.3V
LDO
ON/OFF
VDDOUT
VDDCORE
VDDPLL
PIOx (output)
External Wakeup signal
;
WAKEUPx
Signal Name
Recommended Pin Connection
Description
VDDIN
1.8V to 3.6V
Decoupling/Filtering capacitor
(10μF or higher ceramic capacitor)(1)(2)
Powers the voltage regulator.
VDDIO
1.62V to 3.6V
Decoupling/Filtering capacitors
(100 nF and 2.2 µF)(1)(2)
Powers the peripheral I/Os.
Decoupling/Filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
Warning: At power-up VDDIO needs to reach 0.6V
before VDDIN reaches 1.0V
VDDOUT
Decoupling/Filtering capacitors
(100 nF and 2.2µF)(1)(2)
1.8V Output of the main voltage regulator.
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11061A–ATARM–28-Jul-10
;
Signal Name
Recommended Pin Connection
Description
VDDCORE
1.62V to 1.95V
Connected to VDDOUT Supply
Decoupling capacitor (100 nF)(1)(2)
Core, embedded memories and peripherals power supply
VDDPLL
1.62V to 1.95V
Connected to VDDOUT Supply
Decoupling capacitor (100 nF)(1)(2)
Powers PLLA, PLLB, the Farst RC and the 3-20 MHz
oscillator.
GND
Ground
Ground pins GND are common to VDDIO, VDDPLL and
VDDCORE
Note: The two diodes provide a "switchover circuit" (for illustration purpose) between the backup battery and the main supply when the system is put in backup mode.
8
Application Note
11061A–ATARM–28-Jul-10
Application Note
;
Signal Name
Recommended Pin Connection
Description
Clock, Oscillator and PLL
Internal Equivalent Load Capacitance (CL):
CL = 9.5 pF
Crystal Load Capacitance, ESR, Drive Level and Shunt
Capacitance to validate.
AT91SAM3S
CL
XIN
XOUT
GND
Crystals between 3 and 20 MHz
PB9/XIN
PB8/XOUT
Main Oscillator
in
Normal Mode
Capacitors on XIN and XOUT
(crystal load capacitance dependant)
1 kOhm resistor on XOUT only required for
crystals with frequencies lower than 8 MHz.
1K
8 MHz
C CRYSTAL
C LEXT
C LEXT
The external load capacitance is calculated with the
following formula:
CLEXT=2*(Ccrystal-CL)
Refer to the Crystal Oscillators Design Consideration
Information section of the SAM3S Series Datasheet.
By default, at startup the chip runs out of the Master
Clock using the fast RC oscillator running at 4 MHz.
PB9/XIN
PB8/XOUT
Main Oscillator
in
Bypass Mode
4/8/12MHz Fast
Internal RC
Oscillator
PB9/XIN: external clock source
PB8/XOUT: can be left unconnected or
used as GPIO.
1.62V to 3.6V Square wave signal (VDDIO)External Clock
Source up to 50 MHz
Duty Cycle: 45 to 55%
By default, at startup the chip runs out of the Master
Clock using the fast RC oscillator running at 4 MHz.
PB9/XIN and PB8/XOUT: can be left
unconnected or used as GPIO
Powers up by VDDPLL 1.62V to 1.95V
The output frequency is configurable through the PMC
registers .
The Fast RC oscillator is calibrated in production.
The frequency can be trimmed by softtware
Duty Cycle: 45 to 55%
By default, at startup the chip runs out of the Master
Clock using the fast RC oscillator running at 4 MHz.
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11061A–ATARM–28-Jul-10
;
Signal Name
Recommended Pin Connection
Description
Internal parasistic capacitance Cpara=1pF
Crystal Load Capacitance, ESR, Drive Level and Shunt
Capacitance to validate.
.
SAM3
PA7/XIN32
PA8/XOUT32
32 kHz Crystal
used
XOUT32
XIN32
32.768 kHz Crystal Capacitors on XIN32
and XOUT32
(crystal load capacitance dependent)
C LEXT
CLEXT
CLEXTmax=20pF
CLEXT= 2x(Ccrystal-Cpara- Cpcb)
Refer to the Crystal Oscillators Design Consideration
Information section of the SAM3S Series Datasheet.
By default at start-up the chip runs out of the embeded
32 kHz RC oscillator
PA7/XIN32
PA8/XOUT32
32 kHz Oscillator
in bypass mode
10
PA7/XIN32: external clock source
PA8/XOUT32: can be left unconnectde or
use a GPIO.
1.62V to 3.6V Square wave signal (VDDIO)
External Clock Source up to 44 kHz
Duty Cycle: 45 to 55%
By default at start-up the chip runs out of the embeded
32 kHz RC oscillator
Application Note
11061A–ATARM–28-Jul-10
Application Note
;
Signal Name
Recommended Pin Connection
Description
(3)
Serial Wire and JTAG
Application dependant
If debug mode is not required this pin can
be use as GPIO
Reset State:
- SWJ-DP Mode
- Internal pull-up disabled
- Schmitt Trigger enabled
Application dependant
If debug mode is not required this pin can
be use as GPIO
Reset State:
- SWJ-DP Mode
- Internal pull-up disabled
- Schmitt Trigger enabled
Application dependant
If debug mode is not required this pin can
be use as GPIO
Reset State:
- SWJ-DP Mode
- Internal pull-up disabled
- Schmitt Trigger enabled
TDO/
TRACESWO/PB5
Application dependant
If debug mode is not required this pin can
be use as GPIO
Reset State:
- SWJ-DP Mode
- Internal pull-up disabled
- Schmitt Trigger enabled
JTAGSEL
Application dependant.
Must be tied to VVDDIO to enter JTAG
Boundary Scan.
In harsh environments, It is strongly
recommended to tie this pin to GND.
Permanent Internal pull-down resistor (15 kOhm).
TCK/SWCLK/PB7
TMS/SWDIO/PB6
TDI/PB4
Flash Memory
Internal pull-down resistor (100kOhm).
ERASE/PB12
Application dependant.
If hardware erase is not required this pin
can be use as GPIO
Must be tied to VVDDIO to erase the General Purpose NVM
bits (GPNVMx), the whole Flash content and the security
bit.
Reset state: Erase Input, with a 100 kOhm Internal pull
down and Schmitt trigger enabled
Minimum debouncing time is 220 ms.
Reset/Test
NRST
Application dependant.
Can be connected to a push button for
hardware reset.
TST
TST pin can be left unconnected in
normal mode
To enter in FFPI mode TST pin must be tied
to VVDDIO.
In harsh environments, It is strongly
recommended to tie this pin to GND.
By default, the NRST pin is configured as an input
Permanent internal pull-up resistor to VVDDIO (15 kOhm).
Permanent internal pull-down resistor (15 kOhm).
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11061A–ATARM–28-Jul-10
;
Signal Name
Recommended Pin Connection
Description
PIO
At reset, all PIOs are in IO or System IO mode with Schmitt
trigger inputs and internal pull-up enabled.
PAx - PBx-PCx
Application Dependant
(Pulled-up on VVDDIO)
To reduce power consumption, if not used, the concerned
PIO can be configured as an output and driven at ‘0’ with
internal pull-up disabled.
Parallel Capture Mode
PIODC0-PIODC7
Application Dependant VVDDIO
Parallel Mode capture Data
PIODCCLK
Application Dependant VVDDIO
Parallel Mode capture Clock
PIODCEN1-2
Application Dependant VVDDIO
Parallel Mode capture mode enable
Analog Reference
2.0V to VDDIO(*)
Decoupling capacitor(s).
ADVREF
ADVREF is a pure analog input.
ADVREF is the voltage reference for the ADC,DAC and
Analog comparator.
(*)2.0V is used for 10-bit ADC resolution
only. In other case the minimum ADVREF
value is 2.4V.
To reduce power consumption, if analog features are not
used, connect ADVREF to GND.
12-bit ADC
AD0-AD14
0 to ADVREF.
ADTRG
VDDIO.
ADC Channels
ADC External Trigger input
(4)
10-bit ADC
AD0-AD14
0 to ADVREF.
ADC Channels
ADTRG
VDDIO.
ADC External Trigger input
12-bit DAC
DAC0-DAC1
1/6* ADVREF to 5/6* ADVREF
DACTRG
VDDIO.
DAC External Trigger input
USB Device (UDP)
12
DDP/PB10
Application dependent(3)
If USB device support is not required this
pin can be use as GPIO
Reset State:
- USB Mode
- Internal Pull-down
DDM/PB11
Application dependent(3)
If USB device support is not required this
pin can be use as GPIO
IReset State:
- USB Mode
- Internal Pull-down
Application Note
11061A–ATARM–28-Jul-10
Application Note
;
Signal Name
Recommended Pin Connection
Description
Static Memory Controller (SMC)
D0-D15
A0-A23
Application dependent.
Data Bus (D0 to D15)
Note: Data bus lines are multiplexed with
the PIOB controller. Their I/O line reset state is
input with pull-up enabled.
Application dependent.
Address Bus (A0 to A23)
Note: Data bus lines are multiplexed with
the PIOB & PIOC controllers. Their I/O line reset state is
input with pull-up enabled.
NWAIT pin is an active low input.
NWAIT
Notes:
Application dependent.
Note: NWAIT is multiplexed with PC18.
1. These values are given only as a typical example.
2. Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin.
100nF
VDDCORE
100nF
VDDCORE
100nF
VDDCORE
GND
3. USB Device Typical connection: copy of Figure 37-2 of the Datasheet
4. Note that the ADC voltages in 10-bit mode resolution (ADC 12-bit in low resolution) can descend to 2.0V. Only one ADC is
available on the SAM3S series.
13
11061A–ATARM–28-Jul-10
4. SAM3S Boot Program Hardware Constraints
See AT91SAM Boot Program section of the SAM3S Series Datasheet for more details on the boot
program.
4.1
SAM-BA Boot
The SAM-BA® Boot Assistant supports serial communication via the UART or USB device port:
• UART0 Hardware Requirements: none.
• USB Device Hardware Requirements:
External Crystal or External Clock(1) with frequency of:
11,289 MHz
12,000 MHz
16,000 MHz
18,432 MHz
Note:
1. Must be 2500 ppm and 1.8V Square Wave Signal
Table 4-1.
14
Pins driven during SAM-BA Boot Program execution
Peripheral
Pin
PIO Line
UART0
URXD
PA9
UART0
UTXD
PA10
Application Note
11061A–ATARM–28-Jul-10
Application Note
5. Revision History
Table 5-1.
Revision History
Doc. Rev
Date
Comments
11061A
28-Jul-10
First issue
Change
Request Ref.
15
11061A–ATARM–28-Jul-10
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11061A–ATARM–28-Jul-10