View detail for Atmel AT03463: SAM4S Schematic Checklist

APPLICATION NOTE
AT03463: SAM4S Schematic Checklist
Atmel 32-bit Microcontrollers
Introduction
A good hardware design comes from a proper schematic. Since the Atmel®
SAM4S microcontrollers have a fair number of pins and functions, the schematic
for these devices can be large and quite complex.
This application note describes a common checklist, which should be used when
starting and reviewing the schematics for a SAM4S design.
Features
 Power circuits
 ADC connection
 Clock and crystal oscillators
 JTAG and SWD debug ports
 USB connection
 Boot Program constraints
 Suggested reading
Atmel-42155E-SAM4S-Schematic-Checklist_ApplicationNote_AT03463_112015
Ta bl e of Conte nts
1
Schematic Checklist .................................................................................................... 3
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
2
SAM4S Boot Program Constraints ........................................................................... 14
2.1
3
2
SAM-BA Boot ...................................................................................................................................... 14
Suggested Reading ................................................................................................... 15
3.1
3.2
3.3
3.4
4
Single Power Supply Strategy ............................................................................................................... 3
Dual Power Supply Strategy ................................................................................................................. 5
Backup Unit Externally Supplied ........................................................................................................... 7
Clocks, Oscillator, and PLL ................................................................................................................... 9
Serial Wire and JTAG.......................................................................................................................... 10
Flash Memory ..................................................................................................................................... 11
Reset and Test Pins ............................................................................................................................ 11
PIOs
.............................................................................................................................................. 11
Parallel Capture Mode......................................................................................................................... 11
Analog Reference................................................................................................................................ 12
12-bit and 10-bit ADC (3) ...................................................................................................................... 12
12-bit DAC........................................................................................................................................... 12
USB Device (UDP) .............................................................................................................................. 12
Static Memory Controller (SMC) ......................................................................................................... 13
Device Datasheet ................................................................................................................................ 15
Evaluation Kit User Guide ................................................................................................................... 15
USB Specification................................................................................................................................ 15
ARM Documentation on Cortex-M4 Core ............................................................................................ 15
Revision History ........................................................................................................ 16
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Schematic Checklist
1.1
Single Power Supply Strategy
Figure 1-1.
Single Power Supply Schematic Example
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Table 1-1.
Single Power Supply Checklist
Signal name
VDDIN
Recommended pin connection
1.62V to 3.6V
Decoupling/filtering capacitors
(100nF or higher ceramic capacitor)
Description
Powers the voltage regulator, ADC, DAC, and Analog
comparator power supply.
(1)(2)
VDDIO
VDDOUT
VDDCORE
VDDPLL
GND
Note:
Powers the peripheral I/Os, USB transceiver, Backup
part, 32kHz crystal oscillator, and oscillator pads. Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
1.62V to 3.6V
Decoupling/filtering capacitors
(100nF and 10μF) (1)(2)
Warning:
At power-up VDDIO needs to reach
0.6V before VDDIN reaches 1.0V.
Warning:
VDDIO voltage needs to be equal or
below to (VDDIN voltage +0.5V).
Decoupling/filtering capacitor
(100nF and 2.2μF) (1)(2)
1.2V output of the main voltage regulator. Decoupling/filtering capacitors must be added to guarantee stability.
1.08V to 1.32V
Must be connected directly to
VDDOUT pin.
Decoupling capacitor (100nF) (1)(2)
Power the core, the embedded memories and the peripherals.
1.08V to 1.32V
Decoupling/filtering RLC circuit
Powers PLLA, PLLB, the Fast RC, and the 3 - 20MHz
oscillator.
Maximum voltage ripple is 10mV.
Ground
(1)(2)
Ground pins GND are common to VDDIO, VDDPLL,
and VDDCORE
Restrictions:
With main supply <2.0V, USB, ADC/DAC, and Analog Comparator are not usable.
With main supply ≥2.0V and <3V, USB is not usable.
With main supply ≥3V, all peripherals are usable.
Notes:
4
1.
2.
These values are given only as a typical example.
Capacitors should be placed as close as possible to each pin in the signal group, vias should be avoided.
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1.2
Dual Power Supply Strategy
Figure 1-2.
Dual Power Supply Schematic Example
Main supply
(1.62V – 3.6V)
ADC, DAC, Analog
comparator supply
(2.0V – 3.6V)
VDDIO
100nF
USB
Transceivers
10µF
ADC, DAC,
Analog comparator
Can be the same
supply
VDDIN
Voltage
regulator
100nF
100nF
VDDOUT
2.2µF
VDDCORE supply
(1.08V – 1.32V)
VDDCORE
100nF
10µF
10µH
VDDPLL
100nF
1R
4.7µF
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Table 1-2.
Dual Power Supply Checklist
Signal name
VDDIN
Recommended pin connection
2.0V to 3.6V
Decoupling/filtering capacitors
(100nF or higher ceramic capacitor)
Description
Powers the voltage regulator, ADC, DAC, and Analog
Comparator power supply.
(1)(2)
VDDIO
Warning:
At power-up VDDIO needs to reach
0.6V before VDDIN reaches 1.0V.
Warning:
VDDIO voltage needs to be equal or
below to (VDDIN voltage +0.5V).
Decoupling/filtering capacitor
(100nF and 2.2μF) (1)(2)
1.2V output of the main voltage regulator. Decoupling/filtering capacitors must be added to guarantee stability.
VDDCORE
1.08V to 1.32V
Connected to VDDCORE supply
Decoupling capacitor (100nF) (1)(2)
Power the Core, the embedded memories and the peripherals.
VDDPLL
1.08V to 1.32V
Connected to VDDCORE supply
Decoupling/filtering RLC circuit (1)(2)
Powers PLLA, PLLB, the Fast RC, and the 3 - 20MHz
oscillator.
Maximum voltage ripple is 10mV.
Ground
Ground pins GND are common to VDDIO, VDDPLL,
and VDDCORE
VDDOUT
GND
Note:
1.62V to 3.6V
Connected to main supply
Decoupling/filtering capacitors
(100nF and 10μF) (1)(2)
Powers the peripheral I/Os, USB transceiver, Backup
part, 32kHz crystal oscillator, and oscillator pads. Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
Restrictions:
For USB, VDDIO needs to be greater than 3.0V.
For ADC, VDDIN needs to be greater than 2.0V.
For DAC, VDDIN needs to be greater than 2.4V.
Notes:
6
1.
2.
These values are given only as a typical example.
Capacitor should be placed as close as possible to each pin in the signal group, vias should be avoided.
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1.3
Backup Unit Externally Supplied
Figure 1-3.
Note:
Backup Unit Externally Supplied Schematic Example
The two diodes provide a “switchover circuit” (for illustration purpose) between the backup battery and
the main supply when the system is put in backup mode.
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Table 1-3.
Backup Unit Externally Supplied Checklist
Signal name
VDDIN
Recommended pin connection
1.62V to 3.6V
Decoupling/filtering capacitors
(100nF or higher ceramic capacitor)
Description
Powers the voltage regulator
(1)(2)
VDDIO
1.62V to 3.6V
Decoupling/filtering capacitors
(100nF and 10μF) (1)(2)
Warning:
At power-up VDDIO needs to reach
0.6V before VDDIN reaches 1.0V.
Warning:
VDDIO voltage needs to be equal or
below to (VDDIN voltage +0.5V).
VDDIOUT
Decoupling/filtering capacitor
(100nF and 2.2μF) (1)(2)
1.2V output of the main voltage regulator. Decoupling/filtering capacitors must be added to guarantee stability.
VDDCORE
1.08V to 1.32V
Connected to VDDOUT supply
Decoupling capacitor (100nF) (1)(2)
Power the Core, the embedded memories and the peripherals.
1.08V to 1.32V
Connected to VDDOUT supply
Decoupling/filtering RLC circuit
Powers PLLA, PLLB, the Fast RC and the 3 - 20MHz
oscillator.
Maximum voltage ripple is 10mV.
VDDPLL
GND
Note:
Powers the peripheral I/Os, USB transceiver, Backup
part, 32kHz crystal oscillator, and oscillator pads. Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
Ground
(1)(2)
Ground pins GND are common to VDDIO, VDDPLL,
and VDDCORE
Restrictions:
For USB, VDDIO needs to be greater than 3.0V.
For ADC, VDDIN needs to be greater than 2.0V.
For DAC, VDDIN needs to be greater than 2.4V.
Notes:
8
1.
2.
These values are given only as a typical example.
Capacitor should be placed as close as possible to each pin in the signal group, vias should be avoided.
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1.4
Clocks, Oscillator, and PLL
Table 1-4.
Clocks, Oscillator, and PLL Checklist
Signal name
Recommended pin connection
Description
Internal Equivalent Load Capacitance (CL):
CL = 9.5pF
Crystal Load Capacitance, ESR, Drive Level, and Shunt
Capacitance to validate.
CL
SAM4S
Crystals between 3 and 20MHz
PB9/XIN
PB8/XOUT
Main oscillator
in Normal mode
XIN
XOUT
Capacitors on XIN and XOUT
(crystal load capacitance dependent)
CCRYSTAL
1kΩ resistor on XOUT only required for crystals with frequencies lower than 8MHz.
CLEXT
CLEXT
The external load capacitance is calculated with the following formula:
CLEXT = 2 * (Ccrystal-CL)
Refer to the Crystal Oscillators Design Consideration Information section of the SAM4S Series Datasheet.
By default, at startup the chip runs out of the Master
Clock using the fast RC oscillator running at 4MHz.
PB9/XIN
PB8/XOUT
Main oscillator
in Bypass mode
4/8/12MHz fast
internal RC oscillator
PB9/XIN: external clock source.
PB8/XOUT: can be left unconnected or used as GPIO.
1.62V to 3.6V Square wave signal (VDDIO)
External Clock Source up to 50MHz Duty Cycle: 40 to 60%.
By default, at startup the chip runs out of the Master
Clock using the fast RC oscillator running at 4MHz.
PB9/XIN and PB8/XOUT: can be
left unconnected or used as
GPIO.
Powered up by VDDPLL
The output frequency is configurable through the PMC registers.
The Fast RC oscillator is calibrated in production.
The frequency can be trimmed by software.
Duty Cycle: 40 to 60%.
By default, at startup the chip runs out of the Master
Clock using the fast RC oscillator running at 4MHz.
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Internal parasitic capacitance Cpara=0.7pF Crystal Load Capacitance, ESR, Drive Level, and Shunt Capacitance to validate.
SAM4S
XIN32
PA7/XIN32
PA8/XOUT32
32kHz crystal
used
32.768kHz crystal capacitors on
XIN32 and XOUT32 (crystal load
capacitance dependent).
CLEXT
XOUT32
CCRYSTAL
CLEXT
CLEXTmax = 20pF
CLEXT = 2 * (Ccrystal-Cpara- Cpcb)
Refer to the Crystal Oscillators Design Consideration Information section of the SAM4S Series Datasheet.
By default at start-up the chip runs out of the embedded 32kHz RC oscillator.
PA7/XIN32
PA8/XOUT32
32kHz oscillator
in bypass mode
1.5
PA7/XIN32: external clock
source PA8/XOUT32: can be left
unconnected or use as GPIO.
Serial Wire and JTAG
Signal name
Recommended pin connection
Description
TCK/SWCLK/PB7
Application dependent.
If debug mode is not required this pin
can be use as GPIO.
Reset state:
- SWJ-DP Mode
- Internal pull-up disabled
- Schmitt Trigger enabled
TMS/SWDIO/PB6
Application dependent.
If debug mode is not required this pin
can be use as GPIO.
Reset state:
- SWJ-DP Mode
- Internal pull-up disabled
- Schmitt Trigger enabled
TDI/PB4
Application dependent.
If debug mode is not required this pin
can be use as GPIO.
Reset state:
- SWJ-DP Mode
- Internal pull-up disabled
- Schmitt Trigger enabled
TDO/TRACESWO/PB5
Application dependent.
If debug mode is not required this pin
can be use as GPIO.
Reset state:
- SWJ-DP Mode
- Internal pull-up disabled
- Schmitt Trigger enabled
Application dependent.
Must be tied to VDDIO to enter JTAG
Boundary Scan.
In harsh environments, it is strongly
recommended to tie this pin to GND.
Permanent internal pull-down resistor
(15kΩ)
JTAGSEL
10
1.62V to 3.6V Square wave signal (VDDIO).
External Clock Source up to 44kHz.
Duty Cycle: 40 to 60%.
By default at start-up the chip runs out of the embedded 32kHz RC oscillator.
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1.6
Flash Memory
Signal name
ERASE/PB12
1.7
Recommended pin connection
Application dependent.
If hardware erase is not required this
pin can be use as GPIO.
Description
Internal pull-down resistor (100kΩ).
Must be tied to VDDIO to erase the General
Purpose NVM bits (GPNVMx), the whole
Flash content and the security bit.
Reset state: Erase Input, with a 100kΩ Internal pull down and Schmitt trigger enabled.
Reset and Test Pins
Signal name
NRST
Recommended pin connection
Application dependent.
If hardware erase is not required this
pin can be use as GPIO.
Description
Internal pull-down resistor (100kΩ).
Must be tied to VDDIO to erase the General
Purpose NVM bits (GPNVMx), the whole
Flash content and the security bit.
Reset state: Erase Input, with a 100kΩ Internal pull down and Schmitt trigger enabled.
Minimum debouncing time is 220ms.
TST
1.8
TST pin can be left unconnected in normal mode.
To enter in FFPI mode TST pin must be
tied to VDDIO.
In harsh environments, it is strongly
recommended to tie this pin to GND.
Permanent internal pull-down resistor
(15kΩ).
Recommended pin connection
Description
PIOs
Signal name
At reset, all PIOs are in I/O or System I/O
mode with Schmitt trigger inputs and internal pull-up enabled.
PAx - PBx-PCx
1.9
Application dependent
(Pulled-up on VDDIO)
To reduce power consumption, if not used,
the concerned PIO can be configured as an
output and driven at ‘0’ with internal pull-up
disabled.
Parallel Capture Mode
Signal name
Recommended pin connection
Description
PIODC0-PIODC7
Application dependent
(Pulled-up on VDDIO)
Parallel Mode capture Data
PIODCCLK
Application dependent
(Pulled-up on VDDIO)
Parallel Mode capture Clock
PIODCEN1-2
Application dependent
(Pulled-up on VDDIO)
Parallel Mode capture mode enable
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1.10
Analog Reference
Signal name
ADVREF
1.11
AD0-AD14
ADTRG
Note:
2.0V to VDDIN (*)
Decoupling capacitor(s).
ADVREF is a pure analog input.
ADVREF is the voltage reference for the
ADC, DAC, and Analog comparator.
(*) 2.0V is used for 10-bit ADC resolution
only. In other case the minimum ADVREF
value is 2.4V.
To reduce power consumption, if analog
features are not used, connect ADVREF to
GND.
Recommended pin connection
Description
0 to ADVREF
ADC channels
VDDIO
ADC External Trigger input
3. The ADC voltages in 10-bit mode resolution (ADC 12-bit in low resolution) can descend to 2.0V.
12-bit DAC
Signal name
Recommended pin connection
Description
DAC0-DAC1
1/6 * ADVREF to 5/6 * ADVREF
-
VDDIO
DAC External Trigger input
DACTRG
1.13
Description
12-bit and 10-bit ADC (3)
Signal name
1.12
Recommended pin connection
USB Device (UDP)
Signal name
Recommended pin connection
Description
(4)
DDP/PB11
Application dependent
If USB device support is not required
this pin can be used as GPIO.
If UDP is not used, this pin can be left
unconnected.
DDM/PB10
Application dependent (4)
If USB device support is not required
this pin can be used as GPIO.
If UDP is not used, this pin can be left
unconnected.
Note:
PIO
Reset State:
- USB mode
- Internal pull-down
Reset State:
- USB mode
- Internal pull-down
4. USB device typical connection:
5V Bus monitoring
27k
47k
REXT
DDM
REXT
DDP
12
1
2
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Type B
connector
4
1.14
Static Memory Controller (SMC)
Signal name
Recommended pin connection
Description
Data Bus (D0 to D15)
D0-D15
Application dependent
Note: Data bus lines are multiplexed with the
PIOC controller. Their I/O line reset state is input
with pull-up enabled.
Address Bus (A0 to A23)
A0-A23
Application dependent
NWAIT
Application dependent
Note: Data bus lines are multiplexed with the
PIOA and PIOC controllers. Their I/O line reset
state is input with pull-up enabled.
NWAIT pin is an active low input.
Note: NWAIT is multiplexed with PC13.
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SAM4S Boot Program Constraints
See AT91SAM Boot Program section of the SAM4S Series Datasheet for more details on the boot program.
2.1
SAM-BA Boot
The SAM-BA® Boot Assistant supports serial communication via the UART or USB device port:

UART0 Hardware Requirements: none

USB Device Hardware Requirements: external crystal or External clock
11.289MHz / 12.000MHz / 16.000MHz / 18.432MHz
Note:
with frequency of:
1. Must be 2500ppm and 1.62V to 3.6V (VDDIO) Square Wave Signal.
Table 2-1.
14
(1)
Pins Driven During SAM-BA Boot Program Execution
Peripheral
Pin
PIO line
UART0
URXD0
PA9
UART0
UTXD0
PA10
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Suggested Reading
3.1
Device Datasheet
The device datasheet contains block diagrams of the peripherals and details about implementing firmware for
the device. It also contains the electrical specifications and expected characteristics of the device.
The datasheet is available on http://www.atmel.com/products/microcontrollers/arm/sam4s.aspx in the
datasheets section of the product page.
3.2
Evaluation Kit User Guide
The SAM4S-EK user guide contains schematics that can be used as a starting point when designing with the
SAM4S devices. This user guide is available on http://www.atmel.com/tools/SAM4S-EK.aspx in the documents
section of the SAM4S-EK page.
3.3
USB Specification
The Universal Serial Bus specification is available from http://www.usb.org.
3.4
ARM Documentation on Cortex-M4 Core

ARM® Cortex®-M4 Devices Generic User Guide for revision r0p1

ARM Cortex-M4 Technical Reference Manual for revision r0p1
These documents are available at http://www.arm.com/ in the info center section.
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Revision History
Doc Rev.
Date
Comments
42155E
11/2015
Figure 1-1, Figure 1-2, and Figure 1-3 are updated.
Some typos corrected.
42155D
10/2014
Figure 1-1, Figure 1-2, and Figure 1-3 are updated
42155C
10/2013
Figure 1-1, Figure 1-2, and Figure 1-3 are updated
42155B
08/2013
Updated recommended decoupling/filtering capacitor for VDDIN in:
Table 1-1, Table 1-2, and Table 1-3.
42155A
07/2013
Initial document revision
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