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APPLICATION NOTE
AT06068: SAM4E Schematic Checklist
Atmel ATSAM4E
Introduction
A good hardware design comes from a proper schematic. Since SAM4E devices
have a fair number of pins and functions, the schematic for these devices can be
large and quite complex.
This application note describes a common checklist which should be used when
starting and reviewing the schematics for a SAM4E design.
Features
•
•
•
•
•
•
•
Power circuits
ADC connection
Clock and crystal oscillators
JTAG and SWD debug ports
USB connection
Boot Program constraints
Suggested reading
Atmel-42231C-SAM4E-Schematic-Checklist_Application-Note_AT06068_02/2015
Table of Contents
1. Schematic Checklist ........................................................................... 3
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
Single Power Supply Strategy ........................................................................... 3
Dual Power Supply Strategy ............................................................................. 5
Backup Unit Externally Supplied ....................................................................... 7
Clocks, Oscillator and PLL ................................................................................ 9
Serial Wire and JTAG ..................................................................................... 11
Flash Memory ................................................................................................. 12
Reset and Test Pins ........................................................................................ 12
PIOs ............................................................................................................. 12
Parallel Capture Mode .................................................................................... 12
Analog Front End ............................................................................................ 12
12-bit DAC ...................................................................................................... 13
USB Device (UDP) .......................................................................................... 13
Static Memory Controller (SMC) ..................................................................... 14
2. SAM4E Boot Program Constraints ................................................... 15
2.1
SAM-BA Boot .................................................................................................. 15
3. Suggested Reading.......................................................................... 16
3.1
3.2
3.3
3.4
Device Datasheet ............................................................................................ 16
Evaluation Kit User Guide ............................................................................... 16
USB Specification ........................................................................................... 16
ARM Documentation on Cortex-M4 Core ........................................................ 16
4. Revision History ............................................................................... 17
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1.
Schematic Checklist
1.1
Single Power Supply Strategy
Figure 1-1. Single Power Supply Schematic Example
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Table 1-1.
Single Power Supply Checklist
Signal name
Recommended pin connection
Description
VDDIN
1.62V to 3.6V
Decoupling/Filtering capacitors
(1)(2)
(10µF or higher ceramic capacitor)
Powers the voltage regulator, ADC, DAC, and Analog
comparator power supply.
VDDIO
Powers the peripheral I/Os, USB transceiver, Backup
part, 32kHz crystal oscillator, and oscillator pads.
Decoupling/Filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
1.62V to 3.6V
Decoupling/Filtering capacitors
(1)(2)
(100nF and 10μF)
Warning:
At power-up VDDIO needs to reach 0.6V
before VDDIN reaches 1.0V
Warning:
VDDIO voltage needs to be equal or
below to (VDDIN voltage +0.5V)
VDDOUT
Decoupling/filtering capacitor
(1)(2)
(100nF and 2.2μF)
1.2V output of the main voltage regulator.
Decoupling/Filtering capacitors must be added to
guarantee stability.
VDDCORE
1.08V to 1.32V
Must be connected directly to VDDOUT
pin.
Decoupling/filtering capacitor
(1)(2)
(100nF)
Power the Core, the embedded memories, and the
peripherals.
VDDPLL
1.08V to 1.32V
(1)(2)
Decoupling/filtering RLC circuit
Powers PLLA, PLLB, the Fast RC, and the 3 - 20MHz
oscillator.
Maximum voltage ripple is 10mV.
GND
Ground
Ground pins GND are common to VDDIO, VDDPLL, and
VDDCORE
Note:
Restrictions:
- For USB, VDDIO needs to be greater than 3.0V.
- For AFE, DAC VDDIN needs to be greater than 2.4V.
Note:
1.
These values are given only as a typical example.
2.
Capacitors should be placed as close as possible to each pin in the signal group, vias should be avoided.
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1.2
Dual Power Supply Strategy
Figure 1-2. Dual Power Supply Schematic Example
Main Supply
(1.62V – 3.6V)
VDDIO
100nF
10µF
Can be the same
supply
ADC, DAC, Analog
Comparator Supply
(2.0V – 3.6V)
VDDIN
100nF
USB
Transceivers
ADC, DAC,
Analog comparator
Voltage
Regulator
100nF
VDDOUT
2.2µF
VDDCORE Supply
(1.08V – 1.32V)
VDDCORE
100nF
10µF
10µH
100nF
VDDPLL
1R
4.7µF
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Table 1-2.
Dual Power Supply Checklist
Signal name
Recommended pin connection
Description
VDDIN
2.0V to 3.6V
Decoupling/Filtering capacitors
(1)(2)
(10µF or higher ceramic capacitor)
Powers the voltage regulator, ADC, DAC, and Analog
comparator power supply.
VDDIO
Notes:
Powers the peripheral I/Os, USB transceiver, Backup
part, 32kHz crystal oscillator, and oscillator pads.
Decoupling/Filtering capacitors must be added to
improve startup stability and reduce source voltage drop.
1.62V to 3.6V
Connected to main supply
Decoupling/Filtering capacitors
(1)(2)
(100nF and 10μF)
Warning:
At power-up VDDIO needs to reach
0.6V before VDDIN reaches 1.0V
Warning:
VDDIO voltage needs to be equal or
below to (VDDIN voltage +0.5V)
VDDOUT
Decoupling/filtering capacitor
(1)(2)
(10nF and 2.2μF)
1.2V output of the main voltage regulator.
Decoupling/Filtering capacitors must be added to
guarantee stability.
VDDCORE
1.08V to 1.32V
Connected to VDDCORE supply
Decoupling/filtering capacitors
(1)(2)
(100nF and 10µF)
Power the core, the embedded memories, and the
peripherals.
VDDPLL
1.08V to 1.32V
Connected to VDDCORE supply
(1)(2)
Decoupling/filtering RLC circuit
Powers PLLA, PLLB, the Fast RC, and the 3 - 20MHz
oscillator.
Maximum voltage ripple is 10mV.
GND
Ground
Ground pins GND are common to VDDIO, VDDPLL, and
VDDCORE.
Restrictions:
- For USB, the VDDIO needs to be greater than 3.0V.
- For AFE, the DAC VDDIN needs to be greater than 2.4V.
1.
These values are given only as a typical example.
2.
Capacitor should be placed as close as possible to each pin in the signal group, vias should be avoided.
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1.3
Backup Unit Externally Supplied
Figure 1-3. Backup Unit Externally Supplied Schematic Example
Note:
The two diodes provide a “switchover circuit” (for illustration purpose) between the backup battery and the main
supply when the system is put in backup mode.
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Table 1-3.
Backup Unit Externally Supplied Checklist
Signal name
Recommended pin connection
Description
VDDIN
1.62V to 3.6V
Decoupling/Filtering capacitors
(1)(2)
(10µF or higher ceramic capacitor)
Powers the voltage regulator
VDDIO
Notes:
Powers the peripheral I/Os, USB transceiver, Backup
part, 32kHz crystal oscillator, and oscillator pads.
Decoupling/Filtering capacitors must be added to
improve startup stability and reduce source voltage
drop.
1.62V to 3.6V
Decoupling/Filtering capacitors
(1)(2)
(100nF and 10μF)
Warning:
At power-up VDDIO needs to reach
0.6V before VDDIN reaches 1.0V
Warning:
VDDIO voltage needs to be equal or
below to (VDDIN voltage +0.5V)
VDDOUT
Decoupling/filtering capacitor
(1)(2)
(100nF and 2.2μF)
1.2V Output of the main voltage regulator.
Decoupling/Filtering capacitors must be added to
guarantee stability.
VDDCORE
1.08V to 1.32V
Connected to VDDOUT supply
Decoupling/filtering capacitor
(1)(2)
(100nF)
Power the Core, the embedded memories, and the
peripherals.
VDDPLL
1.08V to 1.32V
Connected to VDDOUT supply
(1)(2)
Decoupling/filtering RLC circuit
Powers PLLA, PLLB, the Fast RC, and the 3 - 20MHz
oscillator.
Maximum voltage ripple is 10mV.
GND
Ground
Ground pins GND are common to VDDIO, VDDPLL,
and VDDCORE.
Restrictions:
- For USB, the VDDIO needs to be greater than 3.0V.
- For AFE, the DAC VDDIN needs to be greater than 2.4V.
Notes:
1.
These values are given only as a typical example.
2.
Capacitor should be placed as close as possible to each pin in the signal group, vias should be avoided.
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1.4
Clocks, Oscillator and PLL
Table 1-4.
Clocks, Oscillator, and PLL Checklist
Signal name
Recommended pin connection
Description
Internal Equivalent Load Capacitance (CL):
CL = 9.5pF
Crystal Load Capacitance, ESR, Drive Level, and Shunt
Capacitance to validate.
CL
SAM4E
Crystals between 3 and 20MHz
PB9/XIN
PB8/XOUT
Main
Oscillator in
Normal Mode
XIN
XOUT
Capacitors on XIN and XOUT
(crystal load capacitance
dependant)
1kΩ resistor on XOUT only
required for crystals with
frequencies lower than 8MHz.
CLEXT
CCRYSTAL
CLEXT
The external load capacitance is calculated with the following
formula:
CLEXT=2*(Ccrystal-CL)
Refer to the Crystal Oscillators Design Consideration
Information section of the SAM4E Series Datasheet.
By default, at startup the chip runs out of the Master Clock
using the fast RC oscillator running at 4MHz.
PB9/XIN
PB8/XOUT
Main
Oscillator in
Bypass Mode
4/8/12MHz
Fast Internal
RC Oscillator
PB9/XIN: external clock source
PB8/XOUT: can be left
unconnected or used as GPIO.
1.62V to 3.6V Square wave signal (VDDIO)
External Clock Source up to 50MHz Duty Cycle: 40 to 60%
By default, at startup the chip runs out of the Master Clock
using the fast RC oscillator running at 4MHz.
PB9/XIN and PB8/XOUT: can be
left unconnected or used as GPIO
Powered up by VDDPLL
The output frequency is configurable through the PMC
registers.
The Fast RC oscillator is calibrated in production.
The frequency can be trimmed by software.
Duty Cycle: 40 to 60%
By default, at startup the chip runs out of the Master Clock
using the fast RC oscillator running at 4MHz.
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Signal name
Recommended pin connection
Description
Internal parasitic capacitance Cpara=0.7pF Crystal Load
Capacitance, ESR, Drive Level, and Shunt Capacitance to
validate.
SAM4E
XIN32
PA7/XIN32
PA8/XOUT32
32kHz Crystal
used
32.768kHz Crystal Capacitors on
XIN32 and XOUT32 (crystal load
capacitance dependent)
CLEXT
XOUT32
CCRYSTAL
CLEXT
CLEXTmax=20pF
CLEXT= 2x(Ccrystal-Cpara-Cpcb)
Refer to the Crystal Oscillators Design Consideration
Information section of the SAM4E Series Datasheet.
By default at start-up the chip runs out of the embedded
32kHz RC oscillator
PA7/XIN32
PA8/XOUT32
32kHz
Oscillator in
bypass mode
PA7/XIN32: external clock source
PA8/XOUT32: can be left
unconnected or use as GPIO.
1.62V to 3.6V Square wave signal (VDDIO)
External Clock Source up to 44kHz
Duty Cycle: 40 to 60%
By default at start-up the chip runs out of the embedded
32kHz RC oscillator
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1.5
Serial Wire and JTAG
Signal name
Recommended pin connection
Description
TCK/SWCLK/PB7
Application dependant.
If debug mode is not required this pin
can be use as GPIO.
Reset State:
- SWJ-DP Mode
- Internal pull-up disabled
- Schmitt Trigger enabled
TMS/SWDIO/PB6
Application dependant.
If debug mode is not required this pin
can be use as GPIO.
Reset state:
- SWJ-DP Mode
- Internal pull-up disabled
- Schmitt Trigger enabled
TDI/PB4
Application dependant.
If debug mode is not required this pin
can be use as GPIO.
Reset state:
- SWJ-DP Mode
- Internal pull-up disabled
- Schmitt Trigger enabled
TDO/TRACESWO/PB5
Application dependant.
If debug mode is not required this pin
can be use as GPIO.
Reset state:
- SWJ-DP Mode
- Internal pull-up disabled
- Schmitt Trigger enabled
JTAGSEL
Application dependant.
Must be tied to VDDIO to enter JTAG
Boundary Scan.
In harsh environments, It is strongly
recommended to tie this pin to GND.
Permanent Internal pull-down resistor
(15kΩ)
Figure 1-4. JTAG Schematic Example with 20-pin Connector
Figure 1-5. SWD Schematic Example with a 10-pin Connector
SWDIO
SWDCLK
TRACESWO
nRST
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1.6
Flash Memory
Signal name
ERASE/PB12
1.7
Recommended pin connection
Application dependant.
If hardware erase is not required this pin can
be use as GPIO.
NRST
TST
Recommended pin connection
Description
Application dependent.
Can be connected to a push button for
hardware reset.
TST pin can be left unconnected in normal
mode.
To enter in FFPI mode TST pin must be tied
to VDDIO.
In harsh environments, It is strongly
recommended to tie this pin to GND.
By default, the NRST pin is configured as an
input Permanent internal pull-up resistor to
VDDIO.
PAx – PBx - PCx
PDx - PEx
1.10
Permanent internal pull-down resistor (15kΩ).
PIOs
Signal name
1.9
Reset state: Erase Input, with a 100kΩ Internal
pull down and Schmitt trigger enabled
Reset and Test Pins
Signal name
1.8
Description
Internal pull-down resistor (100kΩ).
Must be tied to VDDIO to erase the General
Purpose NVM bits (GPNVMx), the whole Flash
content and the security bit.
Recommended pin connection
Application Dependant (Pulled-up on VDDIO)
Description
At reset, all PIOs are in I/O or System I/O mode
with Schmitt trigger inputs and internal pull-up
enabled.
To reduce power consumption, if not used, the
concerned PIO can be configured as an output
and driven at ‘0’ with internal pull-up disabled.
Parallel Capture Mode
Signal name
Recommended pin connection
Description
PIODC0-PIODC7
Application Dependant (Pulled-up on VDDIO)
Parallel Mode capture Data
PIODCCLK
Application Dependant (Pulled-up on VDDIO)
Parallel Mode capture Clock
PIODCEN1-2
Application Dependant (Pulled-up on VDDIO)
Parallel Mode capture mode enable
Analog Front End
Signal name
ADVREF
Recommended pin connection
Description
2.0V to VDDIN(*)
Decoupling capacitor(s).
ADVREF is a pure analog input.
ADVREF is the voltage reference for the ADC,
DAC and Analog comparator.
(*) 2.0V is used for 10-bit ADC resolution only. In
other case the minimum ADVREF value is 2.4V.
To reduce power consumption, if analog
features are not used, connect ADVREF to
GND.
Signal name
Recommended pin connection
Description
AD0-AD14
0 to ADVREF
ADC Channels
ADTRG
VDDIO
ADC External Trigger input
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1.11
1.12
12-bit DAC
Signal name
Recommended pin connection
Description
DAC0-DAC1
1/6* ADVREF to 5/6* ADVREF
-
DACTRG
VDDIO
DAC External Trigger input
USB Device (UDP)
Signal name
Recommended pin connection
Description
(4)
DDP/PB11
DDM/PB10
Application dependent .
If USB device support is not required this pin
can be use as GPIO.
Reset State:
- USB Mode
- Internal Pull-down
If UDP is not used, this pin can be left
unconnected.
(4)
Application dependent .
If USB device support is not required this pin
can be use as GPIO.
Reset State:
- USB Mode
- Internal Pull-down
If UDP is not used, this pin can be left
unconnected.
Note: 4. USB Device Typical connection:
PIO
5V Bus monitoring
27k
47k
DDM
DDP
REXT
1
2
REXT
3
Type B
connector
4
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1.13
Static Memory Controller (SMC)
Signal name
Recommended pin connection
Description
Data Bus (D0 to D15)
D0-D15
Application dependent
Note: Data bus lines are multiplexed with the PIOC
controller. Their I/O line reset state is input with pull-up
enabled.
Address Bus (A0 to A23)
A0-A23
Application dependent
NWAIT
Application dependent
Note: Data bus lines are multiplexed with the PIOA &
PIOC controllers. Their I/O line reset state is input with
pull-up enabled.
NWAIT pin is an active low input.
Note: NWAIT is multiplexed with PC13.
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2.
SAM4E Boot Program Constraints
See AT91SAM Boot Program section of the SAM4E Series Datasheet for more details on the boot program.
2.1
SAM-BA Boot
The SAM-BA® Boot Assistant supports serial communication via the UART or USB device port:
•
•
Note:
UART0 Hardware Requirements: none
USB Device Hardware Requirements: external crystal or External clock
11.289MHz / 12.000MHz / 16.000MHz / 18.432MHz
(1)
with frequency of:
1. Must be 2500ppm and 1.62V to 3.6V (VDDIO) Square Wave Signal.
Table 2-1.
Pins Driven During SAM-BA Boot Program Execution
Peripheral
Pin
PIO Line
UART0
UART0
URXD0
UTXD0
PA9
PA10
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3.
Suggested Reading
3.1
Device Datasheet
The device datasheet contains block diagrams of the peripherals and details about implementing firmware for the
device. It also contains the electrical specifications and expected characteristics of the device.
The datasheet is available on http://www.atmel.com/ in the datasheets section of the product page.
3.2
Evaluation Kit User Guide
The SAM4E-EK user guide contains schematics that can be used as a starting point when designing with the SAM4E
devices. This user guide is available on http://www.atmel.com/ in the documents section of the SAM4E-EK page.
3.3
USB Specification
The Universal Serial Bus specification is available from http://www.usb.org.
3.4
ARM Documentation on Cortex-M4 Core
•
•
Cortex®-M4 Devices Generic User Guide for revision r0p1
Cortex-M4 Technical Reference Manual for revision r0p1
These documents are available at http://www.arm.com/ in the info center section.
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4.
Revision History
Doc. Rev.
Date
Comments
42231C
02/2015
Updated power supply figures
42231B
10/2014
Updated power supply figures
42231A
12/2013
Initial document release
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