APPLICATION NOTE AT07215: SAM G53 Schematic Checklist ATSAM G53 Introduction A good hardware design comes from a proper schematic. Since SAM G53 devices have a fair number of pins and functions, the schematic for these devices can be large and quite complex. This application note describes a common checklist which should be used when building and reviewing the schematics of a SAM G53 application design. The document covers the following general aspect: Power supply strategies Clock and crystal oscillators JTAG and SWD debug ports Suggested reading Atmel-42310B-SAM-G53-Schematic-Checklist-ApplicationNote_042015 1 Schematic Checklist 1.1 Power Supply Strategy Single power supply strategy is mandatory on SAM G53. VDDCORE should always be connected to VDDOUT. Figure 1-1 shows the standard power supply. Figure 1-1. Power Supply Schematic Example Peripheral I/Os Memories F l a ADC s h Main supply (1.7V - 3.6V) VDDIO 4.7µF 100nF (1)(2) (1)(2)(3) Voltage Regulator 100nF (1)(2) 2.2µF VDDOUT (1)(2) 100nF VDDCORE Core (1)(2)(3) Memories (SRAM, FLASH) PLL Peripherals SAM G53 Notes: 2 1. 2. 3. These values are given only as a typical example. Capacitors should be placed as close as possible to each pin in the signal group, vias should be avoided. Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin. AT07215: SAM G53 Schematic Checklist [APPLICATION NOTE] 2 Atmel-42310B-SAM-G53-Schematic-Checklist-ApplicationNote_042015 Main supply 4.7µF 100nF VDDIO 100nF VDDIO 100nF VDDIO SAM G53 The following checklist (Table 1-1) must be followed in order to ensure correct hardware configuration for power supply. Table 1-1. Notes: 1.2 Single Power Supply Checklist Signal name Recommended pin connection Description VDDIO 1.7V to 3.6V Decoupling/Filtering capacitors (100nF and 4.7μF) (1)(2) Powers the peripheral I/Os, Flash memory (dual rail), ADC, 32kHz crystal oscillator and oscillator pads. Decoupling/Filtering capacitors must be added to improve startup stability and reduce source voltage drop. VDDOUT Decoupling/filtering capacitor (100nF and 2.2μF) (1)(2) 1.2V Output of the main voltage regulator. Decoupling/filtering capacitors must be added to guarantee stability. VDDCORE Must be connected directly to VDDOUT pin. Decoupling/filtering capacitor (100nF) (1)(2) Powers the Core, the embedded memories (SRAM, Flash), the PLL and integrated peripherals. GND Ground Ground pins GND are common to VDDIO and VDDCORE 1. 2. These values are given only as a typical example. Capacitors should be placed as close as possible to each pin in the signal group, vias should be avoided. Clocks and Oscillators Configuration There are three possible configurations for Main and 32kHz clocks: 1.2.1 Oscillator in Normal Mode Oscillator in Bypass Internal RC Oscillator Main Clock/Oscillators Figure 1-2 shows a standard main Crystal hardware implementation. AT07215: SAM G53 Schematic Checklist [APPLICATION NOTE] Atmel-42310B-SAM-G53-Schematic-Checklist-ApplicationNote_042015 3 3 Figure 1-2. Main Crystal Schematic Example CL SAM G53 XIN XOUT R = 1k if Crystal Frequency is lower than 8MHz CCRYSTAL CLEXT CLEXT The following checklist (Table 1-2) must be followed in order to ensure correct hardware configuration for main Clock/Oscillators. Table 1-2. Main Clock, Oscillators Checklist Signal name Recommended pin connection Description Internal Equivalent Load Capacitance (CL = 12.5pF to 17.5pF): Crystals between 3 and 20MHz Capacitors on XIN and XOUT (crystal load capacitance dependant) PB9/XIN PB8/XOUT Main Oscillator in Normal Mode 1kΩ resistor on XOUT only required for crystals with frequencies lower than 8MHz. PB9/XIN PB8/XOUT 1.2.2 The external load capacitance is calculated with the following formula: CLEXT=2 (Ccrystal-CL-CPCB) Refer to the Crystal Oscillators Design Consideration Information section of the SAM G5x Series Datasheet. By default, at startup the chip runs out of the Master Clock using the fast RC oscillator running at 8MHz. PB9/XIN: external clock source PB8/XOUT: can be left unconnected or used as GPIO. 1.7V to 3.6V Square wave signal (VDDIO) External Clock Source up to 50MHz Duty Cycle: 40 to 60% By default, at startup the chip runs out of the Master Clock using the fast RC oscillator running at 8MHz. PB9/XIN and PB8/XOUT: can be left unconnected or used as GPIO Powered up by VDDIO The output frequency is configurable through the PMC registers. The Fast RC oscillator is calibrated in production. The frequency can be trimmed by software. Duty Cycle: 40 to 60% By default, at startup the chip runs out of the Master Clock using the fast RC oscillator running at 8MHz. Main Oscillator in Bypass Mode 8/16/24MHz Fast Internal RC Oscillator Crystal Load Capacitance, ESR, Drive Level and Shunt Capacitance to validate. 32kHz Clock/Oscillators Figure 1-3 shows a standard 32kHz Crystal hardware implementation. 4 AT07215: SAM G53 Schematic Checklist [APPLICATION NOTE] 4 Atmel-42310B-SAM-G53-Schematic-Checklist-ApplicationNote_042015 Figure 1-3. 32kHz Crystal Schematic Example CL SAM G53 XIN32 XOUT32 32.768kHz CLEXT C LEXT The following checklist (Table 1-3) must be followed in order to ensure correct hardware configuration for 32kHz Clock/Oscillator. Table 1-3. 32kHz Clock, Oscillators Checklist Signal name PA7/XIN32 PA8/XOUT32 32kHz Crystal used PA7/XIN32 PA8/XOUT32 32kHz Oscillator in bypass mode 1.3 Recommended pin connection Description 32.768kHz Crystal Capacitors on XIN32 and XOUT32 (crystal load capacitance dependent) Internal parasitic capacitance Cpara=0.7pF Crystal Load Capacitance, ESR, Drive Level and Shunt Capacitance to validate. CLEXTmax=17pF CLEXT= 2x(Ccrystal-Cpara- Cpcb) Refer to the Crystal Oscillators Design Consideration Information section of the SAM G5x Series Datasheet. By default at start-up the chip runs out of the embedded 32kHz RC oscillator PA7/XIN32: external clock source PA8/XOUT32: can be left unconnected or use as GPIO. 1.7V to 3.6V Square wave signal (VDDIO) External Clock Source up to 44kHz Duty Cycle: 40 to 60% By default at start-up the chip runs out of the embedded 32kHz RC oscillator Serial Wire and JTAG Figure 1-4, Figure 1-5, Figure 1-6, and Figure 1-7 shows a standard JTAG/SWD hardware implementation with 10-pin Cortex®-M connector and 20-pin connector. It is recommended to establish accessibility to a JTAG/SWD connector for debug in any case. AT07215: SAM G53 Schematic Checklist [APPLICATION NOTE] Atmel-42310B-SAM-G53-Schematic-Checklist-ApplicationNote_042015 5 5 Figure 1-4. JTAG Schematic Example: 10-pin Cortex-M Connector VDDIO 100k 1 3 5 7 9 VTref GND GND NC NC SWDIO/TMS SWCLK/TCK SWO/TDO TDI nRESET 100k 100k 2 4 6 8 10 TMS TCK TDO TDI nRST 10-pin Cortex-M connector Figure 1-5. JTAG Schematic Example: JTAG 20-pin Connector VDDIO 100k 100k 100k 1 3 5 7 9 11 13 15 17 19 TDI TMS TCK TDO nRST VTref nTRST TDI TMS TCK RTCK TDO nSRST DBGRQ 5V-Target NC GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 2 4 6 8 10 12 14 16 18 20 JTAG 20-pin connector Figure 1-6. SWD Schematic Example: 10-pin Cortex-M Connector VDDIO 100k 1 3 5 7 9 VTref GND GND NC NC SWDIO/TMS SWCLK/TCK SWO/TDO TDI nRESET 100k 2 4 6 8 10 10-pin Cortex-M connector 6 AT07215: SAM G53 Schematic Checklist [APPLICATION NOTE] 6 Atmel-42310B-SAM-G53-Schematic-Checklist-ApplicationNote_042015 SWDIO SWCLK SWO nRST Figure 1-7. SWD Schematic Example: SWD 20-pin Connector VDDIO 100k 100k 1 3 5 7 9 11 13 15 17 19 SWDIO SWCLK TRACESWO nRST VTref Not Used Not Used SWDIO SWCLK Not Used SWO RESET Not Used 5V-Target NC GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 2 4 6 8 10 12 14 16 18 20 SWD 20-pin connector The following checklist (Table 1-4) must be followed in order to ensure correct hardware configuration for JTAG/SWD. Table 1-4. Serial Wire and JTAG Checklist Signal name Recommended pin connection Description TCK/SWCLK/PB7 Application dependant If debug mode is not required this pin can be use as GPIO Reset State: - SWJ-DP Mode - Internal pull-up disabled - Schmitt Trigger enabled TMS/SWDIO/PB6 Application dependant If debug mode is not required this pin can be use as GPIO Reset state: - SWJ-DP Mode - Internal pull-up disabled - Schmitt Trigger enabled TDI/PB4 Application dependant If debug mode is not required this pin can be use as GPIO Reset state: - SWJ-DP Mode - Internal pull-up disabled - Schmitt Trigger enabled TDO/TRACESWO/PB5 Application dependant If debug mode is not required this pin can be use as GPIO Reset state: - SWJ-DP Mode - Internal pull-up disabled - Schmitt Trigger enabled JTAGSEL Application dependant. Must be tied to VDDIO to enter JTAG Boundary Scan. In harsh environments, It is strongly recommended to tie this pin to GND. Permanent Internal pull-down resistor (15kΩ) AT07215: SAM G53 Schematic Checklist [APPLICATION NOTE] Atmel-42310B-SAM-G53-Schematic-Checklist-ApplicationNote_042015 7 7 1.4 Flash Memory Signal name ERASE/PB12 Recommended pin connection Application dependant. If hardware erase is not required this pin can be use as GPIO Description Internal pull-down resistor (100kΩ). Must be tied to VDDIO to erase the General Purpose NVM bits (GPNVMx), the whole Flash content and the security bit. Reset state: Erase Input, with a 100kΩ Internal pull down and Schmitt trigger enabled. Note: 1.5 The minimum erase pin assertion for erase effectiveness is 200ms. Reset and Test Pins Figure 1-8, shows a standard Reset hardware implementation. Figure 1-8. Reset Hardware Implementation VDDIO 100k 39 39 NRST 100nF GND SAM G53 8 Signal name Recommended pin connection Description NRST Application dependent. Can be connected to a push button for hardware reset. By default, the NRST pin is configured as an input Permanent internal pull-up resistor to VDDIO. TST TST pin can be left unconnected in normal mode. To enter in FFPI mode TST pin must be tied to VDDIO. In harsh environments, It is strongly recommended to tie this pin to GND. Permanent internal pull-down resistor (15kΩ). AT07215: SAM G53 Schematic Checklist [APPLICATION NOTE] 8 Atmel-42310B-SAM-G53-Schematic-Checklist-ApplicationNote_042015 1.6 PIOs Signal name PAx - PBx Recommended pin connection Application Dependant (Pulled-up on VDDIO) Description At reset, all PIOs are in IO or System IO mode with Schmitt trigger inputs and internal pull-up enabled. To reduce power consumption, if not used, the concerned PIO can be configured as an output and driven at ‘0’ with internal pull-up disabled. AT07215: SAM G53 Schematic Checklist [APPLICATION NOTE] Atmel-42310B-SAM-G53-Schematic-Checklist-ApplicationNote_042015 9 9 2 Suggested Reading 2.1 Device Datasheet The device datasheet contains block diagrams of the peripherals and details about implementing firmware for the device. It also contains the electrical specifications and expected characteristics of the device. The datasheet is available on http://www.atmel.com/ in the Datasheets section of the product page. 2.2 Xplained-Pro User Guide The SAM G53 Xplained PRO user guide contains schematics that can be used as a starting point when designing with the SAM G53 devices. This user guide is available on http://www.atmel.com/ in the documents section of the SAM G53 Xplained Pro. 2.3 ARM Documentation on Cortex-M4 Core Cortex-M4 Devices Generic User Guide for revision r0p1 Cortex-M4 Technical Reference Manual for revision r0p1 These documents are available at http://www.arm.com/ in the info center section. 10 AT07215: SAM G53 Schematic Checklist [APPLICATION NOTE] 1 Atmel-42310B-SAM-G53-Schematic-Checklist-ApplicationNote_042015 0 3 Revision History Doc Rev. Date Comments 42310B 04/2015 Changes to the electrical characteristics. 42310A 06/2014 Initial document release. AT07215: SAM G53 Schematic Checklist [APPLICATION NOTE] Atmel-42310B-SAM-G53-Schematic-Checklist-ApplicationNote_042015 11 1 1 Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 │ www.atmel.com © 2015 Atmel Corporation. / Rev.: Atmel-42310B-SAM-G53-Schematic-Checklist-ApplicationNote_042015. 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