PS-AT28C010 ® revision C MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 128K x 8-Bit PARALLEL EEPROM, MONOLITHIC SILICON Revision Written by Approved by Date C S.JAMES C. FERRE 03/01/08 1/24 PS-AT28C010 Rev C DOCUMENTATION CHANGE NOTICE Date of update Revision letter B C 28/03/07 03/01/08 modifications Update of table 1 with functional tests Add data retention test description 2/24 PS-AT28C010 Rev C 1 1.1 1.2 1.3 1.4 1.5 1.6 2 3 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.2 3.2.1 3.2.2 3.2.3 3.3 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.6 3.6.1 3.6.2 4 4.1 4.2 4.3 4.4 4.4.1 4.4.2 4.4.3 4.5 5 5.1 SUMMARY GENERAL ............................................................................................................................ 4 Scope ....................................................................................................................................................................... 4 Identification............................................................................................................................................................ 4 Absolute maximum ratings.................................................................................................................................... 4 Recommended operating conditions.................................................................................................................... 4 Radiation features................................................................................................................................................... 4 Handling precautions ............................................................................................................................................. 4 APPLICABLE DOCUMENTS ............................................................................................... 5 REQUIREMENTS ................................................................................................................. 5 Design, construction, and physical dimensions. ................................................................................................ 5 Package type. ........................................................................................................................................................... 5 Terminal connections................................................................................................................................................ 5 Block diagram. .......................................................................................................................................................... 5 Timing waveforms..................................................................................................................................................... 5 Marking .................................................................................................................................................................... 5 Lead Identification..................................................................................................................................................... 5 Component Number.................................................................................................................................................. 5 Traceability Information............................................................................................................................................. 6 Electrical characteristics........................................................................................................................................ 6 Burn-in test.............................................................................................................................................................. 6 Electrical circuit ......................................................................................................................................................... 6 Parameters drift value............................................................................................................................................... 6 Environmental and Endurance Tests.................................................................................................................... 6 Electrical Circuit for Operating Life Test ................................................................................................................... 6 Electrical Measurements at Completion of Environmental and endurance tests...................................................... 6 Conditions for Operating Life Test ............................................................................................................................ 6 Data Retention Screening......................................................................................................................................... 6 Total dose irradiation testing................................................................................................................................. 7 Bias Conditions ......................................................................................................................................................... 7 Electrical Measurements........................................................................................................................................... 7 QUALITY ASSURANCE PROVISIONS ............................................................................... 7 Wafer lot validation................................................................................................................................................. 7 Sampling and inspection. ...................................................................................................................................... 7 Screening................................................................................................................................................................. 7 Quality conformance inspection ........................................................................................................................... 7 Group A inspection. .................................................................................................................................................. 7 Group C inspection. .................................................................................................................................................. 7 Group D inspection. .................................................................................................................................................. 7 Delta measurements............................................................................................................................................... 8 PACKAGING ........................................................................................................................ 8 Packaging requirements ........................................................................................................................................ 8 FIGURES FIGURE 1. Case outline ........................................................................................................................................................................... 14 FIGURE 2. Terminal connections. ........................................................................................................................................................... 15 FIGURE 3. Block diagram and the truth table ......................................................................................................................................... 16 FIGURE 4. Timing waveforms. ................................................................................................................................................................ 18 FIGURE 6. Electrical circuit for total dose radiation test. ......................................................................................................................... 23 TABLES TABLE I. Electrical performance characteristics........................................................................................................................................ 9 TABLE 2. Parameter drift values .............................................................................................................................................................. 12 3/24 PS-AT28C010 Rev C 1 GENERAL 1.1 Scope This specification details the ratings, physical and electrical characteristics, tests and inspection data of the 128K x 8-Bit EEPROM named AT28C010. It also defines the specific requirement for space and military applications with high reliability. 1.2 Identification Part number AT28C010-12DK-MQ AT28C010-12DK-SV 1.3 Description Access Time 128K x 8-Bit 120 ns eeprom 128K x 8-Bit 120 ns eeprom Case Level Flat pack 435 mils 32 leads Flat pack 435 mils 32 leads Military Level B Space Level B Absolute maximum ratings Supply voltage range (VDD) ................................................ -0.6V to 6.25V Output voltage range (VOUT)............................................... -0.6V dc to VDD + 0.6V dc Power dissipation (Pd) ....................................................... 0,3W Storage temperature .......................................................... -65°C to 150°C Maximum junction temperature (TJ) ................................... 175°C Thermal resistance junction to case (Θjc) : ....................... 6°C/W Lead temperature (soldering @ 1/16 in, 10 s) ................... 300°C Endurance.......................................................................... 50,000 cycles/byte Data retention .................................................................... 10 years 1.4 Recommended operating conditions. Supply voltage range (VDD) ................................................ 4.5 V dc to 5.5 V dc Ambient operating temperature (TA) ……………………….. -55°C to 125°C Storage temperature .......................................................... 30°C, 20 to 65% RH, dust free, original packing 1.5 Radiation features Tested up to a Total Dose of (according to MIL STD 883 Method 1019) : (dose rate 0.1 rad/s).......................................................... 10 kRads (Si) Read Only Mode, when biased ........... 30 kRads (Si) Read Only Mode, when un-biased No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2 1.6 Handling precautions These components are susceptible to damage by electrostatic discharge. Therefore, suitable precautions shall be employed for protection during all phases of manufacturing, testing, shipment and any handling. ESD.................................................................................... 2000 V 4/24 PS-AT28C010 Rev C 2 APPLICABLE DOCUMENTS MIL-PRF-38535 ........................................Integrated Circuits, Manufacturing, General Specification for. MIL-STD-883 ...........................................Test Method Standard Microcircuits. ASTM Standard F1192-95 ........................Standard guide for the measurement of single event phenomena from heavy ion irradiation of semiconductor devices JEDEC Standard EIA/JESD78..................IC latch-up test ATMEL Aerospace Products Quality Flows In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. 3 REQUIREMENTS 3.1 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein. 3.1.1 Package type. The package shall be a flat pack 435 mils, 32 leads (figure1). The case shall be hermetically sealed and have a ceramic body. The leads shall be brazed. 3.1.2 Terminal connections. The terminal connections shall be as specified on figure 2 . 3.1.3 Block diagram. The block diagram and the truth table shall be as specified on figure 3 . 3.1.4 Timing waveforms. The timing waveforms shall be as specified on figure 4 . 3.2 Marking Each component shall be marked in respect of: (a) Lead Identification (b) Component Number (c) Traceability Information (d) Manufacturer’s Component Number 3.2.1 Lead Identification An index shall be located at the top of the package in the position defined in Figure 1. 3.2.2 Component Number Each component shall bear the component number which shall be constituted and marked as follows : AT28C010-12DK-XX Product identification Speed (12 = 120 ns) Package (DK = flat pack 32) Level (MQ=Military Level B – SV=Space Level B) 5/24 PS-AT28C010 Rev C 3.2.3 Traceability Information Each component shall be marked in respect of traceability information : lot number and date code. 3.3 Electrical characteristics The parameters to be measured with respect of electrical characteristics are scheduled in Table 1. The measurements shall be performed at Tamb=22 ± 3°C, Thigh=125 (+0/-5)°C and Tlow = -55 (+5/-0)°C respectively. 3.4 3.4.1 Burn-in test Electrical circuit Circuit for use in performing the power burn-in is shown in figure 5, in accordance with the intent specified in test method 1015 of MIL-STD-883. 3.4.2 Parameters drift value For space level, the parameter drift values applicable to burn-in are specified in Table 2 of this specification. Unless otherwise stated, measurements shall be performed at + 22 + 3 ° C. The parameter drift values (Δ), applicable to the parameters scheduled, shall not be exceeded. In addition to these drift value requirements, the appropriate limit value specified for a given parameter in Table 1 shall not be exceeded. . 3.5 3.5.1 Environmental and Endurance Tests Electrical Circuit for Operating Life Test The circuit for operating life testing shall be as specified for power burn in (figure 5). 3.5.2 Electrical Measurements at Completion of Environmental and endurance tests The parameters to be measured are scheduled in Table 1. Unless otherwise stated, the measurements shall be performed at tamb = 22+3°C. 3.5.3 Conditions for Operating Life Test The conditions for operating life testing shall be as specified for power burn in. 3.5.4 Data Retention Screening An electrical screening is performed during probe in order to guarantee data retention. The Device Under Test is filled with a checker board, then, is configured in margin mode test which allows a linear search of the high or low voltage threshold (high = “1” and low = “0” in the memory cell). The high (or low) recorded threshold voltage represents the fist fail occurring in all the cells. It must be higher than the reference voltage applied on all control gates during normal read operation. To guarantee the reliability of the read operation, a voltage guard band is applied between the reference voltage and the high (or low) threshold voltage. In a second time, the Device under test performed a bake operation (250 °C / 24 H / without power supply), and is retested with the following flow: • Read operation in order to check the integrity of the memory. • Performed a new linear search of the voltage threshold with checking if the valued measure is still higher than the reference voltage, and also, if the drift of the measure before and after the bake do not exceed 0.2V. If one of these two condition is not respected the data retention is failed. 6/24 PS-AT28C010 Rev C 3.6 3.6.1 Total dose irradiation testing Bias Conditions Continuous bias shall be applied during irradiation testing as shown in Figure 6 of this specification. 3.6.2 Electrical Measurements The parameters to be measured prior to, during and on completion of irradiation texture are scheduled in Table 1 of this specification. 4 QUALITY ASSURANCE PROVISIONS 4.1 Wafer lot validation Compliant with ATMEL Quality Management System. For space level, Wafer Lot is accepted by a SEM performed according to PAQC0016 (PAQC0016 referred to MIL-Std-883 method 2018 and 21400 ESCC specification). 4.2 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535. 4.3 Screening. Screening equivalent to MIL-PRF-38535. Screening shall be conducted on all devices prior to qualification and technology conformance inspection • The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in accordance with MIL-PRF-38535. • Additional screening for space application devices shall be as specified in MIL-PRF-38535, appendix B. 4.4 Quality conformance inspection Qualification inspection for high reliability and space level devices shall be in accordance with MIL-PRF38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections. 4.4.1 Group A inspection. • Tests shall be as specified in table 1 herein. • Subgroups 5 and 6 of table I of method 5005 of MIL STD 883 shall be omitted. • Subgroups 7 and 8 of table I of method 5005 of MIL STD 883 shall include verifying the functionality of the device. • O/V (latch up) tests shall be measured only for the initial qualification and after any process or design changes which may affect the performance of the device. • Capacitance measurement shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is five devices with no failure, and all input and output terminals tested. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table 1 herein. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table 1 herein. 7/24 PS-AT28C010 Rev C 4.5 Delta measurements Delta measurements, as specified in table 2, shall be made and recorded before and after the required burn-in screens to determine delta compliance. The electrical parameters to be measured, with associated delta limits are listed in table 2. The device manufacturer may, at his option, either perform delta measurements or within 24 hours after life test perform final electrical parameter tests, subgroups 1, 7 and 9. 5 PACKAGING 5.1 Packaging requirements The requirements for packaging shall be in accordance with MIL-PRF-38535. 8/24 PS-AT28C010 Rev C TABLE I. Electrical performance characteristics. Test Functionnal test 1 Functionnal test 2 Functionnal test 3 Functionnal test 4 High level input current Low level input current High impedance output leakage current state, low level High impedance output leakage current state, high level Input Low voltage Input Low voltage High level output voltage TTL Symbol - Test method Mil-Std883 3014 - 3014 - 3014 - 3014 IIH 3010 IIL 3010 Limits Unit Min Max - - - - - - - - - - - - 10 - μA μA -10 VIN (CE)= 0V IOZL - VIN (WE, OE ) = 5V VCC = 5.5V VOUT = 0V -10 - μA - 10 μA 0.8 V VIN (CE)= 0V IOZH - VIN (WE, OE ) = 5V VCC = 5.5V VOUT = 5.5V VIL VIH VOH1 3007 VOH2 3007 VOL 3007 Dynamic Operating current ICCOP 3005 Supply current Stand-by mode TTL ICCSB1 3005 Supply current Standby mode CMOS ICCSB2 3005 Input capacitance CIN 3012 Output capacitance COUT 3012 High level output voltage CMOS Low level output voltage Conditions -55°C ≤ TC ≤ +125°C +4.5 V ≤ VDD ≤ +5.5 V unless otherwise specified Verify truth table Note 1 Verify truth table Note 1 Verify truth table Note 1 Verify truth table Note 1 VCC= 5.5V, VIN (under test) = 5.5V (VIN remaining inputs = 0V) VCC= 5.5V, VIN (under test) = 0V (VIN remaining inputs = 5.5V) VCC =4,5 V, IOH = -400 µA Note 2 VCC =4,5 V, IOH = -100 µA Note 2 VCC =4.5 V, IOL = 2.1 mA Note 3 F = 1/TAVAV IOUT = 0 mA VCC = 5.5V 2.0 V 2.4 V 4.2 V 0.45 V 50 mA VCC = 5.5V CS ≥ VIH 10 mA VCC = 5.5V CS ≥ VCC-0.3 10 mA 10 pF 12 pF WE = OE =VIH VIN = 0 V TC = 25°C fIN = 1.0 MHz Note 4 VOUT = 0 V TC = 25°C fIN = 1.0 MHz Note 4 9/24 PS-AT28C010 Rev C 10/24 PS-AT28C010 Rev C Test Symbol Test method Mil-Std883 Conditions -55°C ≤ TC ≤ +125°C +4.5 V ≤ VDD ≤ +5.5 V unless otherwise specified VCC = 4.5 & 5.5V Notes 6,5 VCC = 4.5 & 5.5V Notes 6,5 VCC = 4.5 & 5.5V Notes 6,5 VCC = 4.5 & 5.5V Notes 6,5 Limits Min Unit Max Read cycle time TAVAV 3003 Address access time TAVQV 3003 CE access time TELQV 3003 OE access time TOLQV 3003 OE or CE disable to output in high Z TEHQZ TOHQZ 3003 VCC = 4.5 & 5.5 V Notes 7,8 3003 Note 6 0 3003 VCC = 5.5 V Notes 6,9 0 ns 3003 Notes 6,9 50 ns 0 ns 0 ns Output hold from address change Address setup time Address hold time CE setup time CE hold time Write pulse width ( WE or CE ) Data setup time Data hold time Write cycle time ( WE or CE ) Byte load cycle Write pulse width High OE , CE setup time (chip erase) WE pulse width (chip erase) OE , CE hold time (chip erase) Data hold time ( Data Polling) OE hold time ( Data Polling) Write Recovery Time TOHQX TAXQX TEHQX TAVWL TAVEL TWLAX TELAX TELWL TWLEL TWHEH TEHWH TWLWH TELEH TDVWH TDVEH TWHDX TEHDX TWHWL1 TEHEL1 TWHWL2 3003 3003 VCC = 4.5 & 5.5V Note 6 VCC = 4.5 & 5.5V Note,6 120 ns 120 ns 120 ns 50 ns 50 ns ns 3003 VCC = 4.5 V Notes 6, 9 100 ns 3003 VCC = 4.5 V Notes 6,9 50 ns 3003 Note 6 0 ns 3003 Note 6 10 ms 3003 Note 4 VCC = 4.5 & 5.5V Note 6 VCC = 4.5V Note 6 150 µs TWPH 3003 TELWL2 TOHWL2 3003 TWLWH2 3003 TWHEH2 TWHOL2 3003 TWHDX 3003 TWHOL 3003 TWR 3003 VCC = 4.5V Note 6 VCC = 4.5V Note 6 Note 4 Note 4 50 ns 5 ms 10 ms 10 ms 10 ns 10 ns 0 ns Note 4 ( Data Polling) 11/24 PS-AT28C010 Rev C Test Data hold time (Toggle Bit) OE hold time (Toggle Bit) OE High Pulse (Toggle Bit) Write Recovery Time (Toggle Bit) Symbol Conditions -55°C ≤ TC ≤ +125°C +4.5 V ≤ VDD ≤ +5.5 V unless otherwise specified Test method Mil-Std883 TWHDX 3003 TWHOL 3003 TOEHP 3003 TWR 3003 Limits Min Note 4 Note 4 Note 4 Unit Max 10 ns 10 ns 150 ns 0 ns Note 4 Notes 1/ Functional go-no-go test with the following test sequence: FUNCTIONAL TEST 1 Pattern Zeros Ones Checkerboard Inverse Checkerboard Timing (ns) (a) VCC (V) VSS (V) VIL (V) VIH (V) IOL (mA) IOH (mA) 300 300 300 300 4.5 and 5.5V 4.5 and 5.5V 4.5 and 5.5V 4.5 and 5.5V 0 0 0 0 0 0 0 0 2 2 2 2 0.5 0.5 0.5 0.5 -0.5 -0.5 -0.5 -0.5 Timing (ns) (a) VCC (V) VSS (V) VIL (V) VIH (V) IOL (mA) IOH (mA) 300 300 300 300 5.5 4.5 5.5 4.5 0 0 0 0 -0.3 -0.3 0 0.8 6 6 2 3 0.5 0.5 0.5 0.5 -0.5 -0.5 -0.5 -0.5 Timing (ns) (a) VCC (V) VSS (V) VIL (V) VIH (V) IOL (mA) IOH (mA) 300 4.5 0 0 3 2.1 -0.4 Timing (ns) (a) VCC (V) VSS (V) VIL (V) VIH (V) IOL (mA) IOH (mA) 240 240 240 240 4.5 and 5.5V 4.5 and 5.5V 4.5 and 5.5V 4.5 and 5.5V 0 0 0 0 0 0 0 0 3 3 3 3 1.2 1.2 1.2 1.2 -3.0 -3.0 -3.0 -3.0 Vout comp (V) 1.5 1.5 1.5 1.5 FUNCTIONAL TEST 2 Pattern Checkerboard Inverse Checkerboard Checkerboard Inverse Checkerboard Vout comp (V) 1.5 1.5 (b) (b) FUNCTIONAL TEST 3 Pattern Checkerboard Vout comp (V) (b) FUNCTIONAL TEST 4 Pattern Zeros Ones Checkerboard Inverse Checkerboard Vout comp (V) 1.5 1.5 1.5 1.5 (a) : write cycle is followed by a read cycle. (b) : 0.45V for low output level, 2.4V for high output level 12/24 PS-AT28C010 Rev C 2/ select address inputs to produce a low level at the pin under test. 3/ select address inputs to produce a high level at the pin under test. 4/ guaranteed but not tested 5/ Parameter measured during functional test 4 using pattern Checker board at 4.5V and 5.5V. 6/ Parameter tested go-no-go during functional test 4. 7/ TEHQZ is specified from OE or CE whichever occurs first (CL = 5 pF). 8/ Guaranteed with output loading 5pF but not tested. Characterized at initial design and after major process changes. 9/ Parameter measured during functional test 4 using pattern Checker board in Vcc worst case. 13/24 PS-AT28C010 Rev C TABLE 2. Parameter drift values Test High level output voltage High level output voltage Low level output voltage Low level Input current High level Input current Output leakage Low current Output leakage High current Supply current Standby mode TTL Supply current Standby mode CMOS Symb ol Test method Mil-Std-883 VOH1 As per table 1 VOH2 As per table 1 VOL As per table 1 IIL As per table 1 IIH As per table 1 IOZL As per table 1 IOZH As per table 1 ICCSB1 As per table 1 ICCSB2 As per table 1 Conditions As per table 1 As per table 1 As per table 1 As per table 1 As per table 1 As per table 1 As per table 1 Drift limits Unit 0.1 V 0.1 V 0.1 V 1 μA 1 μA 1 μA 1 μA 1 mA 1 mA As per table 1 As per table 1 Note: the above parameter shall be recorded before and after burn-in to determine the delta. 14/24 PS-AT28C010 Rev C FIGURE 1. Case outline Mm Min inch Max Min Max A 1.78 2.72 0.070 0.107 b 0.38 0.48 0.015 0.019 c 0.076 0.18 0.003 0.007 D 20.62 21.03 0.812 0.828 E 10.92 11.18 0.430 0.440 E2 8.46 80.82 0.333 0.347 K 0.20 0.39 0.008 0.015 K1 0.63 BSC 0.025 BSC e 1.27 BSC 0.050 BSC L 6.65 8.20 0.262 0.323 Q 0.66 0.91 0.026 0.036 S --- 1.14 --- 0.045 N 32 15/24 PS-AT28C010 Rev C FIGURE 2. Terminal connections. Case outline X Pin Number Name Pin Number Name 1 A16 17 I/O3 2 A15 18 I/O4 3 A12 19 I/O5 4 A7 20 I/O6 5 A6 21 I/O7 6 NC 22 CE 7 A5 23 A10 8 A4 24 OE 9 A3 25 A11 10 A2 26 A9 11 A1 27 A8 12 A0 28 A13 13 I/O0 29 A14 14 I/O1 30 WE 15 I/O2 31 NC 16 GND 32 VCC Name A0 - A16 CE Description addresses Chip enable OE Output enable WE Write enable Data inputs/Outputs Not connected Power Ground I/O0 – I/O7 NC VCC GND 16/24 PS-AT28C010 Rev C FIGURE 3. Block diagram and the truth table The truth table is as follow: WE OE Inputs/Outputs H X X Z L H L Data out Read L L H Data in Write X H X Z or Data out Write inhibit X X L Z or Data out Write inhibit L L L No operation Write inhibit CE Mode Stand-by/ Write Inhibit Note: L=low, H=high, X=low or high, Z=high impedance 17/24 PS-AT28C010 Rev C AC Characteristics: Temperature Range: …………………………………………………… -55 +125°C Supply Voltage: …………………………………………………………. 5.0 ± 0.5 V Input Pulse Levels……………………………………………………….. GND to 3.0 V Input Timing reference levels…………………………………………. 1.5V Output level detection …………………………………………….…… 1.5 ± 0.05V . General Specific (Tehqz, Tohqz) 18/24 PS-AT28C010 Rev C FIGURE 4. Timing waveforms. 4(a). Read mode (1), (2) TAVAV TELQV TOLQV TAVQV TEHQZ TAXQX Note: (1) CE may be delayed up to TAVQV - TELQV after the address transition without impact on TAVQV. (2) OE may be delayed up to TELQV - TOLQV after the falling edge of CE without impact on TELQV or by TAVQV - TOLQV after an address change without impact in TAVQV. 19/24 PS-AT28C010 Rev C 4(b). WE controlled byte write mode TOHWL TAVWL TWHOL TWLAX TWHEH TELWL TWPH TWLWH1 TDVWH 4(c). CE controlled byte write mode TOHEL TAVEL TWHDX TEHOL TELAX TEHWH TWLEL TWPH TELEH TDVEH TEHDX 20/24 PS-AT28C010 Rev C 4(d). Page write mode (1), (2) Notes: (1) Addresses A7 through A16 must specify the page address during each high to low transition of WE (or CE ) (2) OE must be high only when WE and CE are both low 4(e). Chip Erase mode 21/24 PS-AT28C010 Rev C 4(f). Data Polling Mode (1) Note: (1) Parameters guaranteed but not tested in this case 4(g). Toggle Bit Mode (1), (2), (3), (4) (16) (4) Notes (1) (2) (3) (4) Parameters guaranteed but not tested in this mode Toggling either OE or CE or both OE and CE will operate toggle bit Beginning and ending state of I/O6 will vary Any address location may be used but the address should not vary 22/24 PS-AT28C010 Rev C FIGURE 5. Electrical circuit for power burn-in and operating life test S16 1 32 VCC S15 2 31 NC S12 3 30 VCC S7 4 29 S14 S6 5 28 S13 NC 6 27 S8 S5 7 26 S9 S4 8 AT28C010 25 S3 9 24 GND S2 10 23 S10 S1 11 22 GND S0 12 21 VCC VCC 13 20 VCC VCC 14 19 VCC VCC 15 18 VCC GND 16 17 VCC Characteristics S11 Symbol Conditions Unit Ambient Temperature Tamb 125 (+0/-5) °C Address inputs Vin S0 to S16 (note 1) Vac Select pins CS 0 V Control inputs WE VCC V Control inputs OE 0 V Pulse frequency F0 1.65 +/- 20% MHz Positive Supply Voltage VCC 5.7V (+0.1 /-0.1) V Negative Supply Voltage GND 0 V Notes: (1) S0 TO S16 are droved signals with the following frequency : S0 frequency = F0 SN frequency = 1 Fn = .Fn −1 for n>=1 2 Resistors = 1 KΩ 23/24 PS-AT28C010 Rev C FIGURE 6. Electrical circuit for total dose radiation test. 5V ± 0.1 V 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 AT28C010 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 Input protection resistors = 512 ohm 24/24