PYX28C64 8K x 8 EEPROM FEATURES Access Times of 200, 250, 300 and 350 ns Software Data Protection Single 5V±10% Power Supply Fully TTL Compatible Inputs and Outputs Simple Byte and Page Write Endurance: 10,000 or 100,000 Cycles Low Power CMOS: - 60 mA Active Current - 200 µA Standby Current Data Retention: 100 Years Available in the following Packages: – 32-Pin Ceramic LCC (450 x 550 mils) – 28-Pin 600 mil Ceramic DIP Fast Write Cycle Times DESCRIPTION PIN CONFIGURATIONS The PYX28C64 is a 5 Volt 8Kx8 EEPROM using floating gate CMOS Technology. The device supports 64-byte page write operation. The PYX28C64 features DATA and Toggle Bit Polling as well as a system software scheme used to indicate early completion of a Write Cycle. The device also includes user-optional software data protection. Endurance is 10,000 or 100,000 Cycles and Data Retention is 100 Years. The device is available in a 32-Pin LCC package as well as a 28-Pin 600 mil wide Ceramic DIP. DIP (C5-1) FUNCTIONAL BLOCK DIAGRAM 1519B LCC (L6) Document # EEPROM101 REV B Revised July 2007 1 PYX28C64 MAXIMUM RATINGS(1) Symbol Parameter Value Unit V CC Power Supply Pin with Respect to GND –0.3 to +6.25 V V TERM Terminal Voltage with Respect to GND (up to 6.25V) –0.5 to +6.25 V TA Operating Temperature –55 to +125 °C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Military Ambient Temperature GND V CC –55°C to +125°C 0V 5.0V ± 10% Symbol Parameter Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol Parameter Conditions Typ. Unit CIN Input Capacitance COUT Output Capacitance VIN = 0V 10 pF VOUT = 0V 10 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol VIH Parameter Test Conditions Input High Voltage P5C164 Unit Min Max 2.0 VCC +0.3 V 0.8 V VCC +0.5 V 0.2 V 0.4 V –0.5 (3) VIL Input Low Voltage V HC VLC CMOS Input High Voltage VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min. VOH Output High Voltage (TTL Load) IOH = –4 mA, VCC = Min. 2.4 ILI Input Leakage Current VCC = Max. –10 +10 µA ILO Output Leakage Current VCC = Max., CE = VIH, –10 +10 µA ISB Standby Power Supply Current (TTL Input Levels) CE ≥ VIH, OE = VIL, VCC= Max, f = Max., Outputs Open ___ 3 mA ISB1 Standby Power Supply Current (CMOS Input Levels) CE ≥ VHC, VCC= Max, f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC ___ 250 µA Supply Current CE = OE = VIL, WE = VIH, All I/O's = Open, Inputs = VCC = 5.5V ICC VCC –0.2 –0.5 CMOS Input Low Voltage V VIN = GND to VCC VOUT = GND to VCC Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. Document # EEPROM101 REV B (3) ___ 60 mA 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Page 2 of 11 PYX28C64 AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter -200 Min Max -250 Min Max -300 Min Max -350 Unit Min Max 200 250 300 350 tAVAV Read Cycle Time tAVQV Address Access Time 200 250 300 350 ns tELQV Chip Enable Access Time 200 250 300 350 ns tOLQV Output Enable Access Time 100 100 100 100 ns tELQX Chip Enable to Output in Low Z tEHQZ Chip Disable to Output in High Z tOLQX Output Enable to Output in Low Z tOHQZ Output Disable to Output in High Z tAVQX Output Hold from Address Change tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 10 10 80 10 10 80 10 80 0 10 80 10 80 0 ns ns 80 10 80 0 ns ns 80 0 ns ns 250 250 250 250 ns 50 50 50 50 ns TIMING WAVEFORM OF READ CYCLE Document # EEPROM101 REV B Page 3 of 11 PYX28C64 AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol tWHWL1 tEHEL1 tAVEL tAVWL tELAX tWLAX tWLEL tELWL tWHEH tOHEL tOHWL tWHOL tELEH tWLWH tDVEH tDVWH tEHDX tWHDX tEHEL2 tWHWL2 tELWL Parameter -200 Min Max Write Cycle Time -250 Min Max 10 -300 Min Max 10 -350 Unit Min Max 10 10 ms Address Setup Time 20 20 20 20 ns Address Hold Time 150 150 150 150 ns Write Setup Time 0 0 0 0 ns Write Hold Time 0 0 0 0 ns OE Setup Time 20 20 20 20 ns OE Hold Time 20 20 20 20 ns WE Pulse Width 150 150 150 150 ns Data Setup Time 50 50 50 50 ns Data Hold Time 10 10 10 10 ns Byte Load Cycle Time 0.2 CE Setup Time tOVHWL Output Setup Time 2 0.2 2 0.2 2 0.2 2 µs 1 1 1 1 µs 1 1 1 1 µs tEHWH CE Hold Time 1 1 1 1 µs tWHOH OE Hold Time 1 1 1 1 µs tOHAV Erase Time 200 200 200 200 ms 150 150 150 150 ns tWLWH2 Chip Erase Time VH High Voltage for Chip Clear Document # EEPROM101 REV B 12 13 12 13 12 13 12 13 V Page 4 of 11 PYX28C64 CE CONTROLLED) TIMING WAVEFORM OF BYTE WRITE CYCLE (CE WE CONTROLLED) TIMING WAVEFORM OF BYTE WRITE CYCLE (WE Document # EEPROM101 REV B Page 5 of 11 PYX28C64 TIMING WAVEFORM OF PAGE WRITE CYCLE TIMING WAVEFORM OF CHIP CLEAR CYCLE Document # EEPROM101 REV B Page 6 of 11 PYX28C64 WRITE SEQUENCE FOR SOFTWARE DATA PROTECTION Document # EEPROM101 REV B SOFTWARE SEQUENCE TO DE-ACTIVATE SOFTWARE DATA PROTECTION Page 7 of 11 PYX28C64 AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE GND to 3.0V Input Rise and Fall Times 10ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Fig. 1 Mode CE OE WE I/O Read VIL VIL VIH DOUT Chip clear VIL VH VIL X Byte write VIL VIH VIL DIN Write inhibit X VIL X High Z/DOUT Write inhibit X X VIH High Z/DOUT VIH X X Standby High Z FIGURE 1. OUTPUT LOAD Document # EEPROM101 REV B Page 8 of 11 PYX28C64 ORDERING INFORMATION ENDURANCE DEVICE MINIMUM ENDURANCE PYX28C64 10,000 cycles (Standard) PYX28C64X 100,000 cycles (High Endurance) Document # EEPROM101 REV B Page 9 of 11 PYX28C64 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE C5-1 SIDE BRAZED DUAL IN-LINE PACKAGE (600 mils) 28 (600 mil) Min Max 0.232 0.014 0.026 0.045 0.065 0.008 0.018 1.490 0.500 0.610 0.600 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - L6 RECTANGULAR LEADLESS CHIP CARRIER 32 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.442 0.458 0.300 BSC 0.150 BSC 0.458 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 7 9 Document # EEPROM101 REV B Page 10 of 11 PYX28C64 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: EEPROM101 PYX28C64 8K x 8 EEPROM REV. ISSUE DATE ORIG. OF CHANGE OR Jul-06 JDB New Data Sheet A May-07 JDB Renamed device from P5C164 to P6C28C64 B Jul-07 JDB Renamed device from P6C28C64 to PYX28C64 Document # EEPROM101 REV B DESCRIPTION OF CHANGE Page 11 of 11