REVISIONS LTR DESCRIPTION A DATE (YR-MO-DA) APPROVED 13-02-11 Thomas M. Hess Add case outline Z. Correct the maximum iccsba value in table I. Update boilerplate in according with MIL-PRF-38535 requirement. - phn REV SHEET REV A A A SHEET 15 16 17 REV STATUS REV A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil Phu H. Nguyen STANDARD MICROCIRCUIT DRAWING 14 CHECKED BY Phu H. Nguyen APPROVED BY THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE 10-01-12 DRAWING APPROVAL DATE Thomas M. Hess AMSC N/A REVISION LEVEL A DSCC FORM 2233 APR 97 MICROCIRCUIT, DIGITAL, ASIC, CMOS GATE ARRAY BASED ON SPACEWIRE REMOTE TERMINAL CONTROLLER, MONOLITHIC SILICON SIZE CAGE CODE A 67268 SHEET 1 OF 5962-10A03 17 5962-E266-13 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 10A03 Federal stock class designator \ RHA designator (see 1.2.1) 01 Q X B Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 01 Circuit function AT7913E SpaceWire Remote Terminal Controller 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter X Y Z Descriptive designator See figure 1 See figure 1 See figure 1 Terminals Package style 349 349 352 Column Grid Array and interposer SCI Column Grid Array Quad flatpack with non conductive tie bar 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 2 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range for core (VCC1) .................................................... Supply voltage range for I/O’s (VCC2) .................................................... Power dissipation (Pd) .......................................................................... Storage temperature range................................................................... Maximum junction temperature (TJ) ...................................................... Thermal resistance junction to case (Rjc): Case X ........................................................................................... Case Y ........................................................................................... Case Z .......................................................................................... Operating free-air temperature range (TA) ............................................ -0.3 V to 2.0 V dc -0.3V to 4.0 V dc 2W -65°C to 150°C 175°C 2°C/W 1 °C/W 2°C/W -55°C to +125°C 1.4 Recommended operating conditions. Supply voltage range for core (VCC1) .................................................... Supply voltage range for I/O’s (VCC2) .................................................... Ambient operating temperature (TA) .................................................... Storage temperature ............................................................................. 1.65 V to 1.95 V dc 3.0 V to 3.6 V dc -55°C to 125°C 30°C, 20 to 65% RH, dust free, original packing 1.5 Radiation features. Maximum total dose available (dose rate = 0.1 rads(Si)/s) ..................................... 100 krads(Si) 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or www.dodssp.daps.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. ________ 1/ 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. All voltage referenced to ground unless otherwise specified STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 3 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block or logic diagram(s). The block or logic diagram(s) shall be as specified on figure 3. 3.2.4 Timing waveforms. The timing waveforms shall be as specified on figure 4. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55°C ≤ TC ≤ +125°C 1.65 V ≤ VCC1 ≤1.95 V 3.0 V ≤ VCC2 ≤3.6 V unless otherwise specified Group A subgroups Limits Min Unit Max Low level input voltage VIL CMOS 1,2,3 High level input voltage VIH CMOS 1,2,3 2.0 V Low level input current 0.8 V IIL VIN = GND, VCC2 = 3.3 V 1,2,3 -1 µA Low level input current Pull-down IILPD VIN = GND, VCC2 = 3.3 V 1,2,3 -5 µA Low level input current Pull-up IILPU -400 VIN = GND, VCC2 = 3.3 V 1,2,3 IIH VIN = VCC2 = 3.3 V 1,2,3 High level input current Pull-up IIHPU VIN = VCC2 = 3.3 V High level input current Pull-down IIHPD VIN = VCC2 = 3.3 V Output leakage low current IOZL Outputs disabled VOUT=GND 1,2,3 Output leakage high current IOZH Outputs disabled VOUT=VCC2 1,2,3 1 µA Low level output voltage VOL VCC2 = 3.0 V IOL= 2,4,8,12,16 mA 1,2,3 0.4 V high level output voltage VOH VCC2 = 3.0 V IOH = -2,-4,-8,-12,-16 mA 1,2,3 High level input current µA 1 µA 1,2,3 5 µA 1,2,3 600 µA -1 µA VCC2-0.4 V Supply current for array when not clocked ICCSBA VCC2 = 3.6 V VCC1 = 1.95 V 1,2,3 5.3 mA Operating supply current for array ICCOPA VCC2 = 3.6 V, VCC1 = 1.95 V 1,2,3 52 mA Input/Output capacitance 1/ CIO VCC2 = 0 V 4 7 pF Propagation delay, SysClk rising to MemCsN_0 falling 2/ tP0 VCC2 = 3.0 V 9,10,11 18 ns Propagation delay, SysClk rising to CanTx_0 rising 2/ tP1 VCC2 = 3.0 V 9,10,11 29 ns Propagation delay, SysClk rising to Gpio_22 rising 2/ tP2 VCC2 = 3.0 V 9,10,11 25 ns Propagation delay, SysClk rising to FifoD_1 rising 2/ tP3 VCC2 = 3.0 V 9,10,11 16 ns Propagation delay, SpwClkSrc rising to SpwDout_P_0 falling 2/ tP4 VCC2 = 3.0 V 9,10,11 14 ns Propagation delay, SpwClkSrc rising to SpwDout_N_0 rising 2/ tP5 VCC2 = 3.0 V 9,10,11 14 ns 1/ 2/ This parameter is tested initially and after major process changes, otherwise guaranteed. Unless otherwise specified the capacitance load shall be 50 pF in worst case. Input signals dynamic characteristics: tr, tf < 10 ns Threshold voltages: VOL = VOH = VCC/2. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 5 Case X SEATING PLANE 0.15(.006) D A2 D1 W V U e T R P N M L E E1 K J H b G F E D C B A 1 TOP VIEW Symbol A A1 A2 b 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A1 BOTTOM VIEW A Millimeters Min Max Dimensions Inches Symbol Min Max 4.30 1.40 2.40 0.79 .169 .055 .094 .031 5.90 1.85 3.45 0.99 .232 .073 .136 .040 D/E D1/E1 e Millimeters Min Max 24.80 25.20 22.86 REF 1.27 REF Min Inches Max .976 .992 .900 REF .050 REF FIGURE 1. Case outline. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 6 Case Y 0.08(.003) D/E D1/E1 A1 e A W V U T R P N M L K J H e G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PIN 1 INDEX AREA b 349 PLS TOP VIEW Symbol A A1 D/E BOTTOM VIEW Dimensions Millimeters Symbol Min Max 2.27 24.85 3.40 2.77 25.15 Millimeters Min Max D1/E1 e 22.86 REF 1.27 REF NOTE: Lid is connected to ground FIGURE 1. Case outline - Continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 7 Case Z L A L1 G 2 PLS 264 177 265 176 D1/E1 352 89 1 88 m e b c SEE DETAIL A A2 J A1 K F DETAIL A Symbol A A1 A2 b b1 c D1/E1 e F Dimensions Symbol Millimeters Min Max Inches Min Max 2.75 3.75 2.35 3.15 0.05 0.35 0.19 0.25 0.18 0.22 0.11 0.20 47.52 48.48 0.50 Basic 4.50 5.50 .108 .148 .092 .124 .002 .014 .007 .010 .007 .009 .004 .008 1.871 1.908 .0196 Basic .177 .217 G J K L L1 L2 L3 m Millimeters Min Max Min 2.50 0.75 .098 .029 74.85 74.60 55.60 65.85 2.50 2.60 1.05 0.50 76.40 75.40 57.00 65.95 2.65 Inches Max 2.947 2.937 2.189 2.592 .098 .104 .041 .020 3.008 2.968 2.244 2.596 .104 FIGURE 1. Case outline - Continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 8 Case outline X and Y Pin Signal Pin K5 L5 K2 K7 L1 M3 L2 L3 P2 K9 M5 M1 L8 M4 N3 L7 M6 N1 P5 N2 P3 N4 L9 T2 P4 N6 L4 L6 R3 E2 D4 D5 G8 C4 A5 G4 G2 F3 G1 F5 H4 G3 H2 G5 ADAddr_0 ADAddr_1 ADAddr_2 ADAddr_3 ADAddr_4 ADAddr_5 ADAddr_6 ADAddr_7 ADCs ADData_0 ADData_1 ADData_2 ADData_3 ADData_4 ADData_5 ADData_6 ADData_7 ADData_8 ADData_9 ADData_10 ADData_11 ADData_12 ADData_13 ADData_14 ADData_15 ADRc ADRdy ADTrig ADWr CanEn_0 CanEn_1 CanRx_0 CanRx_1 CanTx_0 CanTx_1 FifoD_0 FifoD_1 FifoD_2 FifoD_3 FifoD_4 FifoD_5 FifoD_6 FifoD_7 FifoD_8 Signal F6 Fifop_0 F4 Fifop_1 F2 FifoRdN E4 FifoWrN A9 Gpio_0 B9 Gpio_1 C9 Gpio_2 D9 Gpio_3 F9 Gpio_4 J10 Gpio_5 E8 Gpio_6 B8 Gpio_7 E7 Gpio_8 D8 Gpio_9 C7 Gpio_10 G9 Gpio_11 F8 Gpio_12 A7 Gpio_13 E6 Gpio_14 B7 Gpio_15 C6 Gpio_16 D7 Gpio_17 J9 Gpio_18 A6 Gpio_19 F7 Gpio_20 D6 Gpio_21 C5 Gpio_22 B6 Gpio_23 D16 loBrdyN C16 loCsN B14 loOeN D15 loRead A15 loWrN R7 LeonDsuAct V8 LeonDsuBre N8 LeonDsuEn U7 LeonDsuRx T8 LeonDsuTx M7 LeonErrorN P7 LeonPio_0 T4 LeonPio_1 W5 LeonPio_2 T5 LeonPio_3 V6 LeonPio_4 Pin M9 N7 D11 L16 P9 R8 N9 V9 U9 P10 M10 W10 R9 T10 R11 V10 N10 W11 U12 T11 P11 L10 R12 W12 R13 T12 U13 D14 F19 D18 F16 E17 E19 E16 H13 G13 T15 N12 T16 N14 T17 R19 R16 P16 Signal Pin Signal Pin LeonPio_15 K17 MemD_14 LeonWDN K15 MemD_15 LvdsRef K13 MemD_16 LvdsRef2 J19 MemD_17 MemA_0 H17 MemD_18 MemA_1 J18 MemD_19 MemA_2 J17 MemD_20 MemA_3 K11 MemD_21 MemA_4 H15 MemD_22 MemA_5 H19 MemD_23 MemA_6 J12 MemD_24 MemA_7 H18 MemD_25 MemA_8 G17 MemD_26 MemA_9 J13 MemD_27 MemA_10 H14 MemD_28 MemA_11 F15 MemD_29 MemA_12 G18 MemD_30 MemA_13 J11 MemD_31 MemA_14 P13 MemOeN_0 MemA_15 V14 MemOeN_1 MemA_16 U16 MemOeN_2 MemA_17 W15 MemOeN_3 MemA_18 V13 MemWrN_0 MemA_19 U14 MemWrN_1 MemA_20 T13 MemWrN_2 MemA_21 L11 MemWrN_3 MemA_22 A14 PVDDPLL MemBExcN F14 PVSSPLL MemCB_0 N11 RomCsN_0 MemCB_1 P12 RomCsN_1 MemCB_2 A10 SpwClk10Mbit_0 MemCB_3 E11 SpwClk10Mbit_1 MemCB_4 D10 SpwClk10Mbit_2 MemCB_5 D13 SpwClkMult_0 MemCB_6 H12 SpwClkMult_1 MemCB_7 H11 SpwClkMuxSel MemCsN_0 C14 SpwClkPllCnfg_0 MemCsN_1 A13 SpwClkPllCnfg_1 MemCsN_2 E14 SpwClkPllCnfg_2 MemCsN_3 B13 SpwClkSrc MemD_0 C11 SpwDln_N_0 MemD_1 L17 SpwDln_N_1 MemD_2 B11 SpwDln_P_0 MemD_3 L18 SpwDln_P_1 A12 M19 R1 R4 E10 G10 B10 C10 E9 H8 H3 J5 K4 K3 V17 V16 W3 B17 A3 A17 B3 B4 C1 C2 C18 C19 U1 U2 U18 U19 V3 W17 G12 F10 A8 G7 F1 J8 H6 K6 M2 V5 W8 W9 Signal Pin SpwSOut_P_0 J15 SpwSOut_P_1 J16 SysClk G15 SysResetN F17 Tap Tck F18 Tap Tdi D17 Tap Tdo V18 Tap Tms V4 Tap TrstN W4 TestMode B18 TestSE A4 TimeClk A16 TimeTrig_1 B2 TimeTrig_2 B16 VDA0 C3 VDA1 C17 VDA2 D1 VDA3 D19 VDA4 T1 VDA5 T19 VDA6 U3 VDA7 U17 VDA8 V2 VDA9 W16 VDA10 D12 VDA11 H10 VDA12 H9 VDA13 B5 VDA14 D2 VDA15 H7 VDA16 J6 VDA17 K8 VDB0 N5 VDB1 T3 VDB2 P8 VDB3 U8 VDB4 R10 VDB5 U11 VDB6 V12 VDB7 R14 VDB8 U15 VDB9 R18 VDB10 P14 VDB11 N18 Signal VDB22 VDB23 VDB24 VDB25 VDB26 VDB30 VSA0 VSA1 VSA2 VSA3 VSA4 VSA5 VSA6 VSA7 VSA8 VSA9 VSA10 VSA11 VSA12 VSA13 VSA14 VSA15 VSA16 VSA17 VSB0 VSB1 VSB2 VSB3 VSB4 VSB5 VSB6 VSB7 VSB8 VSB9 VSB10 VSB11 VSB12 VSB13 VSB14 VSB15 VSB16 VSB17 VSB18 VSB19 FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 9 Case outline X and Y- Continued Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal H1 H5 J7 J2 J3 J1 K1 D3 G6 E1 FifoD_9 FifoD_10 FifoD_11 FifoD_12 FifoD_13 FifoD_14 FifoD_15 FifoEmpN FifoFullN FifoHalfN U4 T6 W6 P6 T7 M8 V7 U6 W7 R6 LeonPio_5 LeonPio_6 LeonPio_7 LeonPio_8 LeonPio_9 LeonPio_10 LeonPio_11 LeonPio_12 LeonPio_13 LeonPio_14 P19 T18 N16 P17 N19 P15 L12 K19 L15 K16 MemD_4 MemD_5 MemD_6 MemD_7 MemD_8 MemD_9 MemD_10 MemD_11 MemD_12 MemD_13 E13 N15 B12 M18 C12 M17 A11 L19 F12 M14 SpwDOut_N_0 SpwDOut_N_1 SpwDOut_P_0 SpwDOut_P_1 SpwSln_N_0 SpwSln_N_1 SpwSln_P_0 SpwSln_P_1 SpwSOut_N_0 SpwSOut_N_1 U10 V11 M11 W13 T14 N13 P18 M12 M13 K14 VDB12 VDB13 VDB14 VDB15 VDB16 VDB17 VDB18 VDB19 VDB20 VDB21 M16 K12 K18 J14 H16 G16 G14 F13 VSB20 VSB21 VSB22 VSB23 VSB24 VSB25 VSB26 VSB30 Not connected pins: B15, C8, C13, C15, E3, E5, E12, E15, E18, F11, G11, G19, J4, K10, L13, L14, M15, N17, P1, R2, R5, R15, R17, T9, U5, V15, W14. NOTE: VDA* are core power pins, VSA* are core ground pins VDB* are buffer power pins, VSB* are buffer ground pins FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 10 Case outline Z Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal 3 CanEn_0 47 ADAddr_0 94 LeonPio_1 138 MemA_12 185 MemD_1 4 CanEn_1 48 ADAddr_1 95 VSA8 139 MemA_13 186 MemD_2 5 FifoFullN 49 ADAddr_2 96 VDA8 140 MemA_14 187 VDB18 6 FifoEmpN 50 ADAddr_3 97 LeonPio_2 141 VDB13 188 VSB18 7 VSA4 51 ADAddr_4 98 LeonPio_3 142 VSB13 189 MemD_3 8 VDA4 52 ADAddr_5 99 LeonPio_4 145 MemA_15 191 MemD_4 9 FifoHalfN 53 ADAddr_6 100 LeonPio_5 146 MemA_16 192 MemD_5 10 FifoWrN 54 ADAddr_7 101 LeonPio_6 147 MemA_17 193 MemD_6 11 FifoRdN 57 ADRdy 104 LeonPio_7 148 MemA_18 194 VDB19 12 FifoP_0 58 ADTrig 105 LeonPio_8 149 MemA_19 195 VSB19 13 FifoP_1 59 ADData_0 106 LeonPio_9 150 VDB14 196 MemD_7 16 VDB4 60 ADData_1 107 LeonPio_10 151 VSB14 197 MemD_8 17 VSB4 61 ADData_2 108 LeonPio_11 152 MemA_20 198 MemD_9 18 FifoD_0 62 ADData_3 109 LeonPio_12 153 MemA_21 199 MemD_10 19 TestMode 63 VDB8 110 LeonPio_13 154 MemA_22 200 VDB20 20 FifoD_1 64 VSB8 111 LeonPio_14 155 RomCsN_0 202 VSB20 21 FifoD_2 65 ADData_4 112 LeonPio_15 156 RomCsN_1 203 SpwDOut_P_1 SpwDOut_N_1 22 FifoD_3 66 ADData_5 113 LeonDsuEn 157 VDB15 205 23 FifoD_4 67 ADData_6 114 LeonDsuTx 158 VSB15 206 SpwSOut_P_1 24 VDB5 68 ADData_7 115 LeonDsuRx 159 MemWrN_0 208 SpwSOut_N_1 25 VSB5 69 ADData_8 116 LeonDsuBre 160 MemWrN_1 210 LvdsRef2 26 FifoD_5 70 ADData_9 117 LeonDsuAct 161 MemWrN_2 211 SpwDIn_P_1 27 FifoD_6 71 ADData_10 118 VDB10 162 MemWrN_3 212 SpwDIn_N_1 28 FifoD_7 72 ADData_11 119 VSB10 164 MemOeN_0 213 SpwSIn_P_1 29 FifoD_8 73 ADData_12 120 MemA_0 165 VDB16 214 SpwSIn_N_1 30 FifoD_9 74 ADData_13 121 MemA_1 166 VSB16 215 VDB21 31 VDB6 76 ADData_14 124 MemA_2 167 MemOeN_1 217 VSB21 32 VSB6 77 ADData_15 125 MemA_3 168 MemOeN_2 218 MemD_11 33 FifoD_10 78 ADWr 126 MemA_4 169 VSA10 219 MemD_12 36 FifoD_11 79 ADCs 127 VDB11 170 VDA10 220 MemD_13 37 FifoD_12 80 ADRc 128 VSB11 171 MemOeN_3 221 MemD_14 38 FifoD_13 81 VSA6 129 MemA_5 172 MemCsN_0 222 MemD_15 39 FifoD_14 82 VDA6 130 MemA_6 173 MemCsN_1 223 VDB22 40 TestSE 83 SysClk 131 MemA_7 175 VDB17 224 VSB22 41 VDB7 84 SysResetN 132 MemA_8 179 VSB17 225 MemD_16 42 VSB7 85 LeonErrorN 133 MemA_9 180 MemCsN_2 226 MemD_17 43 FifoD_15 87 LeonWDN 134 VDB12 181 MemCsN_3 227 MemD_18 44 TimeClk 91 VDB9 135 VSB12 182 MemD_0 228 MemD_19 45 TimeTrig_1 92 VSB9 136 MemA_10 183 VSA12 230 MemD_20 46 TimeTrig_2 93 LeonPio_0 137 MemA_11 184 VDA12 231 VDB23 FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 11 Case outline Z – Continued. Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal 233 234 235 236 237 238 239 240 241 242 243 247 248 249 250 251 252 253 254 255 256 VSB23 MemD_21 MemD_22 MemD_23 MemD_24 MemD_25 VDB24 VSB24 MemD_26 MemD_27 MemD_28 MemD_29 MemD_30 VDB25 VSB25 MemD_31 MemCB_0 MemCB_1 MemCB_2 MemCB_3 VDB26 257 258 259 260 261 262 263 267 268 269 270 271 272 273 274 275 276 279 280 281 282 VSA14 VDA14 VSB26 MemCB_4 MemCB_5 MemCB_6 MemCB_7 VDB30 VSB30 IoBrdyN IoWrN VSA1 VDA1 IoRead IoOeN IoCsN MemBExcN PVDDPLL PVSSPLL SpwClkMult_0 SpwClkMult_1 283 284 285 286 287 288 290 291 293 294 296 298 299 300 301 302 303 305 306 307 308 SpwClkSrc SpwClkPllCnfg_0 SpwClkPllCnfg_1 SpwClkPllCnfg_2 SpwClkMuxSel VDB0 VSB0 SpwDOut_P_0 SpwDOut_N_0 SpwSOut_P_0 SpwSOut_N_0 LvdsRef SpwDIn_P_0 SpwDIn_N_0 SpwSIn_P_0 SpwSIn_N_0 VDB1 VSB1 SpwClk10Mbit_0 SpwClk10Mbit_1 SpwClk10Mbit_2 309 310 311 312 313 314 317 318 319 320 322 323 324 325 326 327 328 329 330 331 332 TapTms TapTck TapTrstN TapTdo TapTdi Gpio_0 Gpio_1 Gpio_2 Gpio_3 Gpio_4 Gpio_5 Gpio_6 VDB2 VSB2 Gpio_7 Gpio_8 Gpio_9 Gpio_10 Gpio_11 Gpio_12 Gpio_13 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 351 Gpio_14 Gpio_15 Gpio_16 Gpio_17 Gpio_18 Gpio_19 Gpio_20 Gpio_21 Gpio_22 Gpio_23 CanTx_0 CanTx_1 VSA2 VDA2 CanRx_0 CanRx_1 VDB3 VSB3 Not connected pins: 1, 2, 14, 15, 34, 35, 55, 56, 75, 86, 88, 89, 90, 102, 103, 122, 123, 143, 144, 163, 174, 176, 177, 178, 190, 201, 204,;207, 209, 216, 229, 232, 244, 245, 246, 264, 265, 266, 277, 278, 289, 292, 295, 297, 304, 315, 316, 321, 350, 352. NOTES: VDA* are core power pins, VSA* are core ground pins. VDB* are buffer power pins, VSB* are buffer ground pins. FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 12 SRAM,PROM EEPROM,FLASH-PROM RS232/422 MEMORY CONTROLLER DEBUG SERIAL LINK UNIT DEBUG SUPPORT UNIT AHB I/F AHB I/F AHB I/F MEIKO FLOATING POINT UNIT LEON2-FT SPARC V8 INTEGER UNIT I-CASHE D-CASHE AHB ARBITER/ DECODER AHB I/F RS232/422 AMBA AHB GPIO IRQ UARTS TIMERS AHB/APB BRIDGE AMBA APB AMBA AHB AMBA APB 32 BIT TIMERS 24 BIT GENERAL PURPOSE I/O DISCRETE SIGNALS ADC/DAC CTRL I/F ADC/DAC AHB I/F AHB I/F AHB I/F AHB I/F FIFO CTRL I/F CAN CONTROLLER SPACE WIRE LINK ON-CHIP MEMORY FIFO CAN NETWORK SPACEWIRE NETWORK FIGURE 3. Block diagram. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 13 DATA 1 DATA 2 LEAD-OUT Sysclk A1 MemA t p0 MemCsN MemOeN D1 MemD Sysclk FifoWrN tp3 tp3 FifoD FifoFullN Sysclk tp1 tp1 Can_Tx tp2 GPIO SpwClkSrc tp5 SpwDoutN t p4 SpwDoutP FIGURE 4. Timing waveforms. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 14 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection.. 4.2.1 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. 4.4.1 Group A inspection. a. Tests shall be as specified in table II herein. b. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 15 TABLE II. Electrical test requirements. Test requirements Interim electrical parameters (see 4.2) Final electrical parameters (see 4.2) Group A test requirements (see 4.4) Group C end-point electrical parameters (see 4.4) Group D end-point electrical parameters (see 4.4) Group E end-point electrical parameters (see 4.4) Subgroups (in accordance with MIL-STD-883, method 5005, table I) Device class M 1,7,9 Subgroups (in accordance with MIL-PRF-38535, table III) Device class Q 1,7,9 Device class V 1,7,9 1, 2, 3, 4, 7, 8, 9, 10, 11 1/ 1, 2, 3, 4, 7, 8, 9, 10, 11 1/ 1, 2, 3, 4, 7, 8, 9, 10, 11, ∆ 2/ 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1,7,9 1,7,9 1,7,9, ∆ 1,7,9 1,7,9 1,7,9 1,7,9 1,7,9 1,7,9 1/ PDA applies to subgroup 1. 2/ PDA applies to subgroups 1 and 7. 3/ Delta limits, as specified in table IIB, shall be required where specified, and the delta values shall be completed with reference to the zero hour electrical parameters. TABLE IIB. Burn-in delta parameters (25°C). Parameter IIL/IIH IOZL/IOZH ICCSB Limit +/- 10% of specificied value in table 1 +/- 10% of specificied value in table 1 +/- 10% of specificied value in table 1 Unit µA µA mA NOTE: The parameters shall be recorded before and after the required burn-in and lifetest to determine the delta limits. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table II herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C, after exposure, to the subgroups specified in table II herein. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. c. 4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883, method 1019, condition A, and as specified herein. 4.4.4.1.1 Accelerated annealing testing. Accelerated annealing testing shall be performed on all devices requiring a RHA level greater than 5 krads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the pre-irradiation end-point electrical parameter limits at 25°C ±5°C. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 16 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor prepared specification or drawing. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108. 6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0540. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in MIL-HDBK-103 and QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime-VA and have agreed to this drawing. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10A03 A REVISION LEVEL A SHEET 17 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 13-02-11 Approved sources of supply for SMD 5962-10A03 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ 5962-10A0301QXB 5962-10A0301VXB 5962R10A0301VXB 5962-10A0301QYC 5962-10A0301VYC 5962R10A0301VYC 5962-10A0301QZC 5962-10A0301VZC 5962R10A0301VZC Vendor CAGE number F7400 F7400 F7400 F7400 F7400 F7400 F7400 F7400 F7400 Vendor similar PIN 2/ AT7913E2H-MQ AT7913E2H-SV AT7913E2H-SR AT7913E2U-MQ AT7913E2U-SV AT7913E2U-SR AT7913EYC-MQ AT7913EYC-SV AT7913EYC-SR 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number F7400 Vendor name and address Atmel Nantes La Chantrerie 44306 Nantes Cedex3 France The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.