ATWILC3000 Hardware Design Guidelines IEEE 802.11 b/g/n + BT4.0 Combo SoC for IoT Applications USER GUIDE VDDIO VBAT Antenna Chip_En Reset_n Wake SPI/SDIO IRQn ATWILC3000 802.11 B/G/N SOC +BT 4.0 Balun UART/PCM 26 MHz GPIO Block Diagram Introduction This document details the hardware design guidelines for a customer to design the Atmel® ATWILC3000 IC onto their board. Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 Ta bl e of Conte nts 1 Reference Schematic................................................................................................... 3 1.1 2 Notes on Interfacing to the ATWILC3000 ................................................................... 4 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Programmable Pull-up Resistors ........................................................................................................... 4 Restrictions for Power States ................................................................................................................ 5 Power-up/down Sequence .................................................................................................................... 5 Digital I/O Pin Behavior during Power-up Sequences ........................................................................... 6 Placement and Routing Guidelines ....................................................................................................... 6 Power and Ground ................................................................................................................................ 7 RF Traces and Components ................................................................................................................. 7 Sensitive Routes ................................................................................................................................... 8 2.8.1 Signals ...................................................................................................................................... 8 2.8.2 Supplies .................................................................................................................................... 8 Additional Suggestions .......................................................................................................................... 9 3 Interferers ..................................................................................................................... 9 4 Thermal Considerations ............................................................................................ 10 5 External Interfaces ..................................................................................................... 10 5.1 5.2 5.3 General .............................................................................................................................................. 10 SPI Interface........................................................................................................................................ 11 5.2.1 Overview ................................................................................................................................. 11 5.2.2 SPI Timing .............................................................................................................................. 12 5.2.3 SPI PCB Trace Constraints .................................................................................................... 12 UART Interface.................................................................................................................................... 13 6 Antenna 7 FCC, TELEC, ETSI Compliance ................................................................................. 14 8 Reference Documentation and Support ................................................................... 14 8.1 9 2 Schematic.............................................................................................................................................. 3 ................................................................................................................... 13 Reference Documents ......................................................................................................................... 14 Revision History ........................................................................................................ 15 ATWILC3000 Hardware Design Guidelines [USER GUIDE] 2 Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 1 Reference Schematic 1.1 Schematic Figure 1-1 shows the reference schematic for a system using the ATWILC3000. Note that there are several 0Ω resistors (R1-R12) shown in series with signals to the chip. These are place holders in case filtering of these lines is necessary due to high frequency in band (2.4GHz) noise on these lines, which can get into the RF path and degrade receiver sensitivity. If the signals coming from the host MCU are noise free, then these placeholders are not required and can be removed. Figure 1-1. Reference Schematic Figure 1-2. Bill of Materials ATWILC3000 Hardware Design Guidelines [USER GUIDE] Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 3 3 2 Notes on Interfacing to the ATWILC3000 2.1 Programmable Pull-up Resistors The ATWILC3000 provides programmable pull-up resistors on various pins. The purpose of these resistors is to keep any unused input pins from floating which can cause excess current to flow through the input buffer from the VDDIO supply. Any unused chip pin on the ATWILC3000 should leave these pullup resistors enabled so the pin will not float. The default state at power up is for the pull-up resistor to be enabled. However, any pin which is used should have the pull-up resistor disabled. The reason for this is that if any pins are driven to a low level while the ATWILC3000 is in the low power sleep state, current will flow from the VDDIO supply through the pull-up resistors, increasing the current consumption of the chip. Since the value of the pull-up resistor is approximately 100kΩ, the current through any pull-up resistor that is being driven low will be VDDIO/100kΩ. For VDDIO = 3.3V, the current through each pull-up resistor that is driven low would be approximately 3.3V/100kΩ = 33µA. Pins which are used and have had the programmable pull-up resistor disabled should always be actively driven to either a high or low level and not be allowed to float. See the ATWILC3000 Programming Guide for information on enabling/disabling the programmable pullup resistors. Figure 2-1. ATWILC3000 Pad ESD Structure This shows why it is important that any time Chip_En to the chip is low, all pins interfacing to the chip must not be driven or pulled high. They should either be set to a low level or high impedance state. This means that if any external pull-up resistors are attached to any pins they should be disconnected from the supply when Chip_En is low. 4 ATWILC3000 Hardware Design Guidelines [USER GUIDE] 4 Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 Figure 2-2. 2.2 Current Path through ESD Diode Restrictions for Power States When no power supplied to the device, i.e., the DC/DC Converter output and VDDIO are both off (at ground potential). In this case, a voltage cannot be applied to the device pins because each pin contains an ESD diode from the pin to supply. This diode will turn on when voltage higher than one diode-drop is supplied to the pin. If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must be on, so the SLEEP or Power_Down state must be used. Similarly, to prevent the pin-to-ground diode from turning on, do not apply a voltage that is more than one diode-drop below ground to any pin. 2.3 Power-up/down Sequence The power-up/down sequence for ATWILC3000A is shown in Figure 2-3. The timing parameters are provided in Table 2-1. Figure 2-3. Power-up/down Sequence VBATT tA t A' VDDIO tB t B' CHIP_EN tC t C' RESETN XO Clock ATWILC3000 Hardware Design Guidelines [USER GUIDE] Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 5 5 Table 2-1. Power-up/down Sequence Timing Parameter 2.4 Min. Max. Units Description Notes tA 0 ms VBATT rise to VDDIO rise VBATT and VDDIO can rise simultaneously or can be tied together. VDDIO must not rise before VBATT. tB 0 ms VDDIO rise to CHIP_EN rise CHIP_EN must not rise before VDDIO. CHIP_EN must be driven high or low, not left floating. tC 5 ms CHIP_EN rise to RESETN rise This delay is needed because XO clock must stabilize before RESETN removal. RESETN must be driven high or low, not left floating. tA’ 0 ms VDDIO fall to VBATT fall VBATT and VDDIO can fall simultaneously or can be tied together. VBATT must not fall before VDDIO. tB’ 0 ms CHIP_EN fall to VDDIO fall VDDIO must not fall before CHIP_EN. CHIP_EN and RESETN can fall simultaneously. tC’ 0 ms RESETN fall to VDDIO fall VDDIO must not fall before RESETN. RESETN and CHIP_EN can fall simultaneously. Digital I/O Pin Behavior during Power-up Sequences Table 2-2 represents digital I/O pin states corresponding to device power modes. Table 2-2. Digital I/O Pin Behavior in Different Device States Device state Power Down: core supply off CHIP_EN RESETN Output driver Disabled (Hi-Z) Input driver Pull-up/down resistor (96kΩ) High Low Low High High Low Disabled (Hi-Z) Disabled Enabled High Power-On Default: core supply on, device out of reset but not programmed yet High High Disabled (Hi-Z) Enabled Enabled High On Sleep/ On Transmit/ On Receive: core supply on, device programmed by firmware High High Programmed by firmware for each pin: Enabled or Disabled Opposite of Output Driver state Programmed by firmware for each pin: Enabled or Disabled Power-On Reset: core supply on, hard reset on 2.5 VDDIO Disabled Disabled Placement and Routing Guidelines It is critical to follow the recommendations listed below to achieve the best RF performance: 6 The board should have a solid ground plane. The center ground pad of the device must be solidly connected to the ground plane by using a 3 x 3 grid of vias. ATWILC3000 Hardware Design Guidelines [USER GUIDE] 6 Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 2.6 Keep away from antenna, as far as possible, large metal objects to avoid electromagnetic field blocking Do not enclose the antenna within a metal shield Keep any components which may radiate noise or signals within the 2.4 – 2.5GHz frequency band far away from the antenna or better yet, shield those components. Any noise radiated from the main board in this frequency band will degrade the sensitivity of the chip. Power and Ground Dedicate one layer as a ground plane. Make sure that this ground plane does not get broken up by routes. Power can route on all layers except the ground layer. Power supply routes should be heavy copper fill planes to insure the lowest possible inductance. The power pins of the ATWILC3000 should have a via directly to the power plane as close to the pin as possible. Decoupling capacitors should have a via right next to the capacitor pin and this via should go directly down to the power plane – that is to say, the capacitor should not route to the power plane through a long trace. The ground side of the decoupling capacitor should have a via right next to the pad which goes directly down to the ground plane. Each decoupling capacitor should have its own via directly to the ground plane and directly to the power plane right next to the pad. The decoupling capacitors should be placed as close to the pin that it is filtering as possible. 2.7 RF Traces and Components The RF traces that go from the ATWILC3000 to the balun must be 50Ω differential controlled impedance. These are pins 5 and 6 of the ATWILC3000. The route from the balun to the antenna connector must be a 50Ω controlled impedance trace. These controlled impedance traces must reference a ground plane on a lower layer. To achieve 50Ω impedance, a typical design might be 20 mil traces referenced to a ground plane on an inner layer which is 10.7 mils below the traces. This must be adjusted depending on the dielectric and copper weight used. No other traces must route through the RF area on layers between the RF traces and the ground reference plane. In fact, try not to route any other traces in the RF area on any layer. This ground reference plane must extend entirely under the tuner. Be sure to add as many ground vias as possible, tying all ground layers together (ground stitching) all along the RF traces and throughout the area where the RF traces are routed. Add at least two ground vias for every ground pad around the RF components. Place ground vias all along the RF traces on either side. Tie the center ground pad of the ATWILC3000 to the inner ground layer using a grid of nine vias. The ground path going from the ground pad down to the ground plane must be absolutely as low impedance as possible. Do not use thermal relief pads for the ground pads of all components in the RF path. These component pads must be completely filled in with ground copper. Be sure to place the matching components and balun as close to the RFIOP and RFION pins as possible (these C33, C23, C25, C17, C32, L8, and L9 in the reference schematic). Figure 2-4 shows the placement and routing of these components. Note that they are placed as close as possible to the ATWILC3000’s pins 5 and 6. The components used for this design are 0201. Note that the width of the route matches the width of the component pads. This will avoid impedance discontinuities which would occur if there is a large mismatch in trace width versus the component pad size. ATWILC3000 Hardware Design Guidelines [USER GUIDE] Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 7 7 Figure 2-4. Placement and Routing of Balun and Matching Components Be sure the route from the antenna to the ATWILC3000 is as short as possible and is completely isolated from all other signals on the board. No signals should route under this trace on any layer of the board. Make sure that all digital signals that may be toggling while the ATWILC3000 active are placed as far away from the antenna as possible. No connectors which have digital signals going to them should be near the antenna. All digital components and switching regulators on the board should be shielded so they do not radiate noise that is picked up by the antenna. In summary, make sure anything that switches is shielded and kept away from the antenna, the ATWILC3000 or the route from the ATWILC3000 to the antenna. 2.8 Sensitive Routes 2.8.1 Signals The following signals are very sensitive to noise and you must take care to keep them as short as possible and keep them isolated from all other signals by routing them far away from other traces or using ground to shield them. Be sure that they are also isolated from noisy traces on the layers above them and below them: XO_N XO_P RFIOP RFION 2.8.2 Supplies The following power supply pins for the ATWILC3000 are sensitive to noise and care should be taken to isolate the routes to these pins from other noisy signals both on the same layer as the route and on layers above and below. Use ground between these sensitive signals to isolate them from other signals. It is important that the decoupling capacitors for these supplies are placed as close to the ATWILC3000 pin as possible. This is necessary to reduce the trace inductance between the capacitor and ATWILC3000 power pin to an absolute minimum: 8 ATWILC3000 Hardware Design Guidelines [USER GUIDE] 8 Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 VDDRF_RX (pin 1) VDDRF_TX (pin 3) VDD_AMS (pin 2) VDD_SXDIG (pin 45) VDD_VCO (pin 46) Additionally, while the VDDC (pin 18) and VBAT_BUCK (pin 24) supplies are not sensitive to picking up noise, they are noise generating supplies. Therefore, be sure to keep the decoupling capacitors for these supply pins as close as possible to the VDDC and VBAT_BUCK pins and make sure that the routes for these supplies stay far away from sensitive pins and supplies. 2.9 Additional Suggestions Make sure that traces route directly through the pads of all filter capacitors and not by way of a stub route. The following routes are extremely critical and should be routed first. c) is a power route and should be a heavy copper route. These routes must not have anything above, below, or to the side of them except ground. They must be as short as possible. Make sure that the filter capacitor for these pins is placed right next to the pin. a) The 50Ω differential pair from ATWILC3000 pins 5 and 6 to the balun. Be sure this route is as short as possible and that both routes of the differential pair are matched in length. b) The 50Ω unbalanced route from the balun to the antenna. c) The routes to the XO_P and XO_N pins (pins 43 and 44). These must be isolated with ground above, below and to the sides of the routes. d) The route from ATWILC3000 pin 25 (VSW) to the 15nH inductor (L5) must be as short and as wide as possible. Make sure this inductor is placed right next to pin 25. The route from the other side of this inductor to the 1.0µH inductor (L1) must also be as short and heavy as possible. Then the route from L1 to the 10µF capacitor (C10) and to pin 26 must also be as short and heavy as possible. e) The loop created from ATWILC3000 pin 25 through the inductors the capacitor and back to pin 26 must be as small as possible. f) Make sure the ground return path from the 10µF capacitor connected to pin 26 back to the ground pad of the ATWILC3000 is as short and wide as possible. This is critical. The ground return path must be extremely low inductance. Failure to provide a short, heavy ground return between the capacitor and the ATWILC3000 ground pad will result in incorrect operation of the on chip switching regulator. Be sure to place the power supply decoupling capacitors so that there is a capacitor very close to each power supply pin of the device. This requires making the copper as short and as wide as possible – use copper fills for the power supply routing from the pins to the filter capacitors, not narrow traces. 3 Interferers One of the biggest problems with RF receivers is poor performance due to interferers on the board radiating noise into the antenna or coupling into the RF traces going to input LNA. Care must be taken to make sure that there is no noisy circuitry placed anywhere near the antenna or the RF traces. All noise generating circuits should also be shielded so they do not radiate noise that is picked up by the antenna. Also, make sure that no traces route underneath the RF portion of the ATWILC3000. Also, make sure that no traces route underneath any of the RF traces from the antenna to the ATWILC3000 input. This applies to all layers. Even if there is a ground plane on a layer between the RF route and another signal, the ground return current will flow on the ground plane and couple into the RF traces. ATWILC3000 Hardware Design Guidelines [USER GUIDE] Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 9 9 4 Thermal Considerations Table 4-1 lists the thermal resistance from junction to ambient (JA) and from junction to case (JC) for 6x6 48L QFN. Table 4-1. Thermal Resistance from Junction to Ambient and from Junction to Case JA Package 5x5mm 40L QFN JC 29.5ºC/W 3.7ºC/W Junction-to-ambient thermal resistance JA is a one-dimensional value that measures the conduction of heat from the junction (hottest temperature on die) to the environment near the package. The heat that is generated on the die surface reaches the immediate environment along two paths: (1) convection and radiation off the exposed surface of the package and (2) conduction into and through the test board followed by convection and radiation off the exposed board surfaces. JA reported here assumes the package is mounted on a board with two signal layers and two internal planes (2s2p). 5 External Interfaces 5.1 General Digital Pad Characteristics are given in Table 5-1. Table 5-1. Digital Pad Characteristics Symbol VDDIOL (2) Characteristics Min. Typ. Max. Unit I/O Supply Voltage Low Range 1.62 1.80 2.00 V VDDIOM(2) I/O Supply Voltage Mid Range 2.00 2.50 3.00 V VDDIOH(2) I/O Supply Voltage High Range 3.00 3.30 3.60 V VBATT(3) Battery Supply Voltage 2.5(4) 3.6 4.2 V Operating Temperature -30 85 ºC Note: 1. 2. 3. 4. Refer to datasheet for details of power connections. I/O supply voltage is applied to the following pins: VDDIO_A, VDDIO_0, VDDIO_1. Battery supply voltage is applied to following pins: VDDBATT_PPA/PA, VBATT_BUCK. Device is functional across this range of voltages; however, optimal RF performance is guaranteed for VBATT in the range 3.0V < VBATT < 4.2V. Table 5-2. VDDIO condition Characteristic Min. Max. Unit Input Low Voltage VIL -0.30 0.60 V Input High Voltage VIH VDDIO-0.60 VDDIO+0.30 V 0.45 V Output Low Voltage VOL VDDIOL Output High Voltage VOH VDDIO-0.50 V I2 C 4 mA 2 mA Pad Drive Strength (1) All other Digital Pad Drive Strength 10 ATWILC3000 Hardware Design Guidelines [USER GUIDE] 1 Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 0 VDDIO condition Characteristic Min. Max. Unit Input Low Voltage VIL -0.30 0.63 V Input High Voltage VIH VDDIO-0.60 VDDIO+0.30 V 0.45 V Output Low Voltage VOL VDDIOM Output High Voltage VOH VDDIO-0.50 V I2C Pad Drive Strength (1) 8 mA All other Digital Pad Drive Strength 4 mA Input Low Voltage VIL -0.30 0.65 V Input High Voltage VIH VDDIO-0.60 VDDIO+0.30 (up to 3.60) V 0.45 V Output Low Voltage VOL VDDIOH Output High Voltage VOH VDDIO-0.50 V I2 C 12 mA 6 mA Pad Drive Strength (1) All other Digital Pad Drive Strength All Output Loading 20 pF All Digital Input Load 6 pF Note: 1. I2C Pad Drive Strength applies to the following pins: I2C_SDA, I2C_SCL. 5.2 SPI Interface 5.2.1 Overview ATWILC3000 has a Serial Peripheral Interface (SPI) that operates as a SPI slave. The SPI interface can be used for control and for serial I/O of 802.11 data. The SPI pins are mapped as shown in Table 5-3. The SPI is a full-duplex slave-synchronous serial interface that is available immediately following reset when pin 12 (SPI_CFG) is tied to VDDIO. Table 5-3. SPI Interface Pin Mapping Pin # SPI function 12 CFG: Tied to VDDIO if SPI is used. Tied to GND is SDIO is used. 32 SSN: Active Low Slave Select 34 MOSI(RXD): Serial Data Receive 30 SCK: Serial Clock 31 MISO(TXD): Serial Data Transmit When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted data output is buffered, resulting in a high impedance drive onto the MISO line. The SPI interface responds to a protocol that allows an external host to read or write any register in the chip as well as initiate DMA transfers. The SPI SSN, MOSI, MISO, and SCK pins of the ATWILC3000 have internal programmable pull-up resistors. These resistors should be programmed to be disabled. Otherwise, if any of the SPI pins are ATWILC3000 Hardware Design Guidelines [USER GUIDE] Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 11 1 1 driven to a low level while the ATWILC3000 is in the low power sleep state, current will flow from the VDDIO supply through the pull-up resistors, increasing the current consumption of the chip. 5.2.2 SPI Timing The SPI timing is provided in Figure 5-1 and Table 5-4. Figure 5-1. SPI Timing Diagram (SPI Mode CPOL=0, CPHA=0) fSCK tLH tWH SCK tWL tHL TXD t ODLY RXD tISU SSN SPI Master SSN SPI Slave Table 5-4. tSSODLY t SUSSN t HDSSN SPI Slave Timing Parameters Parameter 5.2.3 tIHD Symbol Min. Max. 48 Unit Clock Input Frequency fSCK Clock Low Pulse Width tWL 5 ns Clock High Pulse Width tWH 5 ns Clock Rise Time tLH 5 ns Clock Fall Time tHL 5 ns Input Setup Time tISU 5 ns Input Hold Time tIHD 5 ns Output Delay tODLY 0 Slave Select Setup Time TSUSSN 5 ns Slave Select Hold Time tHDSSN 5 ns 20 Remarks MHz ns SPI PCB Trace Constraints In general, the SPI PCB trace layout must ensure that the total capacitance (trace and load of other pin) on the SPI lines (SPI_RXD, SPI_SSN, SPI_TXD, and SPI_SCK) are less than the maximum pin capacitance of 20pF (see Section 5.1). As this is heavily dependent on the board type and lithography, no single constraint of trace length can be given. It is, however, preferable to minimize the trace length as much as possible. For further guidance, consult your Atmel FAE. Be sure to have all information on the application PCB layout design rules. 12 ATWILC3000 Hardware Design Guidelines [USER GUIDE] 1 Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 2 5.3 UART Interface The ATWILC3000 has a Universal Asynchronous Receiver/Transmitter (UART) interface available on pins 14 and 15. It can be used for control or data transfer if the baud rate is sufficient for a given application. The UART is compatible with the RS-232 standard, where ATWILC3000 operates as Data Terminal Equipment (DTE). It has a two-pin RXD/TXD interface. The UART features programmable baud rate generation with fractional clock division, which allows transmission and reception at a wide variety of standard and non-standard baud rates. The UART input clock is selectable between 10MHz, 5MHz, 2.5MHz, and 1.25MHz. The clock divider value is programmable as 13 integer bits and three fractional bits (with 8.0 being the smallest recommended value for normal operation). This results in the maximum supported baud rate of 10MHz / 8.0 = 1.25MBd. The UART can be configured for seven or eight bit operation, with or without parity, with four different parity types (odd, even, mark, or space), and with one or two stop bits. It also has Rx and Tx FIFOs, which ensure reliable high speed reception and low software overhead transmission. FIFO size is 4 x 8 for both Rx and Tx direction. The UART also has status registers showing the number of received characters available in the FIFO and various error conditions, as well the ability to generate interrupts based on these status bits. An example of UART receiving or transmitting a single packet is shown in Figure 5-2. This example shows 7-bit data (0x45), odd parity, and two stop bits. See the ATWILC3000 Programming Guide for information on configuring the UART. Figure 5-2. 6 Example of UART Rx or Tx packet Antenna Make sure to choose an antenna that covers the proper frequency band, 2.400 to 2.500GHz. Talk to the antenna vendor and make sure he understands the full frequency range that must be covered by the antenna. Make sure the antenna is designed for a 50Ω system. Make sure the PCB pad that the antenna is connected to is properly designed for 50Ω impedance. This is extremely important. The antenna vendor must specify the pad dimensions, the spacing from the pad to the ground reference plane, and the spacing from the edges of the pad to the ground fill on the same layer as the pad. Also, since the ground reference plane for the 50 trace going from the antenna pad to the ATWILC3000 will probably be on a different layer than the ground reference for the antenna pad, make sure the pad design has a proper transition from the pad to the 50Ω trace. Make sure that the antenna matching components are placed as close to the antenna pad as possible. The antenna cannot be properly matched if the matching components are far away from the antenna. ATWILC3000 Hardware Design Guidelines [USER GUIDE] Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 13 1 3 7 FCC, TELEC, ETSI Compliance The reference design provided is compliant with FCC, TELEC, and ETSI regulations. No Calibrations are needed by the device maker if the 26MHz crystal used meets the 802.11 requirements (±20ppm). For crystals variations outside this range, consult your Atmel FAE. 8 Reference Documentation and Support 8.1 Reference Documents Atmel offers a set of collateral documentation to ease integration and device ramp. The following list of documents available on Atmel web or integrated into development tools. Table 8-1. Reference Documents Title Content Datasheet Design Files Package User Guide, Schematic, PCB layout, Gerber, BOM and System notes on: RF/Radio Full Test Report, radiation pattern, design guidelines, temperature performance, ESD. Platform Getting started Guide How to use package: Out of the Box starting guide, HW limitations and notes, SW Quick start guidelines HW Design Guide This document SW Design Guide Integration guide with clear description of: High level Arch, overview on how to write a networking application, list all API, parameters and structures. Features of the device, SPI/handshake protocol between device and host MCU, with flow/sequence/state diagram, timing. SW Programmer guide Explain in details the flow chart and how to use each API to implement all generic use cases (e.g. start AP, start STA, provisioning, UDP, TCP, http, TLS, p2p, errors management, connection/transfer recovery mechanism/state diagram) - usage and sample application note For a complete listing of development-support tools and documentation, visit http://www.atmel.com/ or contact the nearest Atmel field representative. 14 ATWILC3000 Hardware Design Guidelines [USER GUIDE] 1 Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 4 9 Revision History Doc Rev. Date 42513A 10/2015 Comments Initial document release. ATWILC3000 Hardware Design Guidelines [USER GUIDE] Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 15 1 5 Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 │ www.atmel.com © 2015 Atmel Corporation. / Rev.: Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. ARM®, ARM Connected® logo, and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel prod ucts. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON -INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LI MITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF A TMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accurac y or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel product s are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connectio n with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation o f nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically desi gnated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive -grade. Atmel-42513A-ATWILC3000-Hardware-Design-Guidelines_UserGuide_102015 16 ATWILC3000 Hardware Design Guidelines [USER GUIDE] 1 6