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USER GUIDE
ATWILC1000 Hardware Design Guidelines
Atmel SmartConnect
Introduction
This document details the hardware design guidelines for a customer to design
the Atmel® ATWILC1000 IC onto their board.
Atmel-42431A-ATWILC1000-Hardware-Design-Guidelines_UserGuide_03/2015
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Block Diagram
Figure 1-1 shows a block diagram for a typical application.
Figure 1-1.
Block Diagram
VDDIO
VBAT
Chip_En
Reset_n
Wake
SPI
IRQn
ATWILC1000
802.11 B/G/N SOC
Balun
UART
26 MHz
GPIOs
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Reference Schematic
2.1
Schematic
Figure 2-1 shows the reference schematic for a system using the ATWILC1000. Note that there are several 0Ω
resistors (R1 – R10) shown in series with signals to the module. These are place holders in case filtering of
these lines is necessary due to high frequency in band (2.4GHz) noise is on these lines which can get into the
RF path and degrade receiver sensitivity. If the signals coming from the host MCU are noise free, then these
placeholders are not required and can be removed.
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Figure 2-1.
4
Reference Schematic
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Table 2-1.
Item
Bill Of Materials
Qty.
Reference
1
1
C1
2
8
3
4
Value
0.01µF
Description
Manufacturer
CAP,CER,0.01µF,10%X5R,0201,10V,-55125ºC
Part Number
Footprint
Murata
GRM033R61A103KA01D
CS0201
C2,C4,C5,C6,C8,C11,
0.1µF
C12,C19
CAP,CER,0.1µF,10%X5R,0201,6.3V,-55-125ºC Murata
GRM033R60J104KE19D
CS0201
2
C3,C10
2.2µF
CAP,CER,2.2µF,10%X5R,0402,6.3V,-55-85ºC TDK
C1005XSR0J225K
CS0402
1
C7
1.0µF
CAP,CER,1.0µF,10%X5R,0402,6.3V,-55-85ºC GRM155R60J105KE19D GRM155R60J105KE19D
CS0402
TDK
C0603C0G1E6R8D030BA
CS0201
5
4
C15,C16,C23,C24
6.8pF
CAP,CER,6.8pF,0.5pF,NPO,0201,25V,-55125ºC
6
2
C17,C32
1.0pF
CAP,CER,1.0pF,0.1pF,NPO,0201,25V,-55125ºC
Murata
GRM0335C1E1R08A01J
CS0201
7
1
C21
DNI
CAP,CER,1.0pF,0.1pF,NPO,0201,25V,-55125ºC
Murata
GRM0335C1E1R08A01J
CS0201
8
2
R3,C22
DNI
CAP,CER,0.5pF,0.1pF,NPO,0201,25V,-55125ºC
Murata
500RGRM0335C1ER50BA0
CS0201
9
1
C33
0.7pF
CAP,CER,0.7pF,0.1pF,NPO,0201,25V,-55125ºC
Murata
500RGRM0335C1ER70BA01D07S0R5AV4
CS0201
T
10
2
E1
ANTENNA
11
3
FB1,FB2,FB3
BLM03AG121SN1
FERRITE,120Ω@100MHz,200mA,0201,-55125ºC
Murata
BLM03AG121SN1
FBS0201
12
1
L1
1µH
Power Inductor,1µH,20%,940mA,0.125Ω,0603,
Murata
shielded,-40-85ºC
LQM18PN1ROMFRL
LS0603
13
1
L2
0
Power Inductor,1µH,20%,940mA,0.125Ω,0603,
Murata
shielded,-40-85ºC
LQM18PN1ROMFRL
LS0603
14
1
L3
2.0nH
Inductor,2.0nH,0.2nH,Q=13@500MHz,SRF=8.1GHz, Taiyo Yuden
0201,-55-125ºC
HKQ0503S2NOC-T
RS0201
15
1
L5
15nH
Inductor,Multilayer,15nH,5%,350mA,Q=8@100MHz,0402
LQG15HS15NJ02D
LS0402
16
2
L8,L9
3.3nH
Inductor,3.3nH,0.2nH,Q=13@500MHz,SRF,=8.1GHz
Taiyo Yuden
,
0201,-55-125ºC
HKQ0603S3N3C-T
LS0201
17
1
R2
0.5pF
CAP,CER,0.5pF,0.1pF,NPO,0201,25V,-55125ºC
Murata
500RGRM0335C1ER50BA0
CS0201
19
1
R9
DNI
RESISTOR, Thick Film,0Ω,0201
Panasonic
ERJ-1GN0R00C
RS0201
20
10
R11,R16,R17,R18,R5,
0
R6,R8,R12,R13,R14
RESISTOR, Thick Film,0Ω,0201
Panasonic
ERJ-1GN0R00C
RS0201
21
2
R19,R20
4.7K
RESISTOR, Thick Film,4.7KΩ,0402
Vishay
CRCW0201-472J
RS0201
22
1
U1
ATWILC1000
IC,Wi-Fi,40QFN
Atmel
ATWILC1000
40QFN
26MHz
CRYSTAL,26MHz,CL=7,36pF,10ppm,-20-85ºC,
NDK
ESR=50,3.2x2.5mm
NX3225SA-26.000000MHZ-G3
3.2x2.5mm
Murata
18
23
1
Y1
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3
Notes on Interfacing to the ATWILC1000
3.1
Programmable Pull-up Resistors
The ATWILC1000 provides programmable pull-up resistors on various pins. The purpose of these resistors is
to keep any unused input pins from floating which can cause excess current to flow through the input buffer
from the VDDIO supply. Any unused module pin on the ATWILC1000 should leave these pull-up resistors
enabled so the pin will not float. The default state at power up is for the pull-up resistor to be enabled.
However, any pin which is used should have the pull-up resistor disabled. The reason for this is that if any pins
are driven to a low level while the ATWILC1000 is in the low power sleep state, current will flow from the
VDDIO supply through the pull-up resistors, increasing the current consumption of the module. Since the value
of the pull-up resistor is approximately 100KΩ, the current through any pull-up resistor that is being driven low
will be VDDIO/100K. For VDDIO = 3.3V, the current through each pull-up resistor that is driven low would be
approximately 3.3V/100KΩ = 33µA. Pins which are used and have had the programmable pull-up resistor
disabled should always be actively driven to either a high or low level and not be allowed to float.
See the ATWILC1000 Programming Guide for information on enabling/disabling the programmable pull up
resistors.
3.2
Restrictions for Power States
When no power supplied to the device, i.e., the DC/DC Converter output and VDDIO are both off (at ground
potential). In this case, a voltage cannot be applied to the device pins because each pin contains an ESD
diode from the pin to supply. This diode will turn on when voltage higher than one diode-drop is supplied to the
pin.
If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must
be on, so the SLEEP or Power_Down state must be used.
Similarly, to prevent the pin-to-ground diode from turning on, do not apply a voltage that is more than one
diode-drop below ground to any pin.
3.3
Power-up/-down Sequence
The power-up/-down sequence for ATWILC1000 is shown in Figure 3-1. The timing parameters are provided in
Table 3-1.
Figure 3-1.
Power Up/Down Sequence
VBATT
tA
t A'
VDDIO
tB
t B'
CHIP_EN
tC
RESETN
XO Clock
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t C'
Table 3-1.
Power-up/-down Sequence Timing
Parameter
Min.
Max.
Unit
Description
tA
0
VBATT rise to VDDIO rise
VBATT and VDDIO can rise simultaneously or
can be tied together. VDDIO must not rise before VBATT.
tB
0
VDDIO rise to CHIP_EN rise
CHIP_EN must not rise before VDDIO.
CHIP_EN must be driven high or low, not left
floating.
tC
5
CHIP_EN rise to RESETN rise
This delay is needed because XO clock must
stabilize before RESETN removal. RESETN
must be driven high or low, not left floating.
ms
3.4
Notes
tA’
0
VDDIO fall to VBATT fall
VBATT and VDDIO can fall simultaneously or
can be tied together. VBATT must not fall before VDDIO.
tB’
0
CHIP_EN fall to VDDIO fall
VDDIO must not fall before CHIP_EN.
CHIP_EN and RESETN can fall simultaneously.
tC’
0
RESETN fall to VDDIO fall
VDDIO must not fall before RESETN. RESETN
and CHIP_EN can fall simultaneously.
Digital I/O Pin Behavior During Power-up Sequences
Table 3-2 represents digital I/O Pin states corresponding to device power modes.
Table 3-2.
Digital I/O Pin Behavior in Different Device States
Device State
Input Driver
Pull-up/-down
Resistor
(96kΩ)
Disabled (Hi-Z)
Disabled
Disabled
Low
Disabled (Hi-Z)
Disabled
Enabled
High
High
Disabled (Hi-Z)
Enabled
Enabled
High
High
Programmed by
firmware for
each pin: Enabled or Disabled
Opposite of
Output
Driver state
Programmed
by firmware for
each pin: Enabled or Disabled
VDDIO
CHIP_EN
RESETN
Power Down:
core supply off
High
Low
Low
Power-On Reset:
core supply on, hard reset on
High
High
Power-On Default:
core supply on, device out of
reset but not programmed yet
High
On Sleep/
On Transmit/
On Receive:
core supply on, device programmed by firmware
High
Output Driver
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4
Placement and Routing Guidelines
It is critical to follow the recommendations listed below to achieve the best RF performance:
4.1

The board should have a solid ground plane. The center ground pad of the device must be solidly
connected to the ground plane by using a 3 x 3 grid of vias.

Keep away from antenna, as far as possible, large metal objects to avoid electromagnetic field blocking

Do not enclose the antenna within a metal shield

Keep any components which may radiate noise or signals within the 2.4GHz – 2.5GHz frequency band
far away from the antenna or better yet, shield those components. Any noise radiated from the main
board in this frequency band will degrade the sensitivity of the module.
Power and Ground
Dedicate one layer as a ground plane. Make sure that this ground plane does not get broken up by routes.
Power can route on all layers except the ground layer. Power supply routes should be heavy copper fill planes
to insure the lowest possible inductance. The power pins of the NMC1000 should have a via directly to the
power plane as close to the pin as possible. Decoupling capacitors should have a via right next to the capacitor
pin and this via should go directly down to the power plane – that is to say, the capacitor should not route to
the power plane through a long trace. The ground side of the decoupling capacitor should have a via right next
to the pad which goes directly down to the ground plane. Each decoupling capacitor should have its own via
directly to the ground plane and directly to the power plane right next to the pad. The decoupling capacitors
should be placed as close to the pin that it is filtering as possible.
4.2
RF Traces and Components
The RF traces that go from the ATWILC1000 tuner to the balun must be 50Ω differential controlled impedance.
These are pins 7 and 8 of the ATWILC1000. The route from the balun to the antenna connector must be a 50Ω
controlled impedance trace. These controlled impedance traces must reference a ground plane on a lower
layer. To achieve 50Ω impedance, a typical design might be 20 mil traces referenced to a ground plane on an
inner layer which is 10.7 mils below the traces. This must be adjusted depending on the dielectric and copper
weight used. No other traces must route through the RF area on layers between the RF traces and the ground
reference plane. In fact, try not to route any other traces in the RF area on any layer. This ground reference
plane must extend entirely under the tuner.
Be sure to add as many ground vias as possible, tying all ground layers together (ground stitching) all along
the RF traces and throughout the area where the RF traces are routed. Add at least two ground vias for every
ground pad around the RF components. Place ground vias all along the RF traces on either side.
Tie the center ground pad of the ATWILC1000 to the inner ground layer using a grid of 9 vias. The ground path
going from the ground pad down to the ground plane must be absolutely as low impedance as possible.
Do not use thermal relief pads for the ground pads of all components in the RF path. These component pads
must be completely filled in with ground copper.
Be sure to place the matching components and balun as close to the RFIOP and RFION pins as possible
(these C33, C23, C24, C17, C32, L8 and L9 in the reference schematic). Figure 4-1 shows the placement and
routing of these components. Note that they are placed as close as possible to the ATWILC1000’s pins 7 and
8. The components used for this design are 0201. Note that the width of the route matches the width of the
component pads. This will avoid impedance discontinuities which would occur if there is a large mismatch in
trace width versus the component pad size.
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Figure 4-1.
Placement and Routing of Balun and Matching Component
Be sure the route from the antenna to the ATWILC1000 is as short as possible and is completely isolated from
all other signals on the board. No signals should route under this trace on any layer of the board. Make sure
that all digital signals that may be toggling while the ATWILC1000 active are placed as far away from the
antenna as possible. No connectors which have digital signals going to them should be near the antenna. All
digital components and switching regulators on the board should be shielded so they do not radiate noise that
is picked up by the antenna.
In summary, make sure anything that switches is shielded and kept away from the antenna, the ATWILC1000
or the route from the ATWILC1000 to the antenna.
4.3
Sensitive Routes
4.3.1
Signals
The following signals are very sensitive to noise and you must take care to keep them as short as possible and
keep them isolated from all other signals by routing them far away from other traces or using ground to shield
them. Be sure that they are also isolated from noisy traces on the layers above them and below them:
XO_N
XO_P
RFIOP
RFION
4.3.2
Supplies
The following power supply pins for the ATWILC1000 are sensitive to noise and care should be taken to isolate
the routes to these pins from other noisy signals both on the same layer as the route and on layers above and
below. Use ground between these sensitive signals to isolate them from other signals. It is important that the
decoupling capacitors for these supplies are placed as close to the ATWILC1000 pin as possible. This is
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necessary to reduce the trace inductance between the capacitor and ATWILC1000 power pin to an absolute
minimum:
VDDRF_RX (pin 2)
VDDRF_TX (pin 4)
VDD_AMS (pin 3)
VDD_SXDIG (pin 37)
VDD_VCO (pin 38)
Additionally, while the VDDC (pins 14 and 27) and VBAT_BUCK (pin 20) supplies are not sensitive to picking
up noise, they are noise generating supplies. Therefore, be sure to keep the decoupling capacitors for these
supply pins as close as possible to the VDDC and VBAT_BUCK pins and make sure that the routes for these
supplies stay far away from sensitive pins and supplies.
4.4
Additional Suggestions
Make sure that traces route directly through the pads of all filter capacitors and not by way of a stub route.
The following routes are extremely critical and should be routed first. C) is a power route and should be a
heavy copper route. These routes must not have anything above, below or to the side of them except ground.
They must be as short as possible. Make sure that the filter capacitor for these pins is placed right next to the
pin.
A.
The 50Ω differential pair from NMC1000 pins 7 and 8 to the balun. Be sure this route is as short as
possible and that both routes of the differential pair are matched in length.
B.
The 50Ω unbalanced route from the balun to the antenna.
C.
The routes to the XO_P and XO_N pins (pins 35 and 36). These must be isolated with ground above,
below, and to the sides of the routes.
D.
The route from ATWILC1000 pin 21 (VSW) to the 15nH inductor (L5) must be as short and as wide as
possible. Make sure this inductor is placed right next to pin 21. The route from the other side of this
inductor to the 1.0uH inductor (L1) must also be as short and heavy as possible. Then the route from L1
to the 2.2µF capacitor (C10) and to pin 22 must also be as short and heavy as possible.
E.
The loop created from ATWILC1000 pin 21 through the inductors the capacitor and back to pin 22 must
be as small as possible.
F.
Make sure the ground return path from the 2.2µH capacitor connected to pin 22 back to the ground pad
of the ATWILC1000 is as short and wide as possible. This is critical. The ground return path must be
extremely low inductance. Failure to provide a short, heavy ground return between the capacitor and the
ATWILC1000 ground pad will result in incorrect operation of the on chip switching regulator.
Be sure to place the power supply decoupling capacitors so that there is a capacitor very close to each power
supply pin of the device. This requires making the copper as short and as wide as possible – use copper fills
for the power supply routing from the pins to the filter capacitors, not narrow traces.
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Interferers
One of the biggest problems with RF receivers is poor performance due to interferers on the board radiating
noise into the antenna or coupling into the RF traces going to input LNA. Care must be taken to make sure that
there is no noisy circuitry placed anywhere near the antenna or the RF traces. All noise generating circuits
should also be shielded so they do not radiate noise that is picked up by the antenna. Also, make sure that no
traces route underneath the RF portion of the ATWILC1000. Also, make sure that no traces route underneath
any of the RF traces from the antenna to the ATWILC1000 input. This applies to all layers. Even if there is a
ground plane on a layer between the RF route and another signal, the ground return current will flow on the
ground plane and couple into the RF traces.
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6
Thermal Considerations
Table 6-1 lists the thermal resistance from junction to ambient (JA) and from junction to case (JC) for 5x5 40L
QFN and WLCSP packages.
Table 6-1.
Thermal Resistance
Package
5x5mm 40L QFN
3.2x3.2mm 55L WLCSP
JA
JC
29.5ºC/W
3.9ºC/W
38ºC/W
n/a
Junction-to-ambient thermal resistance JA is a one-dimensional value that measures the conduction of heat
from the junction (hottest temperature on die) to the environment near the package. The heat that is generated
on the die surface reaches the immediate environment along two paths: (1) convection and radiation off the
exposed surface of the package and (2) conduction into and through the test board followed by convection and
radiation off the exposed board surfaces. JA reported here assumes the package is mounted on a board with
two signal layers and two internal planes (2s2p). JC for the WLCSP cannot be accurately given without
additional information: JC is the junction-to-case thermal resistance, where the case is defined at the exposed
pad surface. In order to use JC to estimate the thermal performance of the WLCSP package, the board must
be adhered to a metal housing or heat sink, and then a complete thermal analysis can be done.
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Antenna
Make sure to choose an antenna that covers the proper frequency band, 2.400GHz to 2.500GHz. Talk to the
antenna vendor and make sure he understands the full frequency range that must be covered by the antenna.
Make sure the antenna is designed for a 50Ω system.
Make sure the PCB pad that the antenna is connected to is properly designed for 50Ω impedance. This is
extremely important. The antenna vendor must specify the pad dimensions, the spacing from the pad to the
ground reference plane, and the spacing from the edges of the pad to the ground fill on the same layer as the
pad. Also, since the ground reference plane for the 50 trace going from the antenna pad to the ATWILC1000
will probably be on a different layer than the ground reference for the antenna pad, make sure the pad design
has a proper transition from the pad to the 50Ω trace.
Make sure that the antenna matching components are placed as close to the antenna pad as possible. The
antenna cannot be properly matched if the matching components are far away from the antenna.
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8
External Interfaces
8.1
General
ATWILC1000A external interfaces include I2C Slave for control, SPI Slave and SDIO Slave for control and data
transfer, SPI Master for external Flash, I2C Master for external EEPROM, UART for debug, control, and data
transfer, General Purpose Input/output (GPIO) pins, and a Wi-Fi/Bluetooth® coexistence interface. With the
exception of the SPI Slave and SDIO Slave host interfaces, which are selected using the dedicated
SDIO_SPI_CFG pin, the other interfaces can be assigned to various pins by programming the corresponding
pin muxing control register for each pin to a specific value between 0 and 6.The default values of these
registers are 0, which is GPIO mode. The summary of the available interfaces and their corresponding pin mux
settings is shown in Table 8-1. For specific programming instructions, refer to ATWILC1000A Programming
Guide.
Table 8-1.
Pin-MUX Matrix of External Interfaces
Digital Pad Characteristics are given in Table 8-2.
Table 8-2.
Symbol
Characteristics
Min.
Typ.
Max.
VDDIOL(2)
I/O Supply Voltage Low-Range
1.62
1.80
2.00
VDDIOM(2)
I/O Supply Voltage Mid-Range
2.00
2.50
3.00
VDDIOH(2)
I/O Supply Voltage High-Range
3.00
3.30
3.60
VBATT(3)
Battery Supply Voltage
2.5(4)
3.6
4.2
Operating Temperature
-30
Notes:
14
Digital Pad Characteristics
1.
2.
3.
4.
Unit
V
85
ºC
Refer to Datasheet for details of power connections.
I/O supply voltage is applied to the following pins: VDDIO_A, VDDIO_0, and VDDIO_1.
Battery supply voltage is applied to following pins: VDDBATT_PPA/PA, VBATT_BUCK.
Device is functional across this range of voltages; however, optimal RF performance is guaranteed for VBATT
in the range 3.0V < VBATT < 4.2V.
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Table 8-3.
??????
VDDIO Condition
Characteristic
Min.
Max.
Input Low Voltage VIL
-0.30
0.60
Input High Voltage VIH
VDDIO-0.60
VDDIO+0.30
Unit
V
Output Low Voltage VOL
0.45
VDDIOL
Output High Voltage VOH
VDDIO-0.50
I2C Pad Drive Strength(1)
4
All other Digital Pad Drive Strength
2
mA
Input Low Voltage VIL
-0.30
0.63
Input High Voltage VIH
VDDIO-0.60
VDDIO+0.30
V
Output Low Voltage VOL
0.45
VDDIOM
Output High Voltage VOH
I2 C
Pad Drive
VDDIO-0.50
Strength(1)
8
mA
All other Digital Pad Drive Strength
4
Input Low Voltage VIL
-0.30
0.65
Input High Voltage VIH
VDDIO-0.60
VDDIO+0.30 (up to 3.60)
V
Output Low Voltage VOL
0.45
VDDIOH
Output High Voltage VOH
VDDIO-0.50
I2C Pad Drive Strength(1)
12
All other Digital Pad Drive Strength
6
mA
Output Loading
20
Digital Input Load
6
All
Note:
8.2
pF
1.
I2C Pad Drive Strength applies to the following pins: I2C_SDA, I2C_SCL.
I2C Slave Interface
The I2C Slave interface, used primarily for control by the host processor, is a two-wire serial interface
consisting of a serial data line (SDA, Pin 33) and a serial clock (SCL, Pin 32). It responds to the seven bit
address value 0x60. The ATWILC1000A I2C supports I2C bus Version 2.1 - 2000 and can operate in standard
mode (with data rates up to 100Kb/s) and fast mode (with data rates up to 400Kb/s).
The I2C Slave is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while
the SCL line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain to
perform wire-AND functions on the bus. The maximum number of devices on the bus is limited by only the
maximum capacitance specification of 400pF. Data is transmitted in byte packages.
For specific information, refer to the Philips Specification entitled “The I2C -Bus Specification, Version 2.1”.
The I2C Slave timing is provided in Figure 8-1 and Table 8-4.
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Figure 8-1.
I2C Slave Timing Diagram
tPR
tSUDAT
tHDDAT
tBUF
tSUSTO
SDA
tHL
tLH
tWL
SCL
tLH
tHDSTA
tHL
tWH
tPR
tPR
fSCL
Table 8-4.
tSUSTA
I2C Slave Timing Parameters
Parameter
Symbol
Min.
Max.
Unit
400
kHz
SCL Clock Frequency
fSCL
0
SCL Low Pulse Width
tWL
1.3
SCL High Pulse Width
tWH
0.6
SCL, SDA Fall Time
tHL
300
SCL, SDA Rise Time
tLH
300
START Setup Time
tSUSTA
0.6
START Hold Time
tHDSTA
0.6
SDA Setup Time
tSUDAT
100
SDA Hold Time
tHDDAT
0
40
STOP Setup time
tSUSTO
0.6
Bus Free Time Between STOP and START
tBUF
1.3
Glitch Pulse Reject
tPR
0
Remarks
µs
ns
This is dictated by external
components
µs
ns
Slave and Master Default
Master Programming Option
µs
8.3
50
ns
I2C Master Interface
ATWILC1000A provides an I2C bus master, which is intended primarily for accessing an external EEPROM
memory through a software-defined protocol. The I2C Master is a two-wire serial interface consisting of a serial
data line (SDA) and a serial clock line (SCL). SDA can be configured on one of the following pins: GPIO1 (pin
24), GPIO6 (pin 31), or I2C_SDA (pin 33). SCL can be configured on one of the following pins: GPIO0 (pin 10),
GPIO4 (pin 29), or I2C_SCL (pin 32). For more specific instructions, refer to ATWILC1000A Programming
Guide.
The I2C Master interface supports three speeds:
16

Standard mode (100kb/s)

Fast mode (400kb/s)

High-speed mode (3.4Mb/s)
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The timing diagram of the I2C Master interface is the same as that of the I2C Slave interface (see Figure 8-1).
The timing parameters of I2C Master are shown in Table 8-5.
Table 8-5.
I2C Master Timing Parameters
Standard Mode
Parameter
Fast Mode
High-speed Mode
Symbol
Unit
Min.
Max.
Min.
Max.
Min.
Max.
100
0
400
0
3400
SCL Clock Frequency
fSCL
0
SCL Low Pulse Width
tWL
4.7
1.3
0.16
SCL High Pulse Width
tWH
4
0.6
0.06
SCL Fall Time
tHLSCL
300
300
10
40
SDA Fall Time
tHLSDA
300
300
10
80
SCL Rise Time
tLHSCL
1000
300
10
40
SDA Rise Time
tLHSDA
1000
300
10
80
START Setup Time
tSUSTA
4.7
0.6
0.16
START Hold Time
tHDSTA
4
0.6
0.16
SDA Setup Time
tSUDAT
250
100
10
SDA Hold Time
tHDDAT
5
40
0
STOP Setup time
tSUSTO
4
0.6
0.16
Bus Free Time Between STOP
and START
tBUF
4.7
1.3
Glitch Pulse Reject
tPR
kHz
µs
ns
µs
ns
8.4
70
µs
0
50
ns
SPI Slave Interface
ATWILC1000A provides a Serial Peripheral Interface (SPI) that operates as a SPI slave. The SPI Slave
interface can be used for control and for serial I/O of 802.11 data. The SPI Slave pins are mapped as shown in
Table 8-6. The RXD pin is same as Master Output, Slave Input (MOSI), and the TXD pin is same as Master
Input, Slave Output (MISO). The SPI Slave is a full-duplex slave-synchronous serial interface that is available
immediately following reset when pin 9 (SDIO_SPI_CFG) is tied to VDDIO.
Table 8-6.
Pin #
SPI Slave Interface Pin Mapping
SPI Function
9
CFG: Must be tied to VDDIO
16
SSN: Active Low Slave Select
18
SCK: Serial Clock
13
RXD: Serial Data Receive (MOSI)
17
TXD: Serial Data Transmit (MISO)
When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers
between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted
data output is buffered, resulting in a high impedance drive onto the serial master receive line.
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The SPI Slave interface responds to a protocol that allows an external host to read or write any register in the
chip as well as initiate DMA transfers. For the details of the SPI protocol and more specific instructions, refer to
ATWILC1000A Programming Guide.
The SPI Slave interface supports four standard modes as determined by the Clock Polarity (CPOL) and Clock
Phase (CPHA) settings. These modes are illustrated in Table 8-7 and Figure 8-2. The red lines in Figure 8-2
correspond to Clock Phase = 0 and the blue lines correspond to Clock Phase = 1.
Table 8-7.
SPI Slave Modes
Mode
CPOL
CPHA
0
0
0
1
0
1
2
1
0
3
1
1
Figure 8-2.
SPI Slave Clock Polarity and Clock Phase Timing
CPOL = 0
SCK
CPOL = 1
SSN
CPHA = 0
RXD/TXD
(MOSI/MISO)
CPHA = 1
z
1
z
2
1
3
2
4
3
The SPI Slave timing is provided in Figure 8-3 and Table 8-8.
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5
4
6
5
7
6
8
7
z
8
z
Figure 8-3.
SPI Slave Timing Diagram
Table 8-8.
SPI Slave Timing Parameters
Parameter
8.5
Symbol
Min.
Max.
Unit
48
MHz
Clock Input Frequency
fSCK
Clock Low Pulse Width
tWL
15
Clock High Pulse Width
tWH
15
Clock Rise Time
tLH
10
Clock Fall Time
tHL
10
Input Setup Time
tISU
5
Input Hold Time
tIHD
5
Output Delay
tODLY
0
Slave Select Setup Time
tSUSSN
5
Slave Select Hold Time
tHDSSN
5
ns
20
SPI Master Interface
ATWILC1000A provides a SPI Master interface for accessing external flash memory. The SPI Master pins are
mapped as shown in Table 8-9. The TXD pin is same as Master Output, Slave Input (MOSI), and the RXD pin
is same as Master Input, Slave Output (MISO). The SPI Master interface supports all four standard modes of
clock polarity and clock phase shown in Table 8-7. External SPI flash memory is accessed by a processor
programming commands to the SPI Master interface, which in turn initiates a SPI master access to the flash.
For more specific instructions, refer to ATWILC1000A Programming Guide.
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Table 8-9.
SPI Master Interface Pin Mapping
Pin #
Pin Name
SPI Function
28
GPIO3
SCK: Serial Clock Output
29
GPIO4
SCK: Active Low Slave Select Output
30
GPIO5
TXD: Serial Data Transmit Output (MOSI)
31
GPIO6
RXD: Serial Data Receive Input (MISO)
The SPI Master timing is provided in Figure 8-4 and Table 8-10.
Figure 8-4.
SPI Master Timing Diagram
fSCK
tLH
tWH
tWL
SCK
tHL
SSN,
TXD
tODLY
tISU
tIHD
RXD
Table 8-10.
SPI Master Timing Parameters
Parameter
8.5.1
Symbol
Min.
Max.
Unit
48
MHz
Clock Output Frequency
fSCK
Clock Low Pulse Width
tWL
5
Clock High Pulse Width
tWH
5
Clock Rise Time
tLH
5
Clock Fall Time
tHL
5
Input Setup Time
tISU
5
Input Hold Time
tIHD
5
Output Delay
tODLY
0
ns
5
SPI PCB Trace Constraints
In general, the SPI PCB trace layout must ensure that the total capacitance (trace and load of other pin) on the
SPI lines (SPI_RXD, SPI_SSN, SPI_TXD, and SPI_SCK) are less than the maximum pin capacitance of 20pF
(see Table 8-3). As this is heavily dependent on the board type and lithography, no single constraint of trace
length can be given. It is, however, preferable to minimize the trace length as much as possible. For further
guidance, consult your Atmel FAE. Be sure to have all information on the application PCB layout design rules.
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8.6
SDIO Slave Interface
The ATWILC1000A SDIO Slave is a full speed interface. The interface supports the 1-bit/4-bit SD transfer
mode at the clock range of 0 - 50MHz. The Host can use this interface to read and write from any register
within the chip as well as configure the ATWILC1000A for data DMA. To use this interface, pin 9
(SDIO_SPI_CFG) must be grounded. The SDIO Slave pins are mapped as shown in Table 8-11.
Table 8-11.
SDIO Interface Pin Mapping
Pin #
SPI Function
9
CFG: Must be tied to ground
12
DAT3: Data 3
13
DAT2: Data 2
16
DAT1: Data 1
17
DAT0: Data 0
18
CMD: Command
19
CLK: Clock
When the SDIO card is inserted into an SDIO aware host, the detection of the card will be via the means
described in SDIO specification. During the normal initialization and interrogation of the card by the host, the
card will identify itself as an SDIO device. The host software will obtain the card information in a tuple (linked
list) format and determine if that card’s I/O function(s) are acceptable to activate. If the card is acceptable, it will
be allowed to power up fully and start the I/O function(s) built into it.
The SD memory card communication is based on an advanced 9-pin interface (Clock, Command, 4 Data and 3
Power lines) designed to operate at maximum operating frequency of 50MHz.
The SDIO Slave interface has the following features:

Meets SDIO card specification version 2.0.

Host clock rate variable between 0 and 50MHz

1 bit/4-bit SD bus modes supported

Allows card to interrupt host

Responds to Direct read/write (IO52) and Extended read/write (IO53) transactions.

Supports Suspend/Resume operation.
The SDIO Slave interface timing is provided in Figure 8-5 and Table 8-12.
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Figure 8-5.
SDIO Slave Timing Diagram
fpp
tWL
SD_CLK
tHL
tWH
tLH
tISU
tIH
Inputs
tODLY(MAX)
tODLY(MIN)
Outputs
Table 8-12.
SDIO Slave Timing Parameters
Parameter
8.6.1
Symbol
Min.
Max.
Unit
50
MHz
Clock Input Frequency
fPP
0
Clock Low Pulse Width
tWL
10
Clock High Pulse Width
tWH
10
Clock Rise Time
tLH
10
Clock Fall Time
tHL
10
Input Setup Time
tISU
5
Input Hold Time
tIH
5
Output Delay
tODLY
0
ns
14
SDIO PCB Trace Constraints
In general, the SDIO PCB trace layout must ensure that the total capacitance (trace and load of other pin) on
the SDIO lines (SD_DAT0, SD_DAT1, SD_DAT2, SD_DAT3, SD_CLK, SD_CMD) are less than the maximum
pin capacitance of 20pF (see Table 8-3). As this is heavily dependent on the board type and lithography, no
single constraint of trace length can be given. It is, however, imperative to minimize the trace length as much
as possible to ensure maximum interface throughput. For further guidance, consult your Atmel FAE. Be sure to
have all information on the application PCB layout design rules.
8.7
UART
ATWILC1000A has a Universal Asynchronous Receiver/Transmitter (UART) interface for serial
communication. It is intended primarily for debugging, and it can also be used for control or data transfer if the
baud rate is sufficient for a given application. The UART is compatible with the RS-232 standard, where
ATWILC1000A operates as Data Terminal Equipment (DTE). It has a two-pin RXD/TXD interface, where RXD
can be enabled on one of four alternative pins and TXD can be enabled on one of three alternative pins by
programming their corresponding pin MUX control registers to 3 (see Table 8-1).
The UART features programmable baud rate generation with fractional clock division, which allows
transmission and reception at a wide variety of standard and non-standard baud rates. The UART input clock is
selectable between 10MHz, 5MHz, 2.5MHz, and 1.25MHz. The clock divider value is programmable as 13
integer bits and three fractional bits (with 8.0 being the smallest recommended value for normal operation).
This results in the maximum supported baud rate of 10MHz / 8.0 = 1.25MBd.
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The UART can be configured for seven or eight bit operation, with or without parity, with four different parity
types (odd, even, mark, or space), and with one or two stop bits. It also has Rx and Tx FIFOs, which ensure
reliable high speed reception and low software overhead transmission. FIFO size is 4 x 8 for both Rx and Tx
direction. The UART also has status registers showing the number of received characters available in the FIFO
and various error conditions, as well the ability to generate interrupts based on these status bits.
An example of UART receiving or transmitting a single packet is shown in Figure 8-6. This example shows 7-bit
data (0x45), odd parity, and two stop bits.
For more specific instructions, refer to ATWILC1000A Programming Guide.
Figure 8-6.
8.8
Example of UART Rx or Tx packet
Wi-Fi/Bluetooth Coexistence
ATWILC1000A supports 2- and 3-wire Wi-Fi/Bluetooth Coexistence signaling conforming to the IEEE®
802.15.2-2003 standard, Part 15.2. The type of coexistence interface used (2- or 3-wire) is chosen to be
compatible with the specific Bluetooth device used in a given application. Table 8-13 shows a usage example
of the 2-wire interface using the GPIO3 and GPIO4 pins; 3-wire interface using the GPIO3, GPIO4, and GPIO5
pins; for more specific instructions on configuring Coexistence, refer to ATWILC1000A Programming Guide.
Table 8-13.
8.9
Coexistence Pin Assignment Example
Pin Name
Function
GPIO3
BT_Req
GPIO4
Target
Pin #
2-wire
3-wire
BT is requesting to access the medium to transmit
or receive. Goes high on TX or RX slot
28
Used
Used
BT_Pri
Priority of the BT packets in the requested slot.
High to indicate high priority and low for normal.
29
Not Used
Used
GPIO5
WL_Act
Device response to the BT request.
High - BT_req is denied and BT slot blocked.
30
Used
Used
GPIO6
Ant_SW
Direct control on Antenna (coax bypass)
31
Optional
Optional
GPIOs
Nine General Purpose Input/output (GPIO) pins, labeled GPIO 0-8, are available to allow for application
specific functions. Each GPIO pin can be programmed as an input (the value of the pin can be read by the host
or internal processor) or as an output (the output values can be programmed by the host or internal processor),
where the default mode after power-up is input. GPIOs 7 and 8 are only available when the host does not use
the SDIO interface, which shares two of its pins with these GPIOs. Therefore, for SDIO-based applications,
seven GPIOs (0-6) are available. For more specific usage instructions, refer to ATWILC1000A Programming
Guide.
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FCC, TELEC, ETSI Compliance
The reference design provided is compliant with FCC, TELEC, and ETSI regulations. No Calibrations are
needed by the device maker if the 26MHz crystal used meets the 802.11 requirements (±20ppm). For crystals
variations outside this range, consult your Atmel FAE.
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Reference Documentation and Support
10.1
Reference Documents
Atmel offers a set of collateral documentation to ease integration and device ramp.
Table 10-1 shows a list of documents available on the Atmel web or integrated into development tools.
Table 10-1.
Reference Documents
Title
Content
Datasheet
Design Files
User Guide, Schematic, PCB layout, Gerber, BOM and
System notes on: RF/Radio Full Test Report, radiation pattern, design guide-lines, temperature performance, ESD.
Package
How to use package: Out of the Box starting guide, HW limitations and notes, SW Quick
start guidelines
Platform Getting started
Guide
This document
HW Design Guide
Integration guide with clear description of: High level Arch, overview on how to write a
networking application, list all API, parameters and structures.
Features of the device, SPI/handshake protocol between device and host MCU, with
flow/sequence/state diagram, timing.
SW Design Guide
Explain in details the flow chart and how to use each API to implement all generic use
cases (e.g. start AP, start STA, provisioning, UDP, TCP, http, TLS, p2p, errors management, connection/transfer recovery mechanism/state diagram) - usage and sample application note.
For a complete listing of development-support tools and documentation, visit http://www.atmel.com/ or contact
the nearest Atmel field representative.
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Revision History
Doc Rev.
Date
42431A
03/2015
Comments
Initial document release.
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