PIC16(L)F1512/1513 PIC16(L)F1512/1513 Family Silicon Errata and Data Sheet Clarification The PIC16(L)F1512/1513 family devices that you have received conform functionally to the current Device Data Sheet (DS40001624C), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with a hardware debugger: 1. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. 2. 3. The errata described in this document will be addressed in future revisions of the PIC16(L)F1512/1513 silicon. 4. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (A3). Data Sheet clarifications and corrections start on page 5, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip’s programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: 5. Using the appropriate interface, connect the device to the hardware debugger. Open an MPLAB IDE project. Configure the MPLAB IDE project for the appropriate device and hardware debugger. Based on the version of MPLAB IDE you are using, do one of the following: a) For MPLAB IDE 8, select Programmer > Reconnect. b) For MPLAB X IDE, select Window > Dashboard and click the Refresh Debug Tool Status icon ( ). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC16(L)F1512/ 1513 silicon revisions are shown in Table 1. SILICON DEVREV VALUES DEVICE ID<13:0>(1),(2) Part Number REV<4:0> Silicon Revision DEV<8:0> A1 A2 A3 PIC16F1512 01 0111 000 0 0001 0 0010 0 0011 PIC16LF1512 01 0111 001 0 0001 0 0010 0 0011 PIC16F1513 01 0110 010 0 0001 0 0010 0 0011 PIC16LF1513 01 0111 010 0 0001 0 0010 0 0011 Note 1: 2: The Device ID is located in the configuration memory at address 8006h. Refer to the “PIC16(L)F151X/152X Memory Programming Specification” (DS41442) for detailed information on Device and Revision IDs for your specific device. 2012-2016 Microchip Technology Inc. DS80000543D-page 1 PIC16(L)F1512/1513 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A1 Oscillator Clock Switching 1.1 Clock switching can cause a single corrupted instruction. X Oscillator Oscillator Start-up Timer (OST) bit 1.2 OST bit remains set. X ADC ADOUT Function 2.1 ADOEN bit issue during ADOUT function. X ADC Automated CVD 2.2 Cannot run back-to-back conversions using FRC. X ADC TRIS Control during conversions 2.3 No auto TRIS control, must be done manually. X Program Flash Memory (PFM) PFM Self-Write 3.1 PFM self-write will not work depending on clock selection. Fixed Voltage Reference (FVR) Gain Amplifier Output 4.1 Use of FVR module can cause device Reset. X Fixed Voltage Reference (FVR) FVR Output Levels 4.2 Large errors are possible. X Fixed Voltage Reference (FVR) ADC Conversion 4.3 First conversion of FVR signal may contain errors. X Note 1: A2 A3 X X X X X X Only those issues indicated in the last column apply to the current silicon revision. DS80000543D-page 2 2012-2016 Microchip Technology Inc. PIC16(L)F1512/1513 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A3). 1. Module: Oscillator 1.1 Clock Switching When switching clock sources between INTOSC clock source and an external clock source, one corrupted instruction may be executed after the switch occurs. When switching from an external oscillator clock source, first switch to 16 MHz HFINTOSC. Once running at 16 MHz HFINTOSC, configure IRCF to run at desired internal oscillator frequency. When switching from an internal oscillator (INTOSC) to an external oscillator clock source, first switch to HFINTOSC High-Power mode (16 MHz). Once running from HFINTOSC, switch to the external oscillator clock source. Affected Silicon Revisions A2 2.1 ADOEN Bit Issue During ADOUT Function To operate the ADC during the pre-charge stage of conversion as stated in the data sheet, the ADOUT output-override must be disabled (ADOOEN = 0) when the ADOUT pin is not connected to the ADC conversion bus (ADOEN/ADOLEN = 0). Likewise, the ADOUT output-override should be enabled (ADOOEN = 1) when ADOUT is enabled (ADOEN/ ADOLEN = 1). Work around Stated above. Affected Silicon Revisions A1 Work around A1 2. Module: ADC A3 X 1.2 Oscillator Start-up Timer (OST) bit During the Two-Speed Start-up sequence, the OST is enabled to count 1024 clock cycles. After the count is reached, the OSTS bit is set, the system clock is held low until the next falling edge of the external crystal (LP, XT or HS mode), before switching to the external clock source. When an external oscillator is configured as the primary clock and Fail-Safe Clock mode is enabled (FCMEN = 1), any of the following conditions will result in the Oscillator Start-up Timer (OST) failing to restart: • MCLR Reset • Wake from Sleep • Clock change from INTOSC to Primary Clock This anomaly will manifest itself as a clock failure condition for external oscillators which take longer than the clock failure time-out period to start. A2 A3 X 2.2 Automated CVD The double conversion procedure for the ADC is activated by setting the ADDSEN bit in the AADCON3 register. Double conversions do not work reliably if the FRC is selected as the ADC clock source. This is true whether or not the part is in Sleep mode. Single conversions can be performed, in Sleep mode or not, with the FRC selected. Work around Do not run double conversions with the FRC selected as the clock for the ADC. Affected Silicon Revisions A1 A2 A3 X X X 2.3 TRIS Control During Conversions When running conversions using the acquisition timer feature, the TRIS control for the selected analog pin will not be automatically set to ‘1’ if its current value is ‘0’. This will cause the charge on the ADC hold capacitor to be driven to VSS or VDD. However, if the selected analog pin’s current TRIS value is ‘1’, the pre-charge timer will correctly override it to an output during the pre-charge stage. Work around None. Set the TRIS bit (TRISx = 1) to configure the pin as a digital input before starting the ADC conversion. When the conversion completes, the TRIS bit can be cleared (TRISx = 0) to return the pin as a digital output. Affected Silicon Revisions Affected Silicon Revisions Work around A1 A2 A3 X 2012-2016 Microchip Technology Inc. A1 A2 A3 X DS80000543D-page 3 PIC16(L)F1512/1513 3. Module: Program Flash Memory (PFM) 4.3 ADC Conversion Writes to the PFM will not execute if the device’s clock source is HS or ECH, or if the internal oscillator is at 16 MHz. When using the ADC to sample the output of the FVR, the first conversion result may contain errors. This can occur particularly if both the FVR and ADC modules have been powered down for significant time prior to the conversion. Work around Work around To write to the PFM, the clock source must have one of the following settings: internal oscillator set to 8 MHz or lower, ECM, ECL, XT, External RC, LP or T1OSC. Method 1: 3.1 PFM Self-Write Affected Silicon Revisions A1 A2 A3 X 4. Module: Fixed Voltage Reference (FVR) 4.1 Gain Amplifier Output When using the FVR module, if the gain amplifier outputs are set via the CDAFVR or ADFVR bits in FVRCON, while the module is disabled (FVREN = 0), the internal oscillator frequency may shift, device current consumption can increase, and a Brown-out Reset may occur. Work around Affected Silicon Revisions A2 X X a) Enable ADC with sample path set to VREFL (Vss); Enable FVR with ADFVR bits set to zero; Configure FVR gain to the desired level per data sheet instructions; Allow time for FVR stabilization and poll for FVRRDY = 1; Configure ADC sample path to FVR and required ADC acquisition time allowed; Initiate the ADC conversion. b) c) d) e) f) Set the FVREN bit of FVRCON to enable the module prior to adjusting the amplifier output selections with the CDAFVR and ADFVR bits. If switching from the 4x output setting to the 1x output setting, select the 2x output setting as an intermediary step. Always set the amplifier output selections to off (’00’) before disabling the FVR module. A1 Prior to the conversion, provide ‘FVR Stabilization Period’ per the graph provided in the Electrical Specification chapter of the data sheet. As shown in this graph, this stabilization time is typically in the range 25 to 30 µs. During this stabilization time, the ADC should be enabled and set to sample the VREFL (VSS) node. The following steps should be followed: A3 4.2 FVR Output Levels Method 2: Alternately, the FVR and ADC modules can be enabled and a series of ADC conversions of the sampled FVR output performed while both modules remain active. In this case, the first conversion result should be discarded and the subsequent results utilized. It is noted that this approach, in effect, provides for the stabilization time referred to above. Affected Silicon Revisions A1 A2 A3 X X X The output levels of the FVR are likely to contain large errors that can exceed 30% of the 1.024/ 2.048/4.096V target levels stated in the Electrical Specifications section of the data sheet. Work around None. Affected Silicon Revisions A1 A2 A3 X DS80000543D-page 4 2012-2016 Microchip Technology Inc. PIC16(L)F1512/1513 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS40001624C): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. None. 2012-2016 Microchip Technology Inc. DS80000543D-page 5 PIC16(L)F1512/1513 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (03/2012) Initial release of this document. Rev B Document (08/2012) Added MPLAB X IDE; Added Silicon Revision A2; Updated Modules 1.2 and 2.2; Added Module 3, Program Flash Memory, and Module 4, Fixed Voltage Reference. Data Sheet Clarifications: Added Module 1, Electrical Specifications. Rev C Document (03/2014) Added Silicon Revision A3; Other minor corrections. Data Sheet Clarification: Removed Module 1. Rev D Document (06/2016) Silicon Errata Issues: Added Section 4.3 – ADC Conversion. Other minor corrections. DS80000543D-page 6 2012-2016 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2012-2016 Microchip Technology Inc. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2012-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. 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