PIC16F570 Memory Programming Specification

PIC16F570
PIC16F570 Memory Programming Specification
1.1
This document includes the programming specifications
for the following devices:
Hardware Requirements
• PIC16F570
The PIC16F570 requires one power supply for VDD
(5.0V) and one for VPP (12.5V).
1.0
1.2
PROGRAMMING THE
PIC16F570
The Program/Verify mode for the PIC16F570 allows
programming of user program memory, user ID
locations, backup OSCCAL location and the
Configuration Word.
The PIC16F570 is programmed using a serial method.
The Serial mode will allow the PIC16F570 to be
programmed while it is in the user’s system. This allows
for increased design flexibility. This programming
specification applies to the PIC16F570 devices in all
packages.
FIGURE 1-1:
Program/Verify Mode
28-PIN DIAGRAM FOR PIC16F570
SPDIP, SOIC, SSOP
MCLR/VPP
1
RA0
2
3
RA1
RB7/ICSPDAT
26
25
RB5
24
RB3
23
RB2
22
RB1
21
RB0
20
VDD
RB6/ICSPCLK
RB4
RA4
6
RA5
7
VSS
8
RA7
9
RA6
10
19
VSS
RC0
18
17
RC7
RC1
11
12
RC2
13
16
RC5
RC3
14
15
RC4
PIC16F570
RA3
4
5
RA2
 2012 Microchip Technology Inc.
28
27
RC6
Preliminary
DS41670A-page 1
PIC16F570
FIGURE 1-2:
28-PIN DIAGRAM FOR PIC16F570
28
27
26
25
24
23
22
RA1
RA0
MCLR/VPP
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
QFN
8
9
10
11
12
13
14
PIC16F570
TABLE 1-1:
21
20
19
18
17
16
15
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC1
RC2
RC3
RC4
RC5
RC6
1
2
3
4
5
6
7
RC0
RA2
RA3
RA4
RA5
VSS
RA7
RA6
PIN DESCRIPTIONS DURING PROGRAMMING
During Programming
Pin Name
Function
Pin Type
Pin Description
RB6
ICSPCLK
I
RB7
ICSPDAT
I/O
Data input/output – Schmitt Trigger input
Program/Verify mode
P(1)
Programming Power
VDD
VDD
P
Power Supply
VSS
VSS
P
Ground
MCLR/VPP
Clock input – Schmitt Trigger input
Legend: I = Input, O = Output, P = Power
Note 1: The programming high voltage is internally generated. To activate the Program/Verify mode, a high voltage
with the current capability listed as IIHH in Table 6-1 needs to be applied to the MCLR input.
DS41670A-page 2
Preliminary
 2012 Microchip Technology Inc.
PIC16F570
2.0
MEMORY MAPPING
2.2
The program memory map of the PIC16F570 device is
shown in Figure 2-1. In Program/Verify mode, the
program memory extends from 0x000 to 0xFFF.
FIGURE 2-1:
MEMORY MAP
User Memory
Space
On-chip User
Program
Memory (Page 0)
On-chip User
Program
Memory (Page 1)
On-chip User
Program
Memory (Page 2)
Data Memory
Space
On-chip User
Program
Memory (Page 3)
Reset Vector
Configuration Memory
Space
Backup OSCCAL
Locations
The data memory space is the self-writable Flash data
memory block and is located at addresses PC = 800h83Fh. All program mode commands that work on
normal Flash memory work on the self-writable Flash
data memory block. This includes Bulk Erase, Load
and Read Data commands.
2.3
3FFh
400h
2.3.1
5FFh
600h
7FEh
7FFh
800h
83Fh
840h
843h
844h
847h
848h
2.3.2
CONFIGURATION WORD
The Configuration Word is physically located at 0xFFF.
It is only available upon Program mode entry. Once an
Increment Address command is issued, the
Configuration Word is no longer accessible, regardless
of the address of the Program Counter.
8AFh
8B0h
Note:
Unimplemented
FFEh
FFFh
User Memory
The user memory space is the on-chip user program
memory. As shown in Figure 2-1, it extends from 0x000
to 0x7FF and partitions into pages, including the Reset
vector, at address 0x7FF, and the Interrupt vector, at
address 0x004. Note that the Program Counter (PC)
will increment from (0x000-0x7FF) then to 0x800, (not
to 0x000).
 2012 Microchip Technology Inc.
USER ID LOCATIONS
A user may store identification information (ID) in four
user ID locations. The user ID locations are mapped in
[0x840:0x843]. It is recommended that users use only
the four Least Significant bits (LSb) of each user ID
location and program the upper eight bits as ‘1’s. The
user ID locations read out normally, even after code
protection is enabled. It is recommended that the user
ID location is written as ‘1111 1111 bbbb’, where
‘bbbb’ is the user ID information.
Reserved
Configuration Word
Configuration Memory
The configuration memory space extends from 0x840
to 0xFFF. Locations from 0x848 through 0x8AF are
reserved. The user ID locations extend from 0x840
through 0x843. The Configuration Word is physically
located at 0xFFF, and the backup OSCCAL locations
extend from 0x844 through 0x847.
1FFh
200h
Self-writable
Flash Data Memory
User ID Locations
2.1
000h
Data Memory
Preliminary
By convention, the Configuration Word is
stored at the logical address location of
0xFFF within the hex file generated for the
PIC16F570. This logical address location
may not reflect the actual physical
address for the part itself. It is the
responsibility
of the programming
software to retrieve the Configuration
Word from the logical address within the
hex file and granulate the address to the
proper
physical
location
when
programming.
DS41670A-page 3
PIC16F570
2.4
Oscillator Calibration Bits
During factory testing of the device, the internal oscillator is tested and calibrated. A unique calibration value
is determined for the device and is stored within a
MOVLW instruction as the operand. This MOVLW instruction is then stored at the reset vector address location,
0x7FF. After a reset of the device, the unique calibration value is moved into the working register (W). It is
the user’s responsibility to restore the calibration value
to the OSCCAL register using a MOVWF instruction.
Programming interfaces must allow users to program
the calibration bits themselves for custom trimming of
the INTOSC. Capability for programming the
calibration bits when programming the entire memory
array must also be maintained for backwards
compatibility.
2.4.1
BACKUP OSCCAL VALUE
A backup copy of the MOVLW instruction, with the
unique calibration value as the operand, is also stored
in the first backup OSCCAL address location at 0x844.
The remaining backup OSCCAL locations, 0x8450x847, can be used to store additional copies of this
instruction.
The backup OSCCAL value locations, 0x844-0x847,
are not erased during a standard Bulk Erase, unless
the PC is moved into configuration memory prior to
invoking the Bulk Erase. If these values are to be
erased, it is the user’s responsibility to read and store
them prior to the erase cycle and then to rewrite them
back to these locations for future use.
DS41670A-page 4
Preliminary
 2012 Microchip Technology Inc.
PIC16F570
3.0
COMMANDS AND
ALGORITHMS
3.1
Program/Verify Mode
3.1.1
The ICSPCLK pin is used for clock input and the
ICSPDAT pin is used for data input/output during serial
operation. To input a command, the clock pin is cycled
six times. Each command bit is latched on the falling
edge of the clock with the LSb of the command being
input first. The data must adhere to the setup (TSET1)
and hold (THLD1) times with respect to the falling edge
of the clock (see Figure 3-2).
The Program/Verify mode is entered by holding pins
ICSPCLK and ICSPDAT low while raising the VDD pin
from VIL to VDDPROG. Then raise the VPP pin from VIL
to VIHH. Once in this mode, the user program memory
and configuration memory can be accessed and
programmed in serial fashion. Clock and data are
Schmitt Trigger input in this mode.
FIGURE 3-1:
Commands that do not have data associated with them
are required to wait a minimum of TDLY2 measured
from the falling edge of the last command clock to the
rising edge of the next command clock (see
Figure 3-4). Commands that do have data associated
with them (Read and Load) are also required to wait
TDLY2 between the command and the data segment
measured from the falling edge of the last command
clock to the rising edge of the first data clock. The data
segment, consisting of 16 clock cycles, can begin after
this delay (see Figure 3-2).
ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
TPPDP
THLD0
VIHH
VPP
VIL
Note:
VDD
After every End Programming command,
a time of TDIS must be delayed.
The first and last clock pulses during the data segment
correspond to the Start and Stop bits, respectively.
Input data is a “don't care” during the Start and Stop
cycles. The 14 clock pulses between the Start and Stop
cycles clock the 14 bits of input/output data. Data is
transferred LSb first.
ICSPDAT
ICSPCLK
The sequence that enters the device into the
Programming/Verify mode places all other logic into the
Reset state (the MCLR pin was initially at VIL). This
means that all I/Os are in the Reset state (highimpedance inputs).
During Read commands, in which the data is output
from the PIC® device, the ICSPDAT pin transitions from
the high-impedance state to the low-impedance output
state at the rising edge of the second data clock (first
clock edge after the Start cycle). The ICSPDAT pin
returns to the high-impedance state at the rising edge
of the 16th data clock (first edge of the Stop cycle) (see
Figure 3-3).
The program memory may be written in two ways. The
fastest method writes four words at a time to the
program memory array. However, one-word writes are
also supported (see Section 3.1.2 “Four-Word
Programming” and Section 3.1.3 “One-Word
Programming”).
TABLE 3-1:
SERIAL PROGRAM/VERIFY
OPERATION
The commands that are available are described in
Table 3-1.
COMMAND MAPPING FOR PIC16F570
Command
Mapping (MSb … LSb)
Data
Load Data for Program Memory
x
x
0
0
1
0
0 (start bit), data (14-bit), 0 (stop bit)
Read Data from Program Memory
x
x
0
1
0
0
0 (start bit), data (14-bit), 0 (stop bit)
Increment Address
x
x
0
1
1
0
Begin Programming
x
x
1
0
0
0
End Programming
x
x
1
1
1
0
Bulk Erase Program Memory
x
x
1
0
0
1
 2012 Microchip Technology Inc.
Preliminary
Externally Timed
Internally Timed
DS41670A-page 5
PIC16F570
3.1.2
FOUR-WORD PROGRAMMING
3.1.3
The normal sequence for writing the program array is
to load four words to sequential addresses, then issue
a Begin Programming command. The PC must be
advanced following the first three loads, but not
advanced following the last program load until after the
programming cycle. The programming cycle is started
and timed externally. Then, the PC is advanced after
the programming cycle. The cycle repeats to program
the array. After writing the array, the PC may be reset
and read back to verify the write. It is not possible to
verify immediately following the write because the PC
can only increment, not decrement (see Figure 3-11).
ONE-WORD PROGRAMMING
Configuration memory must be written one word at a
time. The one-word sequence loads a word, programs,
verifies and finally increments the PC (see
Figure 3-10).
A device Reset will clear the PC and set the address to
0xFFF. The Increment Address command will
increment the PC. The available commands are shown
in Table 3-1.
3.1.4
PROGRAMMING SELF-WRITABLE
FLASH MEMORY
The same program mode commands that work on the
standard Flash memory also work on the self-writable
Flash memory area.
It is important that the PC is not advanced after the 4th
word is loaded, as the programming cycle writes the
row selected by the PC<11:2>. If the PC is advanced,
the data will be written to the next row.
3.1.5
LOAD DATA FOR PROGRAM
MEMORY
After receiving this command, the chip will load a 14bit “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two Most Significant bits (MSbs) of the data word are
ignored. The data received is loaded into a data latch.
A timing diagram for the Load Data command is shown
in Figure 3-2.
FIGURE 3-2:
LOAD DATA COMMAND (PROGRAM/VERIFY)
1
2
3
4
5
0
0
x
6
TDLY2
1
2
3
4
5
15
16
ICSPCLK
ICSPDAT
0
1
TSET1
THLD1
DS41670A-page 6
x
strt_bit
TDLY1
LSb
MSb stp_bit
TSET1
-+THLD1
Preliminary
 2012 Microchip Technology Inc.
PIC16F570
3.1.6
READ DATA FROM PROGRAM
MEMORY
After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently addressed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge. Because this is a 12-bit core, the
two MSbs of the 14-bit word will be read as ‘1’s.
If the program memory is code-protected (CP = 0),
portions of the program memory will be read as zeros.
See Section 5.0 “Code Protection” for details.
FIGURE 3-3:
READ DATA FROM PROGRAM MEMORY COMMAND
TDLY2
1
2
3
4
1
0
5
1
6
2
3
ICSPCLK
4
5
15
16
TDLY3
1 0
ICSPDAT
0
x
x
stp_bit
LSb
TDLY1
TSET1
MSb
strt_bit
THLD1
Input
3.1.7
Input
Output
INCREMENT ADDRESS
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 3-4.
It is not possible to decrement the address counter. To
reset this counter, the user must either exit and re-enter
Program/Verify mode or increment the PC from 0xFFF
to 0x000.
FIGURE 3-4:
INCREMENT ADDRESS COMMAND
TDLY2
1
2
3
4
5
6
Next Command
1
2
ICSPCLK
ICSPDAT
0
1
1
0
x
x
TSET1
THLD1
 2012 Microchip Technology Inc.
Preliminary
DS41670A-page 7
PIC16F570
3.1.8
BEGIN PROGRAMMING
(EXTERNALLY TIMED)
A Load command must be given before every Begin
Programming command. Programming will begin after
this command is received and decoded. Programming
requires (TPROG) time and is terminated using an End
Programming command. This command programs the
current location(s). No erase is performed.
FIGURE 3-5:
BEGIN PROGRAMMING (EXTERNALLY TIMED)
TPROG
End Programming Command
1
2
3
0
0
0
4
5
1
6
2
ICSPCLK
ICSPDAT
1
TSET1
3.1.9
x
0
x
1
THLD1
END PROGRAMMING
The End Programming command terminates the
program process by removing the high programming
voltage from the memory cells and resetting the data
input latches to all ‘1’s (erased state). A delay of TDIS is
required before the next command to allow the high
programming voltage to discharge (see Figure 3-6).
FIGURE 3-6:
END PROGRAMMING (EXTERNALLY TIMED)
TDIS
1
2
3
4
0
1
1
1
5
6
Next Command
1
2
ICSPCLK
ICSPDAT
TSET1
DS41670A-page 8
x
x
THLD1
Preliminary
 2012 Microchip Technology Inc.
PIC16F570
3.1.10
BULK ERASE PROGRAM MEMORY
To perform a Bulk Erase of the program memory and
configuration fuses, the following sequence must be
performed (see Figure 3-7).
After this command is performed, the entire program
memory and Configuration Word is erased.
1.
Note 1: A fully-erased part will read ‘1’s in every
program memory location.
2: The oscillator calibration bits are erased if
a Bulk Erase is invoked. They must be
read and saved prior to erasing the
device and restored during the programming operation. Oscillator calibration bits
are stored at the Reset vector as the
operand of a MOVLW instruction.
2.
3.
4.
5.
Read and save the oscillator calibration bits
stored at the Reset vector location 0x7FF, and
the backup OSCCAL bits stored at locations
0x844-0x847
into
computer/programmer
temporary memory.
Enter Program/Verify mode. PC is set to the
Configuration Word address.
Perform a Bulk Erase Program Memory
command.
Wait TERA to complete Bulk Erase.
Restore oscillator calibration bits and backup
OSCCAL bits to respective locations.
To perform a full device Bulk Erase of the program
memory, configuration fuses, user IDs and backup
OSCCAL, the following sequence must be performed
(see Figure 3-7).
1.
2.
3.
4.
5.
6.
FIGURE 3-7:
Read and save the oscillator calibration bits
stored at the Reset vector location 0x7FF, and
the backup OSCCAL bits stored at locations
0x844-0x847
into
computer/programmer
temporary memory.
Enter Program/Verify mode.
Increment the PC to 0x840 (first user ID
location).
Perform a Bulk Erase command.
Wait TERA to complete Bulk Erase.
Restore oscillator calibration bits and backup
OSCCAL bits to respective locations.
BULK ERASE PROGRAM MEMORY COMMAND
TERA
Next Command
1
2
3
4
5
6
1
2
ICSPCLK
1
ICSPDAT
0
0
1
x
x
TSET1
THLD1
 2012 Microchip Technology Inc.
Preliminary
DS41670A-page 9
PIC16F570
3.1.11
VDD FOR BULK ERASE
To ensure that there is sufficient voltage to bulk erase
the program memory, the VDD voltage level must be
maintained at the VDDPROG level throughout the entire
execution of the Bulk Erase command. See
Section 6.0 “Program/Verify Mode Electrical
Characteristics”.
If the VDD voltage level is not high enough at the time
the Bulk Erase command is issued, the erase operation
will not commence.
TABLE 3-2:
BULK ERASE MEMORY PORTIONS
Config. Word
(Fuses)
User Program
Memory Erased
FFFh Configuration Word (Fuses)
Yes
Yes
CPSW = 0 - Yes
CPSW = 1 - No
No
000h-7FFh (Program Memory)
Yes
Yes
CPSW = 0 - Yes
CPSW = 1 - No
No
800h-83Fh (Self-Write Memory)
No
No
No
840h-847h (User ID Memory)
No
No
CPSW = 0 - No
CPSW = 1 - Yes
No
PC
Note:
Self-Writable Flash
User ID
Data Memory Erased Memory Erased
Yes
Yes = Erased; No = Unchanged
DS41670A-page 10
Preliminary
 2012 Microchip Technology Inc.
PIC16F570
FIGURE 3-8:
READING AND TEMPORARY SAVING OF THE OSCCAL CALIBRATION BITS
Start
Enter Programming
Mode
Increment
Address
No
PC = 0x7FF?
Yes
Read Calibration
Bits and Save in
Computer/Programmer
Temp. Memory
Increment
Address
No
PC = 0x844?
Yes
Read Backup OSCCAL
bits and Save in
Computer/Programmer
Temporary Memory
Exit Programming Mode
Done
 2012 Microchip Technology Inc.
Preliminary
DS41670A-page 11
PIC16F570
FIGURE 3-9:
RESTORING/PROGRAMMING THE OSCCAL CALIBRATION BITS
Start
Enter Programming
Mode
Increment
Address
No
PC = 0x7FF?
Yes
Read Calibration
Bits from
Computer/Programmer
Temperature Memory
Write calibration bits
back as the operand
of a MOVLW instruction
to 0x7FF
Increment
Address
No
PC = 0x844?
Yes
Read Backup OSCCAL
Calibration Bits from
Computer/Programmer
Temperature Memory
Write Backup OSCCAL
Bits back to 0x844
Exit Programming Mode
Done
DS41670A-page 12
Preliminary
 2012 Microchip Technology Inc.
PIC16F570
FIGURE 3-10:
ONE-WORD PROGRAM FLOWCHART – PROGRAM MEMORY
Start
Read and Save
OSCCAL bits
(Figure 3-8)
Enter Program
Mode
PC = 0xFFF
Increment
Address
Bulk Erase
Device
PROGRAM CYCLE
Load Data
for
Program Memory
One Word
Program Cycle
Begin
Programming
Command
(Externally Timed)
Read Data
from
Program Memory
Wait TPROG
Data Correct?
No
Report
Programming
Failure
End
Programming
Yes
Increment
Address
Command
No
All Locations
Done?
Wait TDIS
Yes
Exit Program
Mode
Restore OSCCAL
bits (Figure 3-9)
Program
Configuration
Memory
(Figure 3-12)
Done
 2012 Microchip Technology Inc.
Preliminary
DS41670A-page 13
PIC16F570
FIGURE 3-11:
FOUR-WORD PROGRAM FLOWCHART – PROGRAM MEMORY
Start
Read and Save
OSCCAL bits
(Figure 3-8)
PROGRAM CYCLE
Load Data
for
Program Memory
Enter
Program
Mode
PC = FFF
Increment
Address
Command
Increment
Address
Command
Load Data
for
Program Memory
Bulk Erase
Device
Increment
Address
Command
Four-Word
Program Cycle
Increment
Address
Command
Load Data
for
Program Memory
No
All Locations
Done?
Increment
Address
Command
Yes
Reset and
Re-enter
Program/Verify
Load Data
for
Program Memory
Read Data
Command
Data
Correct?
No
Report
Verify Error
Begin
Programming
Command
(Externally timed)
Yes
Wait TPROG
Increment
Address
Command
No
Address =
0x800?
Program
Configuration
memory
(Figure 3-12)
Yes
Exit
Program
Mode
Restore
OSCCAL bits
End
Programming
Wait TDIS
(Figure 3-9)
Done
DS41670A-page 14
Preliminary
 2012 Microchip Technology Inc.
PIC16F570
FIGURE 3-12:
PROGRAM FLOWCHART – CONFIGURATION MEMORY
Start
Enter Program
Mode
PC = 0xFFF
One-Word
Programming
Cycle
(Figure 3-10)
Programs Configuration Word
Read Data
Command
Data
Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
No
Address =
0x840?
Yes
Load Data
Command
Programs User IDs
One-Word
Programming
Cycle
(Figure 3-10)
Read Data
Command
Data
Correct
No
Report
Programming
Failure
Yes
Increment
Address
Command
No
Address =
0x843?
Yes
Exit
Programming
mode
Done
 2012 Microchip Technology Inc.
Preliminary
DS41670A-page 15
PIC16F570
FIGURE 3-13:
PROGRAM FLOWCHART – ERASE PROGRAM MEMORY, CONFIGURATION
WORD
Start
Bulk Erase Device
Read and save
OSCCAL bits
(Figure 3-8)
Wait TERA
Restore OSCCAL bits
(Figure 3-9)
Enter
Program/Verify mode
PC = 0xFFF
(Config. Word)
Exit Programming
Mode
Done
FIGURE 3-14:
PROGRAM FLOWCHART – ERASE PROGRAM MEMORY, CONFIGURATION
WORD AND USER ID
Read and save
OSCCAL bits
(Figure 3-8)
Start
Enter
Program/Verify mode
PC = 0xFFF
(Config. Word)
Increment
PC
No
PC = 0x840?
(First User ID)
Yes
Bulk Erase Device
Wait TERA
Restore OSCCAL bits
(Figure 3-9)
Exit Programming Mode
Done
DS41670A-page 16
Preliminary
 2012 Microchip Technology Inc.
PIC16F570
4.0
CONFIGURATION WORD
The implemented Configuration bits can be
programmed at their default values, or they are not
programmed.
See Register 4-1 below for details.
REGISTER 4-1:
U-1
U-1
—
—
CONFIGURATION WORD
R/P-1
R/P-1
DRTEN BOREN
R/P-1
R/P-1
U-1
R/P-1
R/P-1
CPSW
IOSCFS
—
CP
WDTE
R/P-1
R/P-1
R/P-1
FOSC2 FOSC1 FOSC0
bit 11
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
u = Bit is unchanged
x = Bit is unknown
-n = Blank/Bulk Erase Value
‘1’ = Bit is set
‘0’ = Bit is cleared
P = Programmable bit
bit 11-10
Unimplemented: Read as ‘1’
bit 9
DRTEN: Device Reset Timer Enable bit
1 = DRT enabled (18 ms)
0 = DRT disabled
bit 8
BOREN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
bit 7
CPSW: Code Protection bit – Self-Writable Flash Data Memory
1 = Code protection off
0 = Code protection on
bit 6
IOSCFS: Internal Oscillator Frequency Select bit
1 = 8 MHz INTOSC speed
0 = 4 MHz INTOSC speed
bit 5
Unimplemented: Read as ‘1’
bit 4
CP: Code Protection bit – User Program Memory
1 = Code protection off
0 = Code protection on
bit 3
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0
FOSC<2:0>: Oscillator Selection bits
000 = LP oscillator and automatic 18 ms DRT (DRTEN fuse ignored)
001 = XT oscillator and automatic 18 ms DRT (DRTEN fuse ignored)
010 = HS oscillator and automatic 18 ms DRT (DRTEN fuse ignored)
011 = EC oscillator with RA6 function on RA6/OSC2/CLKOUT and 10 us start-up time(1,2)
100 = INTRC with RA6 function on RA6/OSC2/CLKOUT and 10 us start-up time(1,2)
101 = INTRC with CLKOUT function on RA6/OSC2/CLKOUT and 10 us start-up time(1,2)
110 = EXTRC with RA6 function on RA6/OSC2/CLKOUT and 10 us start-up time(1,2)
111 = EXTRC with CLKOUT function on RA6/OSC2/CLKOUT and 10 us start-up time(1,2)
Note 1:
It is the responsibility of the application designer to ensure that the use of the 10 us start-up time will result
in acceptable operation. Refer to Section 6.0 “Program/Verify Mode Electrical Characteristics” for
VDD rise time and stability requirements for this mode of operation.
The optional DRTEN fuse can be used to extend this start-up time to 18 ms.
2:
 2012 Microchip Technology Inc.
Preliminary
DS41670A-page 17
PIC16F570
5.0
CODE PROTECTION
5.2
For the PIC16F570, once code protection is enabled,
all program memory locations 0x40-0x7FE read all ‘0’s.
Program memory locations 0x000-0x03F and 0x7FF
are always unprotected. The user ID locations, backup
OSCCAL location and the Configuration Word read out
in an unprotected fashion. It is possible to program the
user ID locations, backup OSCCAL location and the
Configuration Word after code-protect is enabled.
The code protection of the self-writable Flash data
memory is dependant on the CPSW bit. If the CPSW
bit is set, only the self-writable Flash data memory
block is code-protected. See Table 3-2 for erase
conditions involving the CPSW bit.
5.1
5.2.1
Checksum Computation
CHECKSUM
Checksum is calculated by reading the contents of the
PIC16F570 memory locations and adding up the
opcodes up to the maximum user addressable location.
Any Carry bits exceeding 16 bits are neglected. Finally,
the Configuration Word (appropriately masked) is
added to the checksum. The checksum computation
for the PIC16F570 is shown in Table 5-1.
The checksum is calculated by summing the following:
• The contents of all program memory locations
• The Configuration Word, appropriately masked
• Masked user ID locations (when applicable)
The Least Significant 16 bits of this sum are the
checksum.
Disabling Code Protection
It is recommended that the following procedure be
performed before any other programming is attempted.
It is also possible to turn code protection off using this
procedure. However, all data within the program
memory will be erased when this procedure is executed, and thus, the security of the code is not
compromised. See Table 3-2 for more information on
self-writable Flash data memory.
The following table describes how to calculate the
checksum for each PIC16F570.
Note:
The checksum calculation differs depending on the code-protect setting. The
Configuration Word and user ID locations
can always be read regardless of the
code-protect settings.
To disable code-protect:
a)
b)
c)
Enter Program mode
Execute the Bulk Erase program memory
command (001001)
Wait TERA
Note:
To allow portability of code, the programmer is required to read the Configuration
Word and user ID locations from the hex
file when loading the hex file. If Configuration Word information was not present in
the hex file, then a simple warning
message may be issued. Similarly, while
saving a hex file, Configuration Word and
user ID information must be included. An
option to not include this information may
be provided.
Microchip Technology Incorporated feels
strongly that this feature is important for
the benefit of the end customer.
DS41670A-page 18
Preliminary
 2012 Microchip Technology Inc.
PIC16F570
TABLE 5-1:
Device
PIC16F570
CHECKSUM COMPUTATIONS(1)
Code-Protect
Checksum*
0x723 at 0
and Max.
Address
Blank
Value
OFF
SUM[0x000:0x7FE] + CFGW & 0x3FF
0xEBE0
0xDA28
ON
SUM[0x00:0x3F] + CFGW & 0x3FF + SUM_ID
0xEF6F
0xD4DB
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = User ID locations masked by 0xF then made into a 16-bit value with ID0 as the
Most Significant nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID2 = 0x3, ID3 = 0x4, then SUM_ID = 0x1234.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
Note 1: Checksum shown assumes that SUM_ID contains the unprotected checksum.
 2012 Microchip Technology Inc.
Preliminary
DS41670A-page 19
PIC16F570
6.0
PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 6-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE
Standard Operating Conditions (unless otherwise
stated)
Operating Temperature 10°C  TA 40°C
Operating Voltage
4.5V  VDD 5.5V
AC/DC CHARACTERISTICS
Sym.
Characteristics
Min.
Typ.
Max.
Units
Conditions/
Comments
General
VDDPROG
VDD level for programming operations,
program memory
4.5
—
5.5
V
VDDERA
VDD level for Bulk Erase operations,
program memory
4.5
—
5.5
V
IDDPROG
IDD level for programming operations,
program memory
—
—
1.8
mA
IDDERA
IDD level for Bulk Erase operations, program
memory
—
—
1.8
mA
VIHH
High voltage on MCLR for Program/Verify
mode entry
12.5
—
13.5
V
IIHH
MCLR pin current during Program/Verify
mode
—
—
0.45
mA
TVHHR
MCLR rise time (VSS to VIHH) for Program/
Verify mode entry
—
—
1.0
s
TPPDP
Hold time after VDD
5
—
—
s
VIH1
(ICSPCLK, ICSPDAT) input high level
0.8 VDD
—
—
V
VIL1
(ICSPCLK, ICSPDAT) input low level
—
—
0.2 VDD
V
THLD0
ICSPCLK, ICSPDAT hold time after MCLR
(Program/Verify mode selection pattern
setup time)
5
—
—
s
Serial Program/Verify
TSET1
Data in setup time before clock
100
—
—
ns
THLD1
Data in hold time after clock
100
—
—
ns
TDLY1
Data input not driven to next clock input
(delay required between command/data or
command/command)
1.0
—
—
s
TDLY2
Delay between clockto clockof next
command or data
1.0
—
—
s
TDLY3
Clock to data out valid (during Read Data)
—
80
ns
TERA
Erase cycle time
—
—
10(1)
ms
TPROG
Programming cycle time (externally timed)
—
—
2(1)
ms
TDIS
Time delay for internal programming voltage
discharge
300
—
—
s
TRESET
Time between exiting Program mode with
VDD and VPP at GND and then re-entering
Program mode by applying VDD
—
10
—
ms
VSW
Self-write/erase voltage
2.0
—
—
V
TSW
Self-write/erase timing
2.0
—
5
ms
Note 1:
Minimum time to ensure that function completes successfully over voltage, temperature and device
variations.
DS41670A-page 20
Preliminary
 2012 Microchip Technology Inc.
PIC16F570
APPENDIX A:
REVISION HISTORY
Revision A (12/2012)
Initial release of this document.
 2012 Microchip Technology Inc.
Preliminary
DS41670A-page 21
PIC16F570
NOTES:
DS41670A-page 22
Preliminary
 2012 Microchip Technology Inc.
PIC16F570
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620768051
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2012 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Preliminary
DS41670A-page 23
Worldwide Sales and Service
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DS41670A-page 24
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11/29/12
Preliminary
 2012 Microchip Technology Inc.