PIC10F200/202/204/206 Memory Programming Specification

PIC10F200/202/204/206
Memory Programming Specification
This document includes the
programming specifications for the
following devices:
•
•
•
•
1.1
The PIC10F200/202/204/206 requires one power
supply for VDD (5.0V) and one for VPP (12V).
PIC10F200
PIC10F202
PIC10F204
PIC10F206
1.0
Hardware Requirements
1.2
Program/Verify Mode
The Program/Verify mode for the PIC10F200/202/204/
206 allows programming of user program memory for
user ID locations, backup OSCCAL location and the
Configuration Word.
PROGRAMMING THE
PIC10F200/202/204/206
The PIC10F200/202/204/206 is programmed using a
serial method. The Serial mode will allow the
PIC10F200/202/204/206 to be programmed while in
the user’s system. This allows for increased design
flexibility. This programming specification applies to
PIC10F200/202/204/206 devices in all packages.
Pin Diagrams
GP0
1
VSS
2
GP1
3
6
GP3/MCLR/VPP
5
VDD
4
GP2/T0CKI/FOSC4
1
VSS
2
GP1/CIN-
3
1
VDD
2
GP2/T0CKI/FOSC4
3
GP1
4
TABLE 1-1:
Pin Name
8
GP3/MCLR/VPP
N/C
1
7
VSS
VDD
2
6
N/C
GP2/T0CKI/COUT/FOSC4
3
5
GP0
GP1/CIN-
4
5
VDD
4
GP2/T0CKI/COUT/FOSC4
8
GP3/MCLR/VPP
7
VSS
6
N/C
5
GP0/CIN+
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC10F200/202/204/206
During Programming
Function
Pin Type
Pin Description
GP1
ICSPCLK
I
GP0
ICSPDAT
I/O
Program/Verify mode
P
Programming Power
VDD
VDD
P
Power Supply
VSS
VSS
P
Ground
Legend:
GP3/MCLR/VPP
PIC10F204/6
N/C
MCLR/VPP
6
PDIP
PIC10F200/2
PDIP
GP0/CIN+
PIC10F204/6
SOT-23
PIC10F200/2
SOT-23
Clock input – Schmitt Trigger input
Data input/output – Schmitt Trigger input
I = Input, O = Output, P = Power
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DS41228F-page 1
PIC10F200/202/204/206
2.0
MEMORY MAPPING
2.1
User Program Memory Map
have support in the language and programming tools.
For this reason, it is recommended that the user only
use the four LSBs of each user ID location.
The user memory space extends from (0x000-0x0FF)
on the PIC10F200/204 and (0x000-0x1FF) on the
PIC10F202/206. In Program/Verify mode, the program
memory space extends from (0x000-0x1FF) for the
PIC10F200/204
and
(0x000-0x3FF)
for
the
PIC10F202/206. The first half, (0x000-0x0FF) and
(0x000-0x1FF) respectively, is user program memory.
The second half, (0x100-0x1FF) and (0x200-0x3FF)
respectively, is configuration memory. The PC will
increment from (0x000-0x0FF) and (0x000-0x1FF)
respectively, then to 0x100 and 0x200, respectively
(not to 0x000).
2.3
Configuration Word
The Configuration Word register is physically located at
0x1FF and 0x3FF, respectively. It is only available upon
Program mode entry. Once an Increment Address
command is issued, the Configuration Word is no longer accessible, regardless of the address of the
program counter.
Note:
In the configuration memory space, 0x100-0x13F for
the PIC10F200/204, and 0x200-0x23F for the
PIC10F202/206,
are
physically
implemented.
However, only locations 0x100-0x103 and 0x2000x203 are available. Other locations are reserved.
User ID Locations
The contents of user ID locations are used in the
calculation of the device checksum when Code
Protection is enabled (CP = 0). The four Least
Significant bits (LSbs) of each location are
concatenated into a 2-byte value, the “User ID”, and
used in the checksum calculation. This 2-byte “User ID”
is displayed by MPLAB® IDE. Table 2-1 illustrates an
example of the relationship between the user ID
locations and the “User ID” value (PIC10F200/204),
used in the checksum computations (see Table 5-1 and
Table 5-2).
TABLE 2-1:
User ID
Memory
Address
“USER ID” VALUE AND
LOCATION 
(PIC10F200/204 EXAMPLE)
User ID Location – 12-bit
value
Binary
Hex
FIGURE 2-2:
User Memory
Space
A user may store identification information (ID) in four
user ID locations. The user ID locations are mapped in
[0x100:0x103] and [0x200:0x203], respectively. Each
user ID location is 12 bits.
PIC10F200/204 PROGRAM
MEMORY MAP
On-chip
User
Program
Memory
Reset Vector
User ID Locations
Config Memory
Space
2.2
By convention, the Configuration Word
register is stored at the logical address
location of 0xFFF within the hex file generated for the PIC10F200/202/204/206.
This logical address location may not
reflect the actual physical address for the
part itself. It is the responsibility of the programming software to retrieve the Configuration Word register from the logical
address within the hex file and translate
the address to the proper physical location
when programming.
Backup OSCCAL value
000h
00Fh
010h
0FEh
0FFh
100h103h
104h
105h
Reserved
Unimplemented
Configuration Word
13Fh
140h
1FEh
1FFh
“User ID”
Values
0x100
0000 0000 1001b
009h
9xxxh
0x101
1100 0001 1000b
C18h
x8xxh
0x102
0111 0010 0100b
724h
xx4xh
0x103
0110 0011 0101b
635h
xxx5h
“User ID” composite value displayed in MPLAB IDE = 9845h
Although 12 bits are available in each location,
previous devices only implemented the lower 4 bits of
each location. As a result, these additional bits may not
DS41228F-page 2
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PIC10F200/202/204/206
User Memory
Space
FIGURE 2-3:
PIC10F202/206 PROGRAM
MEMORY MAP
000h
On-chip
User
Program
Memory
Reset Vector
Config Memory
Space
User ID Locations
Backup OSCCAL value
1FEh
1FFh
200h
203h
204h
205h
Reserved
23Fh
240h
Unimplemented
Configuration Word
2.4
0FFh
100h
3FEh
3FFh
Oscillator Calibration Bits
The oscillator Calibration bits are stored at the Reset
vector as the operand of a MOVLW instruction.
Programming interfaces must allow users to program
the Calibration bits themselves for custom trimming of
the INTOSC. Capability for programming the
Calibration bits when programming the entire memory
array must also be maintained for backwards
compatibility.
2.5
Backup OSCCAL Value
The backup OSCCAL value, 0x104/0x204, is a factory
reserved location where the OSCCAL value is stored
during testing of the INTOSC. This location is not
erased during a standard Bulk Erase, but is erased if
the PC is moved into configuration memory prior to
invoking a Bulk Erase. If this value is erased, it is the
user’s responsibility to rewrite it back to this location for
future use.
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DS41228F-page 3
PIC10F200/202/204/206
3.0
PROGRAM/VERIFY MODE
In Program/Verify mode, the program memory and the
configuration memory can be accessed and
programmed in serial fashion. ICSPDAT and ICSPCLK
are used for the data and the clock, respectively. All
commands and data words are transmitted LSb first.
Data changes on the rising edge of the ICSPCLK and
is latched on the falling edge. In Program/Verify mode,
both the ICSPDAT and ICSPCLK are Schmitt Trigger
inputs. The sequence that enters the device into
Program/Verify mode places all other logic into the
Reset state. Upon entering Program/Verify mode, all
I/Os are automatically configured as high-impedance
inputs and the address is cleared.
3.1
• VDD- First Entry mode
• VPP- First Entry mode
3.1.1
3.
To enter Program/verify mode via the VDD- first
method, please follow the sequence below:
1.
2.
3.
Hold ICSPCLK and ICSPDAT low.
Raise the voltage on VDD from 0V to the desired
operating voltage (VIL to VDD).
Raise the voltage on MCLR/VPP from VDD or
below, to VIHH.
The VDD- first method is useful when programming the
device when VDD is already applied, for it is not
necessary to disconnect VDD to enter Program/Verify
mode. See the timing diagram in Figure 3-2.
FIGURE 3-2:
PROGRAMMING MODE
ENTRY – VDD FIRST
TPPDP
THLD0
VIHH
VPP
VIL
VDD
VPP- FIRST ENTRY MODE
To enter Program/Verify mode via the VPP- first
method, please follow the sequence below:
2.
VDD- FIRST ENTRY MODE
High-Voltage Program/Verify mode
Entry and Exit
There are two different methods of entering Program/
Verify mode via high-voltage:
1.
3.1.2
Hold ICSPCLK and ICSPDAT low. All other pins
should be un-powered.
Raise the voltage on MCLR/VPP from 0V to
VIHH.
Raise the voltage on VDD from 0V to the desired
operating voltage.
ICSPDAT
ICSPCLK
The VPP- first entry prevents the device from executing
code prior to entering Program/Verify mode. For
example, when Configuration Word 1 has MCLR
disabled (MCLRE = 0), the power-up time is disabled
(PWRTE = 0), the internal oscillator is selected
(FOSC = 100), and ICSPCLK and ICSPDAT pins are
driven by the user application, the device will execute
code. Since this may prevent entry, VPP- First Entry
mode is strongly recommended. See the timing
diagram in Figure 3-1.
FIGURE 3-1:
PROGRAMMING MODE
ENTRY – VPP FIRST
TPPDP
THLD0
VIHH
VPP
VIL
VDD
ICSPDAT
ICSPCLK
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PIC10F200/202/204/206
3.1.3
PROGRAM/VERIFY MODE EXIT
To exit Program/Verify mode take MCLR to VDD or
lower (VIL). See Figure 3-3 and Figure 3-4.
FIGURE 3-3:
PROGRAMMING MODE
EXIT – VPP LAST
TEXIT
VIHH
3.2
Program/Verify Commands
The PIC® Flash MCUs programming commands are
six bits in length. The commands are summarized in
Table 3-1. Commands that have data associated with
them are specified to have a minimum delay of TDLY
between the command and the data. After this delay,
16 clocks are required to either clock in or clock out the
14-bit data word. The first clock is for the Start bit and
the last clock is for the Stop bit.
3.2.1
VPP
VIL
VDD
ICSPDAT
ICSPCLK
FIGURE 3-4:
PROGRAMMING MODE
EXIT – VDD LAST
TEXIT
VIHH
VPP
VIL
VDD
ICSPDAT
ICSPCLK
SERIAL PROGRAM/VERIFY
OPERATION
The ICSPCLK pin is used for clock input and the
ICSPDAT pin is used for data input/output during serial
operation. To input a command, the clock pin is cycled
six times. Each command bit is latched on the falling
edge of the clock with the LSb of the command being
input first. The data must adhere to the setup (TSET1)
and hold (THLD1) times with respect to the falling edge
of the clock (see Table 6-1).
Commands that do not have data associated with them
are required to wait a minimum of TDLY2 measured
from the falling edge of the last command clock to the
rising edge of the next command clock (see Table 6-1).
Commands that do have data associated with them
(Read and Load) are also required to wait TDLY2
between the command and the data segment
measured from the falling edge of the last command
clock to the rising edge of the first data clock. The data
segment, consisting of 16 clock cycles, can begin after
this delay.
Note:
After every End Programming command,
a delay of TDIS is required.
The first and last clock pulses during the data segment
correspond to the Start and Stop bits, respectively.
Input data is a “don't care” during the Start and Stop
cycles. The 14 clock pulses between the Start and Stop
cycles clock the 14 bits of input/output data. Data is
transferred LSb first.
During Read commands, in which the data is output from
the PIC Flash MCUs, the ICSPDAT pin transitions from
the high-impedance input state to the low-impedance
output state at the rising edge of the second data clock
(first clock edge after the Start cycle). The ICSPDAT pin
returns to the high-impedance state at the rising edge of
the 16th data clock (first edge of the Stop cycle). See
Figure 3-6.
The commands that are available are described in
Table 3-1.
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DS41228F-page 5
PIC10F200/202/204/206
TABLE 3-1:
COMMAND MAPPING FOR PIC10F200/202/204/206
Command
Mapping (MSb … LSb)
HEX
Data
Load Data for Program Memory
x
x
0
0
1
0
02h
0, data (14), 0
Read Data from Program Memory
x
x
0
1
0
0
04h
0, data (14), 0
Increment Address
x
x
0
1
1
0
06h
Begin Programming
x
x
1
0
0
0
08h
End Programming
x
x
1
1
1
0
0Eh
Bulk Erase Program Memory
x
x
1
0
0
1
09h
3.2.1.1
Externally Timed
Internally Timed
Load Data For Program Memory
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 3-5.
FIGURE 3-5:
LOAD DATA COMMAND (PROGRAM/VERIFY)
1
2
3
4
5
0
0
x
6
TDLY2
ICSPCLK
ICSPDAT
3.2.1.2
1
0
TSET1
THLD1
1
2
strt_bit
x
3
13
LSb
14
MSb
15
X
16
stp_bit
X
TSET1
-+THLD1
TDLY1
Read Data From Program Memory
After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently addressed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge. Because this is a 12-bit core, the
two MSbs of the 14-bit word will be read as ‘0’s.
If the program memory is code-protected (CP = 0),
portions of the program memory will be read as zeros.
See Section 5.0 “Code Protection” for details.
FIGURE 3-6:
READ DATA FROM PROGRAM MEMORY COMMAND
TDLY2
1
2
3
4
1
0
5
6
1
2
3
ICSPCLK
ICSPDAT
13
14
15
16
TDLY3
0
0
x
X
strt_bit
TDLY1
TSET1
MSb
stp_bit
LSb
THLD1
Input
DS41228F-page 6
Output
Advance Information
Input
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PIC10F200/202/204/206
3.2.1.3
Increment Address
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 3-7.
It is not possible to decrement the address counter. To
reset this counter, the user must either exit and re-enter
Program/Verify mode or increment the PC from 0x1FF
for the PIC10F200/204 or 0x3FF for the PIC10F202/
206 to 0x000.
FIGURE 3-7:
INCREMENT ADDRESS COMMAND
TDLY2
1
2
3
4
5
Next Command
1
6
2
ICSPCLK
ICSPDAT
0
1
0
1
x
x
TSET1
THLD1
3.2.1.4
Begin Programming (Externally
Timed)
A Load command must be given before every Begin
Programming command. Programming will begin after
this command is received and decoded. Programming
requires (TPROG) time and is terminated using an End
Programming command. This command programs the
current location, no erase is performed.
FIGURE 3-8:
BEGIN PROGRAMMING (EXTERNALLY TIMED)
TPROG
1
2
3
0
0
0
4
5
6
x
x
End Programming Command
1
2
ICSPCLK
ICSPDAT
TSET1
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1
0
1
THLD1
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DS41228F-page 7
PIC10F200/202/204/206
3.2.1.5
End Programming
The End Programming command terminates the
program process. A delay of TDIS (see Table 6-1) is
required before the next command to allow the internal
programming voltage to discharge (see Figure 3-9).
FIGURE 3-9:
END PROGRAMMING (EXTERNALLY TIMED)
TDIS
1
2
3
4
0
1
1
1
5
6
Next Command
1
2
ICSPCLK
ICSPDAT
x
TSET1
3.2.1.6
Bulk Erase Program Memory
After this command is performed, the entire program
memory and Configuration Word is erased.
1.
2.
3.
4.
5.
THLD1
To perform a full device Bulk Erase of the program
memory, configuration fuses, user IDs and backup
OSCCAL value, the following sequence must be
performed (see Figure 3-16).
Note 1: A fully erased part will read ‘1’s in every
program memory location.
1.
2: The oscillator Calibration bits are erased
if a Bulk Erase is invoked. They must be
read and saved prior to erasing the
device and restored during the programming operation. Oscillator Calibration bits
are stored at the Reset vector as the
operand of a MOVLW instruction.
2.
3.
To perform a Bulk Erase of the program memory and
configuration fuses, the following sequence must be
performed (see Figure 3-15).
x
4.
5.
6.
7.
Read and save 0x0FF/0x1FF oscillator
Calibration bits and 0x104/0x204 backup
OSCCAL bits into computer/programmer
temporary memory.
Enter Program/Verify mode.
Increment PC to 0x200/0x400 (first user ID
location).
Perform a Bulk Erase command.
Wait TERA to complete Bulk Erase.
Restore OSCCAL bits.
Restore backup OSCCAL bits.
Read and save 0x0FF/0x1FF oscillator
Calibration bits and 0x104/0x204 backup
OSCCAL bits into computer/programmer
temporary memory.
Enter Program/Verify mode. PC is set to
Configuration Word address.
Perform a Bulk Erase Program Memory
command.
Wait TERA to complete Bulk Erase.
Restore OSCCAL bits.
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PIC10F200/202/204/206
TABLE 3-2:
BULK ERASE RESULTS
Program Memory Space
PC =
Configuration Memory Space
Program Memory
Reset Vector
Configuration
Word
User ID
Backup
OSCCAL
Configuration Word or
Program Memory Space
E
E
E
U
U
First User ID Location
E
E
E
E
E
FIGURE 3-10:
BULK ERASE PROGRAM MEMORY COMMAND
TERA
1
2
3
4
5
6
Next Command
1
2
ICSPCLK
1
ICSPDAT
0
0
1
x
x
TSET1
THLD1
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PIC10F200/202/204/206
FIGURE 3-11:
READING AND TEMPORARY SAVING OF THE OSCCAL CALIBRATION BITS
Start
Enter Programming
Mode
Increment
Address
No
PC =
0x0FF/0x1FF?
Yes
Read Calibration
Bits and Save in
Computer/Programmer
Temp. Memory
Increment
Address
No
PC =
0x104/0x204?
Yes
Read Backup OSCCAL
Calibration Bits
and Save in
Computer/Programmer
Temp. Memory
Exit Programming Mode
Done
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PIC10F200/202/204/206
FIGURE 3-12:
RESTORING/PROGRAMMING THE OSCCAL CALIBRATION BITS
Start
Enter Programming
Mode
Increment
Address
No
PC =
0x0FF/0x1FF?
Yes
Read Calibration
Bits from
Computer/Programmer
Temp. Memory
Write Calibration Bits
back as the operand
of a MOVLW instruction
to 0x0FF/0x1FF
Increment
Address
No
PC =
0x104/0x204?
Yes
Read Backup OSCCAL
Calibration Bits from
Computer/Programmer
Temp. Memory
Write Backup OSCCAL
Bits back to 0x104/0x204
Exit Programming Mode
Done
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PIC10F200/202/204/206
FIGURE 3-13:
PROGRAM FLOW CHART – PIC10F200/202/204/206 PROGRAM MEMORY
Start
Read and save
OSCCAL bits
(Figure 3-11)
Enter Programing
Mode
PC = 0x1FF/0x3FF
(Config Word)
Increment
Address
Bulk Erase
Device
PROGRAM CYCLE
Load Data
for
Program Memory
One-Word
Program Cycle
Begin
Programming
Command
(Externally timed)
Read Data
from
Program Memory
No
Data Correct?
Report
Programming
Failure
End
Programming
Yes
Increment
Address
Command
No
Wait TPROG
All Programming
Locations
Done?
Wait TDIS
Yes
Exit Programming
Mode
Restore OSCCAL bits
(Figure 3-12)
Program
Configuration
Memory
(Figure 3-14)
Done
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PIC10F200/202/204/206
FIGURE 3-14:
PROGRAM FLOW CHART – PIC10F200/202/204/206 CONFIGURATION MEMORY
Start
Enter Programming
Mode
PC = 0x1FF/0x3FF
(Config Word)
Load Data Command
Programs Configuration Word
One-Word
Programming
Cycle
(see Figure 3-13)
Read Data Command
Data
Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
No
Address =
0x100/0x200
Yes
Load Data
Command
Programs User ID’s
One-Word
Programming
Cycle
(see Figure 3-13)
Read Data Command
Data
Correct?
No
Report
Programming
Failure
Yes
Increment Address
Command
No
Address =
0x104/0x204?
Yes
Exit Programming Mode
Yes
Done
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PIC10F200/202/204/206
FIGURE 3-15:
PROGRAM FLOW CHART – ERASE PROGRAM MEMORY, CONFIGURATION
WORD
Start
Bulk Erase Device
Read and save
OSCCAL bits
(Figure 3-11)
Wait TERA
Restore OSCCAL bits
(Figure 3-12)
Enter
Program/Verify mode
PC = 0x1FF/0x3FF
(Config Word)
Exit Programming Mode
Done
FIGURE 3-16:
PROGRAM FLOW CHART – ERASE PROGRAM MEMORY, CONFIGURATION
WORD AND USER ID
Read and save
OSCCAL bits
(Figure 3-11)
Start
Enter
Program/Verify mode
PC = 0x1FF/0x3FF
(Config Word)
Increment
PC
No
PC = 0x100/0x200?
(First User ID)
Yes
Bulk Erase Device
Wait TERA
Restore OSCCAL Bits
(Figure 3-12)
Exit Programming Mode
Done
DS41228F-page 14
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PIC10F200/202/204/206
4.0
CONFIGURATION WORD
The PIC10F200/202/204/206 has several Configuration
bits. These bits can be programmed (reads ‘0’) or left
unchanged (reads ‘1’), to select various device
configurations.
REGISTER 4-1:
CONFIGURATION WORD – PIC10F200/202/204/206
U-1
U-1
U-1
U-1
—
—
—
—
bit 11
bit 8
U-1
U-1
U-1
R/P-1
R/P-1
R/P-1
U-1
U-1
—
—
—
MCLRE
CP
WDTE
—
—
bit 7
bit 0
Legend:
W = Writable bit
‘0’ = Bit is cleared
R = Readable bit
‘1’ = Bit is set
x = Bit is unknown
-n = Value at POR
U = Unimplemented bit
P = Programmable Bit
bit 11-5
Unimplemented: Read as ‘1’
bit 4
MCLRE: Master Clear Enable bit
1 = GP3/MCLR pin functions as MCLR
0 = GP3/MCLR pin functions as GP3, MCLR internally tied to VDD
bit 3
CP: Code Protection bit
1 = Code protection off
0 = Code protection on
bit 2
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
Unimplemented: Read as ‘1’
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PIC10F200/202/204/206
5.0
CODE PROTECTION
5.3
Checksum Computation
For the PIC10F200/202/204/206, once code protection
is enabled, all program memory locations, 0x0400x0FE (F200/204) and 0x040-x1FE (F202/206) inclusive, read all ‘0’s. Program memory locations, 0x0000x03F, 0x0FF (F200/204) and 0x1FF (F202/206), are
always unprotected. The user ID locations, backup
OSCCAL locations, and the Configuration Word read
out in an unprotected fashion. It is possible to program
the user ID locations, backup OSCCAL locations and
the Configuration Word after code-protect is enabled.
5.3.1
5.1
The checksum is calculated by summing the following:
Disabling Code Protection
It is recommended that the following procedure be
performed before any other programming is attempted.
It is also possible to turn code protection off (CP = 1)
using this procedure. However, all data within the program memory will be erased when this procedure is
executed, and thus, the security of the code is not
compromised.
To disable code-protect:
a)
b)
Enter Program mode.
Execute Bulk Erase
command (001001).
Wait TERA.
c)
5.2
Note:
The checksum is calculated by reading the contents
of the PIC10F200/202/204/206 memory locations
and adding up the opcodes up to the maximum user
addressable location (e.g., 0x1FF for the
PIC10F202/206). Any Carry bits exceeding 16 bits
are neglected. Finally, the Configuration Word
(appropriately masked) is added to the checksum.
Checksum computation for the PIC10F200/202/204/
206 is shown in Table 5-2.
• The contents of all program memory locations
• The Configuration Word, appropriately masked
• Masked user ID locations (when applicable)
The Least Significant 16 bits of this sum is the
checksum.
The following table describes how to calculate the
checksum for each device.
Note:
Program
CHECKSUM
Memory
The
checksum
calculation
differs
depending on the code-protect setting.
The Configuration Word and user ID
locations can always be read regardless
of the code-protect settings.
Embedding Configuration Word
and User ID Information in the 
Hex File
To allow portability of code, the
programmer is required to read the
Configuration Word and user ID locations
from the hex file when loading the hex file.
If Configuration Word information was not
present in the hex file, then a simple
warning message may be issued.
Similarly, while saving a hex file,
Configuration Word and user ID
information must be included. An option to
not include this information may be
provided. 
Microchip Technology Incorporated feels
strongly that this feature is important for
the benefit of the end customer.
DS41228F-page 16
Advance Information
 2007-2011 Microchip Technology Inc.
PIC10F200/202/204/206
TABLE 5-1:
CHECKSUM COMPUTATIONS – PIC10F200/204
Device
Code-Protect
PIC10F200/204
OFF
ON
Blank
Value
0x723 at 0
and Max
Address
SUM[0x000:0x0FE] + CFGW & 0x01C
0xEF1D
0xDD65
SUM[0x00:0x3F] + CFGW & 0x01C + SUM_ID(1)
0xEEF1
0xD45D
Checksum*
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = User ID locations masked by 0x00F then made into a 16-bit value with ID0 as the Most
Significant nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID2 = 0x3, ID3 = 0x4, then SUM_ID = 0x1234.
*Checksum = [Sum of all the individual expressions] & [0x0FFFF]
+ = Addition
& = Bitwise AND
Note 1: The checksum shown assumes that SUM_ID contains the unprotected checksum.
TABLE 5-2:
CHECKSUM COMPUTATIONS – PIC10F202/206
Device
Code-Protect
PIC10F202/206
OFF
ON
Checksum*
SUM[0x000:0x1FE] + CFGW & 0x01C
(1)
SUM[0x00:0x3F] + CFGW & 0x01C + SUM_ID
Blank
Value
0x723 at 0
and Max
Address
0xEE1D
0xDC65
0xEDF1
0xD35D
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = User ID locations masked by 0x00F then made into a 16-bit value with ID0 as the Most
Significant nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID2 = 0x3, ID3 = 0x4, then SUM_ID = 0x1234.
*Checksum = [Sum of all the individual expressions] & [0x0FFFF]
+ = Addition
& = Bitwise AND
Note 1: The checksum shown assumes that SUM_ID contains the unprotected checksum.
 2007-2011 Microchip Technology Inc.
Advance Information
DS41228F-page 17
PIC10F200/202/204/206
6.0
PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 6-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
10°C  TA 40°C
Operating Voltage
4.5V  VDD 5.5V
AC/DC CHARACTERISTICS
Sym.
Characteristics
Min.
Typ.
Max.
Units
Conditions/
Comments
General
VDDPROG
VDD level for programming operations,
program memory
4.5
—
5.5
V
VDDERA
VDD level for Bulk Erase operations, program
memory
4.5
—
5.5
V
IDDPROG
IDD level for programming operations,
program memory
—
—
0.5
mA
IDDERA
IDD level for Bulk Erase operations, program
memory
—
—
0.5
mA
VPP
High voltage on MCLR for Program/Verify
mode entry
12.5
—
13.5
V
IPP
MCLR pin current during Program/Verify
mode
—
—
0.45
mA
TVHHR
MCLR rise time (VSS to VIHH) for Program/
Verify mode entry
—
—
1.0
s
TPPDP
Hold time after VPP
5
—
—
s
s
TEXIT
Time delay when exiting Program/Verify mode
1
—
—
VIH1
(ICSPCLK, ICSPDAT) input high level
0.8 VDD
—
—
V
VIL1
(ICSPCLK, ICSPDAT) input low level
—
—
0.2 VDD
V
TSET0
ICSPCLK, ICSPDAT setup time before
MCLR (Program/Verify mode selection
pattern setup time)
100
—
—
ns
THLD0
ICSPCLK, ICSPDAT hold time after MCLR
(Program/Verify mode selection pattern setup
time)
5
—
—
s
Serial Program/Verify
TSET1
Data in setup time before clock
100
—
—
ns
THLD1
Data in hold time after clock
100
—
—
ns
TDLY1
Data input not driven to next clock input (delay
required between command/data or command/command)
1.0
—
—
s
TDLY2
Delay between clockto clockof next
command or data
1.0
—
—
s
TDLY3
Clock to data out valid (during Read Data)
—
80
ns
TERA
Erase cycle time
—
6
10(1)
ms
TPROG
Programming cycle time (externally timed)
—
1
2(1)
ms
TDIS
Time delay for internal programming voltage
discharge
100
—
—
s
TRESET
Time between exiting Program mode with
VDD and VPP at GND and then re-entering
Program mode by applying VDD.
—
10
—
ms
Note 1:
Minimum time to ensure that function completes successfully over voltage, temperature and device variations.
DS41228F-page 18
Advance Information
 2007-2011 Microchip Technology Inc.
PIC10F200/202/204/206
APPENDIX A:
REVISION HISTORY
Revision F (11/2011)
Revised Sections 2.2; 3.0-3.2; Table 3-1; Register 4-1;
Table 5-1; Added Revision History.
 2007-2011 Microchip Technology Inc.
Advance Information
DS41228F-page 19
PIC10F200/202/204/206
NOTES:
DS41228F-page 20
Advance Information
 2007-2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-809-3
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
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DS41228F-page 21
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