PIC16F59 Memory Programming Specification This document includes the programming specifications for the following devices: • PIC16F59 1.0 PROGRAMMING THE PIC16F59 The PIC16F59 is programmed using a serial method. The Serial mode will allow the PIC16F59 to be programmed while in the user’s system. This allows for increased design flexibility. This programming specification applies to PIC16F59 devices in all packages. 1.1 Hardware Requirements The PIC16F59 requires one power supply for VDD (5.0V) and one for VPP (12V). 1.2 Program/Verify Mode The Program/Verify mode for the PIC16F59 allows programming of user program memory, special locations used for ID and the Configuration Word. © 2008 Microchip Technology Inc. Preliminary DS41243B-page 1 PIC16F59 Pin Diagrams •1 40 T0CKI RA1 2 39 RE7 RA2 3 38 RA3 4 37 RE6 RE5 VSS RB0 5 36 RE4 6 35 RB1 7 34 VDD OSC1/CLKIN RB2 8 33 OSC2/CLKOUT RB3 9 32 RD7 RB4 10 31 RD6 RB5 11 30 RD5 RB6/ICSPCLK 12 29 RD4 RB7/ICSPDAT 13 28 RD3 MCLR/VPP 14 27 VDD 15 26 RD2 RD1 RC0 16 25 VSS RC1 17 24 RD0 RC2 18 23 RC7 RC3 19 22 RC6 RC4 20 21 RC5 RA3 RA2 RA1 RA0 T0CKI RE7 RE6 RE5 RE4 VDD VDD 44 43 42 41 40 39 38 37 36 35 34 44-Pin TQFP PIC16F59 RA0 PDIP, 0.600" 33 32 31 30 29 28 27 26 25 24 23 PIC16F59 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 OSC1 OSC2 RD7 RD6 RD5 RD4 RD3 RD2 RD1 VSS VSS VDD VDD RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD0 VSS VSS RB0 RB1 RB2 RB3 RB4 RB5 RB6/ICSPCLK RB7/ICSPDAT MCLR/VPP TABLE 1-1: Pin Name PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F59 During Programming Function Pin Type Pin Description RB6 ICSPCLK I RB7 ICSPDAT I/O Data input/output – Schmitt Trigger input Program Mode Select Clock input – Schmitt Trigger input Program/Verify mode P(1) VDD VDD P Power Supply VSS VSS P Ground MCLR/VPP Legend: I = Input, O = Output, P = Power Note 1: In the PIC16F59, the programming high voltage is internally generated. To activate the Program/Verify mode, high voltage of IIHH current capability (see Table 5-1) needs to be applied to MCLR input. DS41243B-page 2 Preliminary © 2008 Microchip Technology Inc. PIC16F59 2.0 PROGRAM MODE ENTRY 2.1 User Program Memory Map FIGURE 2-1: PC<10:0> The user memory space extends from 0x000 to 0x7FF. In Program/Verify mode, the program memory space extends from 0x000 to 0xFFF with the first half (0x0000x7FF) being user program memory and the second half (0x800-0xFFF) being configuration memory. The PC will increment from 0x000 to 0x7FF, then to 0x800 (not to 0x000). 11 CALL, RETLW Stack Level 1 Stack Level 2 000h On-chip Program Memory (Page 0) In the configuration memory space, 0x800-0x83F are physically implemented. However, only locations 0x800 through 0x803 are available. Other locations are reserved. 0FFh 100h 1FFh 200h User Memory Space 2.2 PROGRAM MEMORY MAP AND STACK User ID Locations A user may store identification information (ID) in four user ID locations. The user ID locations are mapped in [0x800: 0x803]. It is recommended that the user use only the four Least Significant bits (LSb) of each user ID location. The user ID locations read out normally, even after code protection is enabled. It is recommended that user ID locations are written as ‘xxxx xxxx bbbb’ where ‘bbbb’ is user ID information. On-chip Program Memory (Page 1) 2FFh 300h 3FFh 400h On-chip Program Memory (Page 2) 4FFh 500h 5FFh 600h The 12 bits may be programmed, but only the four LSbs are displayed by MPLAB® IDE. The xxxx’s are “don’t care” bits and are not read by MPLAB IDE. On-chip Program Memory (Page 3) 6FFh 700h Reset Vector 7FFh User ID Locations 800h803h Reserved 804h 83Fh 840h 2.3 Unimplemented Configuration Word FFEh The Configuration Word is located at 0xFFF and is only available upon Program mode entry. Once an Increment Address command is issued, the Configuration Word is no longer accessible regardless of the address of the program counter. Configuration Word 2.4 FFFh Program/Verify Mode The Program/Verify mode is entered by holding pins ICSPCLK and ICSPDAT low while raising VDD pin from VIL to VDD. Then raise VPP from VIL to VIHH. Once in this mode, the user program memory and configuration memory can be accessed and programmed in serial fashion. Clock and data are Schmitt Trigger input in this mode. The sequence that enters the device into the Programming/Verify mode places all other logic into the Reset state (the MCLR pin was initially at VIL). This means that all I/O are in the Reset state (high-impedance inputs). The PIC16F59 program memory may be written in two ways. The fastest method writes four words at a time to the program memory array. However, one-word writes are also supported. © 2008 Microchip Technology Inc. Preliminary DS41243B-page 3 PIC16F59 2.4.1 2.4.3 FOUR-WORD PROGRAMMING The normal sequence for writing the program array is to load four words to sequential addresses, then issue a Begin Programming command. The PC must be advanced following the first three loads, but not advanced following the last program load until after the programming cycle. The programming cycle is started and timed externally. Then, the PC is advanced after the programming cycle. The cycle repeats to program the array. After writing the array, the PC may be reset and read back to verify the write. It is not possible to verify immediately following the write because the PC can only increment, not decrement. See Figure 2-10. The ICSPCLK pin is used for clock input and the ICSPDAT pin is used for data input/output during serial operation. To input a command, the clock pin is cycled six times. Each command bit is latched on the falling edge of the clock with the LSb of the command being input first. The data must adhere to the setup (TSET1) and hold (THLD1) times with respect to the falling edge of the clock (see Table 5-1). Commands that do not have data associated with them are required to wait a minimum of TDLY2 measured from the falling edge of the last command clock to the rising edge of the next command clock (see Table 5-1). Commands that do have data associated with them (Read and Load) are also required to wait TDLY2 between the command and the data segment measured from the falling edge of the last command clock to the rising edge of the first data clock. The data segment, consisting of 16 clock cycles, can begin after this delay. It is important that the PC is not advanced after the 4th word is loaded as the programming cycle writes the row selected by the PC <11:2>. If the PC is advanced, the data will be written to the next row. 2.4.2 ONE-WORD PROGRAMMING Configuration memory must be written one word at a time. The one-word sequence loads a word, programs, verifies and finally increments the PC. See Figure 2-9. Note: A device Reset will clear the PC and set the address to 0xFFF. The Increment Address command will increment the PC. The available commands are shown in Table 2-1. FIGURE 2-2: After every End Programming command, a time of TDIS must be delayed. The first and last clock pulses during the data segment correspond to the Start and Stop bits, respectively. Input data is a “don't care” during the Start and Stop cycles. The 14 clock pulses between the Start and Stop cycles clock the 14 bits of input/output data. Data is transferred LSb first. ENTERING HIGH VOLTAGE PROGRAM/ VERIFY MODE TPPDP SERIAL PROGRAM/VERIFY OPERATION During Read commands, in which the data is output from the PIC16FXXXX, the ICSPDAT pin transitions from the high-impedance state to the low-impedance output state at the rising edge of the second data clock (first clock edge after the Start cycle). The ICSPDAT pin returns to the high-impedance state at the rising edge of the 16th data clock (first edge of the Stop cycle). See Figure 2-4. THLD0 VPP VDD The commands that are available are described in Table 2-1. ICSPDAT ICSPCLK TABLE 2-1: COMMAND MAPPING FOR PIC16F59 Command Load Data for Program Memory Mapping (MSb … LSb) x x 0 0 1 Data 0 0, data (14), 0 0, data (14), 0 Read Data from Program Memory x x 0 1 0 0 Increment Address x x 0 1 1 0 Begin Programming x x 1 0 0 0 End Programming x x 1 1 1 0 Bulk Erase Program Memory x x 1 0 0 1 DS41243B-page 4 Preliminary Externally Timed Internally Timed © 2008 Microchip Technology Inc. PIC16F59 2.4.3.1 Load Data For Program Memory After receiving this command, the chip will load in a 14-bit “data word” when 16 cycles are applied, as described previously. Because this is a 12-bit core, the two MSbs of the data word are ignored. A timing diagram for the Load Data command is shown in Figure 2-3. FIGURE 2-3: LOAD DATA COMMAND (PROGRAM/VERIFY) 1 2 3 4 5 0 0 x 6 TDLY2 1 2 3 4 5 15 16 ICSPCLK 0 ICSPDAT 1 2.4.3.2 LSb strt_bit x TSET1 THLD1 MSb stp_bit 15 16 TSET1 TDLY1 -+THLD1 Read Data From Program Memory After receiving this command, the chip will transmit data bits out of the program memory (user or configuration) currently addressed, starting with the second rising edge of the clock input. The data pin will go into Output mode on the second rising clock edge, and it will revert to Input mode (high-impedance) after the 16th rising edge. Because this is a 12-bit core, the two MSbs of the 14-bit word will be read as ‘1’s. If the program memory is code-protected (CP = 0), portions of the program memory will be read as zeros. See Section 4.0 “Code Protection” for details. FIGURE 2-4: READ DATA FROM PROGRAM MEMORY COMMAND TDLY2 1 2 3 4 5 1 6 2 3 ICSPCLK ICSPDAT 4 5 TDLY3 1 0 0 1 0 x x strt_bit TDLY1 TSET1 MSb stp_bit LSb THLD1 Input © 2008 Microchip Technology Inc. Output Preliminary Input DS41243B-page 5 PIC16F59 2.4.3.3 Increment Address The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 2-5. It is not possible to decrement the address counter. To reset this counter, the user must either exit and re-enter Program/Verify mode or increment the PC from 0xFFF to 0X000. FIGURE 2-5: INCREMENT ADDRESS COMMAND TDLY2 1 2 3 4 5 Next Command 1 6 2 ICSPCLK ICSPDAT 0 1 1 0 x x TSET1 THLD1 2.4.3.4 Begin Programming (Externally Timed) A Load command must be given before every Begin Programming command. Programming will begin after this command is received and decoded. Programming requires (TPROG) time and is terminated using an End Programming command. This command programs the current location(s), no erase is performed. FIGURE 2-6: BEGIN PROGRAMMING (EXTERNALLY TIMED) TPROG End Programming Command 1 2 3 0 0 0 4 5 6 1 2 ICSPCLK ICSPDAT TSET1 DS41243B-page 6 1 x x 0 1 THLD1 Preliminary © 2008 Microchip Technology Inc. PIC16F59 2.4.3.5 End Programming The End Programming command terminates the program process by removing the high programming voltage from the memory cells and resetting the data input latches to all ‘1’s (erased state). A delay of TDIS (see Table 5-1) is required before the next command to allow the high programming voltage to discharge (see Figure 2-7. FIGURE 2-7: END PROGRAMMING (EXTERNALLY TIMED) TDIS 1 2 3 4 0 1 1 1 5 Next Command 1 6 2 ICSPCLK ICSPDAT TSET1 2.4.3.6 x x THLD1 Bulk Erase Program Memory After this command is performed, the entire program memory and Configuration Word is erased. To perform a Bulk Erase of the program memory and configuration fuses, the following sequence must be performed (see Figure 2-8). 1. 2. Perform a Bulk Erase Program Memory command Wait TERA to complete Bulk Erase To perform a Bulk Erase of the program memory, configuration fuses and user IDs, the following sequence must be performed (see Figure 2-8). 1. 2. 3. Increment PC to 0x800 Perform a Bulk Erase command Wait TERA to complete Bulk Erase FIGURE 2-8: BULK ERASE PROGRAM MEMORY COMMAND TERA 1 2 3 4 5 6 Next Command 1 2 ICSPCLK 1 ICSPDAT 0 0 1 x x TSET1 THLD1 © 2008 Microchip Technology Inc. Preliminary DS41243B-page 7 PIC16F59 FIGURE 2-9: ONE-WORD PROGRAM FLOWCHART – PIC16F59 PROGRAM MEMORY Start Enter Program Mode PC = 0xFFF Increment Address Bulk Erase Device PROGRAM CYCLE Load Data for Program Memory One Word Program Cycle Begin Programming Command (Externally timed) Read Data from Program Memory Data Correct? No Report Programming Failure End Programming Yes Increment Address Command No Wait TPROG All Locations Done? Wait TDIS Yes Exit Program Mode Program Configuration Memory (Figure 2-11) Done DS41243B-page 8 Preliminary © 2008 Microchip Technology Inc. PIC16F59 FIGURE 2-10: FOUR-WORD PROGRAM FLOWCHART – PIC16F59 PROGRAM MEMORY PROGRAM CYCLE Start Load Data for Program Memory Enter Program Mode PC = FFF Increment Address Command Increment Address Command Load Data for Program Memory Bulk Erase Device Increment Address Command Four-Word Program Cycle Increment Address Command No Load Data for Program Memory All Locations Done? Increment Address Command Yes Reset and Re-enter Program/Verify Load Data for Program Memory Read Data Command Data Correct? No Report Verify Error Yes Increment Address Command No Address = 0x800? Begin Programming Command (Externally timed) Wait TPROG Yes Exit Program Mode Program Configuration memory End Programming Wait TDIS (Figure 2-11) Done © 2008 Microchip Technology Inc. Preliminary DS41243B-page 9 PIC16F59 FIGURE 2-11: PROGRAM FLOWCHART – PIC16F59 CONFIGURATION MEMORY Start Enter Program Mode PC = 0xFFF One-Word Programming Cycle (see Figure 2-9) Programs Configuration Word Read Data Command Data Correct? No Report Programming Failure Yes Increment Address Command No Address = 0x800? Yes Load Data Command Programs User ID’s One-Word Programming Cycle (see Figure 2-9) Read Data Command Data Correct No Report Programming Failure Yes Increment Address Command No Address = 0x804? Yes Done DS41243B-page 10 Preliminary © 2008 Microchip Technology Inc. PIC16F59 FIGURE 2-12: PROGRAM FLOWCHART – ERASE PROGRAM MEMORY, CONFIGURATION WORD Start Enter Program/Verify mode PC = 0x3FF (Config Word) Bulk Erase Device Wait TERA Done FIGURE 2-13: PROGRAM FLOWCHART – ERASE PROGRAM MEMORY, CONFIGURATION WORD AND USER ID Start Enter Program/Verify mode PC = 0x3FF (Config Word) Increment PC No PC = 0x200? (First user ID) Yes Bulk Erase Device Wait TERA Done © 2008 Microchip Technology Inc. Preliminary DS41243B-page 11 PIC16F59 3.0 CONFIGURATION WORD The PIC16F59 has several Configuration bits. These bits can be programmed (reads ‘0’), or left unchanged (reads ‘1’), to select various device configurations. REGISTER 3-1: — — CONFIGURATION WORD — — — — — — CP WDTE FOSC1 bit 11 FOSC0 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 11-4 Unimplemented: Read as ‘1’ bit 3 CP: Code Protection bit 1 = Code protection off 0 = Code protection on bit 2 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0 FOSC1:FOSC0: Oscillator Selection bits 00 = LP oscillator 01 = XT oscillator 10 = HS oscillator 11 = RC oscillator DS41243B-page 12 Preliminary x = Bit is unknown © 2008 Microchip Technology Inc. PIC16F59 4.0 CODE PROTECTION 4.3 For the PIC16F59, once code protection is enabled, all program memory locations above 0x3F read all ‘0’s. Program memory locations 0x00-0x3F are always unprotected. The ID locations and the Configuration Word read out in an unprotected fashion. It is possible to program the ID locations and the Configuration Word once CP is enabled. 4.1 Disabling Code Protection Checksum Computation 4.3.1 CHECKSUM Checksum is calculated by reading the contents of the PIC16F59 memory locations and adding up the opcodes up to the maximum user addressable location, (e.g., 0x7FF for the PIC16F59). Any carry bits exceeding 16 bits are neglected. Finally, the Configuration Word (appropriately masked) is added to the checksum. Checksum computation for the PIC16F59 is shown in Table 4-1. It is recommended that the following procedure be performed before any other programming is attempted. It is also possible to turn code protection off (CP = 1) using this procedure. However, all data within the program memory will be erased when this procedure is executed, and thus, the security of the code is not compromised. The checksum is calculated by summing the following: To disable code-protect: The following table describes how to calculate the checksum for each device. a) b) c) Enter Programming mode Execute Bulk Erase Program Memory (001001) Wait TERA 4.2 • The contents of all program memory locations • The Configuration Word, appropriately masked • Masked ID locations (when applicable) The Least Significant 16 bits of this sum is the checksum. Note: Embedding Configuration Word and ID Information in the Hex File The checksum calculation differs depending on the code-protect setting. The Configuration Word and ID locations can always be read regardless of the code-protect setting. To allow portability of code, the programmer is required to read the Configuration Word and ID locations from the hex file when loading the hex file. If Configuration Word information was not present in the hex file, then a simple warning message may be issued. Similarly, while saving a hex file, Configuration Word and ID information must be included. An option to not include this information may be provided. Microchip Technology Incorporated feels strongly that this feature is important for the benefit of the end customer. TABLE 4-1: Device PIC16F59 CHECKSUM COMPUTATIONS(1) Code Protect Checksum* Blank Value 0x723 at 0 and Max Address OFF SUM[0x000:0x7FF] + CFGW & 0x00F + 0xFF0 0x07FF 0xF647 ON SUM[0x000:0x3F] + CFGW & 0x00F + 0xFF0 + SUM_ID 0x17B6 0xFD22 Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a to b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant nibble. For example, ID0 = 0x1, ID1 = 0x2, ID2 = 0x3, ID3 = 0x4, then SUM_ID = 0x1234. *Checksum = [Sum of all the individual expressions] modulo [0xFFFF] + = Addition & = Bitwise AND Note 1: Checksum shown assumes that SUM_ID contains the unprotected checksum. © 2008 Microchip Technology Inc. Preliminary DS41243B-page 13 PIC16F59 5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS TABLE 5-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE Standard Operating Conditions (unless otherwise stated) Operating Temperature 10°C ≤ TA ≤ 40°C Operating Voltage 4.5V ≤ VDD ≤ 5.5V AC/DC CHARACTERISTICS Sym. Characteristics Min. Typ. Max. Units Conditions/Comments General VDDPROG VDD level for programming operations, program memory 4.5 — 5.5 V VDDERA VDD level for Bulk Erase operations, program memory 4.5 — 5.5 V IDDPROG IDD level for programming operations, program memory — — 0.5 mA IDDERA IDD level for Bulk Erase operations, program memory — — 0.5 mA VPP High voltage on MCLR for Program/Verify mode entry 12.5 — 13.5 V IPP MCLR pin current during Program/Verify mode — — 0.45 mA TVHHR MCLR rise time (VSS to VIHH) for Program/ Verify mode entry — — 1.0 μs μs TPPDP Hold time after VPP↑ 5 — — VIH1 (ICSPCLK, ICSPDAT) input high-level 0.8 VDD — — V VIL1 (ICSPCLK, ICSPDAT) input low-level — — 0.2 VDD V TSET0 ICSPCLK, ICSPDAT setup time before MCLR↑ (Program/Verify mode selection pattern setup time) 100 — — ns THLD0 ICSPCLK, ICSPDAT hold time after MCLR↑ (Program/Verify mode selection pattern setup time) 5 — — μs Data in setup time before clock↓ 100 — — ns THLD1 Data in hold time after clock↓ 100 — — ns TDLY1 Data input not driven to next clock input (delay required between command/data or command/command) 1.0 — — μs TDLY2 Delay between clock↓ to clock↑ of next command or data 1.0 — — μs TDLY3 Clock↑ to data out valid (during Read Data) — 80 ns TERA Erase cycle time — — 10(1) ms TPROG Programming cycle time (externally timed) — — 2(1) ms TDIS Time delay for internal programming voltage discharge 100 — — μs TRESET Time between exiting Program mode with VDD and VPP at GND and then re-entering Program mode by applying VDD — 10 — ms Serial Program/Verify TSET1 Note 1: Minimum time to ensure that function completes successfully over voltage, temperature and device variations. DS41243B-page 14 Preliminary © 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. 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