PIC12F510 Memory Programming Specification This document includes the programming specifications for the following devices: 1.1 The PIC12F510 requires one power supply for VDD (5.0V) and one for VPP (12V). • PIC12F510 1.0 Hardware Requirements 1.2 PROGRAMMING THE PIC12F510 Program/Verify Mode The Program/Verify mode for the PIC12F510 allows programming of user program memory, user ID locations, backup OSCCAL location and the Configuration Word. The PIC12F510 is programmed using a serial method. The Serial mode will allow the PIC12F510 to be programmed while in the user’s system. This allows for increased design flexibility. This programming specification applies to PIC12F510 devices in all packages. Pin Diagrams TABLE 1-1: Pin Name VDD 1 GP5/OSC1/CLKIN 2 GP4/OSC2 3 MCLR/VPP/GP3 4 PIC12F510 PDIP, SOIC, MSOP 8 VSS 7 GP0/AN0/CIN+/ICSPDAT 6 GP1/AN1/CIN-/ICSPCLK 5 GP2/AN2/COUT//T0CKI PIN DESCRIPTIONS (DURING PROGRAMMING): PIC12F510 During Programming Function Pin Type Pin Description GP1 ICSPCLK I GP0 ICSPDAT I/O Data input/output – Schmitt Trigger input Program Mode Select Clock input – Schmitt Trigger input Program/Verify mode P(1) VDD VDD P Power Supply VSS VSS P Ground MCLR/VPP/GP3 Legend: I = Input, O = Output, P = Power Note 1: In the PIC12F510, the programming high voltage is internally generated. To activate the Program/Verify mode, high voltage of IIHH current capability (see Table 6-1) needs to be applied to the MCLR input. © 2007 Microchip Technology Inc. DS41257B-page 1 PIC12F510 2.1 User Program Memory Map The user memory space extends from (0x000-0x3FF) on the PIC12F510. In Program/Verify mode, the program memory space extends from (0x000-0x7FF) for the PIC12F510. The first half, (0x000-0x3FF), is user program memory. The second half, (0x400-0x7FF), is configuration memory. The PC will increment from (0x000-0x3FF) then to 0x400, (not to 0x000). In the configuration memory space, 0x400-0x43F are physically implemented. However, only locations 0x400-0x403 are available. Other locations are reserved. 2.2 User ID Locations A user may store identification information (ID) in four user ID locations. The user ID locations are mapped in [0x400:0x403]. It is recommended that the user use only the four Least Significant bits (LSb) of each user ID location. The user ID locations read out normally, even after code protection is enabled. It is recommended that user ID locations are written as ‘xxxx xxxx bbbb’ where ‘bbbb’ is user ID information. The 12 bits may be programmed, but only the four LSbs are displayed by MPLAB® IDE. The xxxx’s are “don’t care” bits and are not read by MPLAB IDE. 2.3 Configuration Word The Configuration Word is physically located at 0x7FF. It is only available upon Program mode entry. Once an Increment Address command is issued, the Configuration Word is no longer accessible, regardless of the address of the program counter. Note: By convention, the Configuration Word is stored at the logical address location of 0xFFF within the hex file generated for the PIC12F510. This logical address location may not reflect the actual physical address for the part itself. It is the responsibility of the programming software to retrieve the Configuration Word from the logical address within the hex file and granulate the address to the proper physical location when programming. DS41257B-page 2 FIGURE 2-1: User Memory Space MEMORY MAPPING PIC12F510 PROGRAM MEMORY MAP On-chip User Program Memory (Page 0) On-chip User Program Memory (Page 1) Reset Vector Config Memory Space 2.0 User ID Locations Backup OSCCAL value 1FFh 200h 3FEh 3FFh 400h 403h 404h 405h Reserved 43Fh 440h Unimplemented Configuration Word 2.4 000h 7FEh 7FFh Oscillator Calibration Bits The oscillator calibration bits are stored at the Reset vector as the operand of a MOVLW instruction. Programming interfaces must allow users to program the calibration bits themselves for custom trimming of the INTOSC. Capability for programming the calibration bits when programming the entire memory array must also be maintained for backwards compatibility. 2.5 Backup OSCCAL Value The backup OSCCAL value, 0x404, is a factory location where the OSCCAL value is stored during testing of the INTOSC. This location is not erased during a standard Bulk Erase, but is erased if the PC is moved into configuration memory prior to invoking a Bulk Erase. If this value is erased, it is the user’s responsibility to rewrite it back to this location for future use. © 2007 Microchip Technology Inc. PIC12F510 3.0 COMMANDS AND ALGORITHMS 3.1 Program/Verify Mode 3.1.2 The ICSPCLK pin is used for clock input and the ICSPDAT pin is used for data input/output during serial operation. To input a command, the clock pin is cycled six times. Each command bit is latched on the falling edge of the clock with the LSb of the command being input first. The data must adhere to the setup (TSET1) and hold (THLD1) times with respect to the falling edge of the clock (see Table 6-1). The Program/Verify mode is entered by holding pins ICSPCLK and ICSPDAT low while raising VDD pin from VIL to VDD. Then raise VPP from VIL to VIHH. Once in this mode, the user program memory and configuration memory can be accessed and programmed in serial fashion. Clock and data are Schmitt Trigger input in this mode. Commands that do not have data associated with them are required to wait a minimum of TDLY2 measured from the falling edge of the last command clock to the rising edge of the next command clock (see Table 6-1). Commands that do have data associated with them (Read and Load) are also required to wait TDLY2 between the command and the data segment measured from the falling edge of the last command clock to the rising edge of the first data clock. The data segment, consisting of 16 clock cycles, can begin after this delay. The sequence that enters the device into the Programming/Verify mode places all other logic into the Reset state (the MCLR pin was initially at VIL). This means that all I/O are in the Reset state (high-impedance inputs). 3.1.1 PROGRAMMING The programming sequence loads a word, programs, verifies and finally increments the PC. Program/Verify mode entry will set the address to 0x7FF. The Increment Address command will increment the PC. The available commands are shown in Table 3-1. FIGURE 3-1: Note: THLD0 During Read commands, in which the data is output from the PIC12F510, the ICSPDAT pin transitions from the high-impedance input state to the low-impedance output state at the rising edge of the second data clock (first clock edge after the Start cycle). The ICSPDAT pin returns to the high-impedance state at the rising edge of the 16th data clock (first edge of the Stop cycle). See Figure 3-3. VPP VDD ICSPDAT The commands that are available are described in Table 3-1. ICSPCLK TABLE 3-1: After every End Programming command, a delay of TDIS is required. The first and last clock pulses during the data segment correspond to the Start and Stop bits, respectively. Input data is a “don’t care” during the Start and Stop cycles. The 14 clock pulses between the Start and Stop cycles clock the 14 bits of input/output data. Data is transferred LSb first. ENTERING HIGH VOLTAGE PROGRAM/ VERIFY MODE TPPDP SERIAL PROGRAM/VERIFY OPERATION COMMAND MAPPING FOR PIC12F510 Command Mapping (MSb … LSb) Data Load Data for Program Memory x x 0 0 1 0 0, data (14), 0 Read Data from Program Memory x x 0 1 0 0 0, data (14), 0 Increment Address x x 0 1 1 0 Begin Programming x x 1 0 0 0 End Programming x x 1 1 1 0 Bulk Erase Program Memory x x 1 0 0 1 © 2007 Microchip Technology Inc. Externally Timed Internally Timed DS41257B-page 3 PIC12F510 3.1.2.1 Load Data For Program Memory After receiving this command, the chip will load in a 14-bit “data word” when 16 cycles are applied, as described previously. Because this is a 12-bit core, the two MSbs of the data word are ignored. A timing diagram for the Load Data command is shown in Figure 3-1. FIGURE 3-2: LOAD DATA COMMAND (PROGRAM/VERIFY) 1 2 3 4 5 0 0 TSET1 THLD1 x 6 TDLY2 ICSPCLK 3.1.2.2 1 0 ICSPDAT 1 2 4 5 16 15 MSb stp_bit LSb strt_bit x 3 TSET1 -+THLD1 TDLY1 Read Data From Program Memory After receiving this command, the chip will transmit data bits out of the program memory (user or configuration) currently addressed, starting with the second rising edge of the clock input. The data pin will go into Output mode on the second rising clock edge, and it will revert to Input mode (high-impedance) after the 16th rising edge. Because this is a 12-bit core, the two MSbs of the 14-bit word will be read as ‘0’s. If the program memory is code-protected (CP = 0), portions of the program memory will be read as zeros. See Section 5.0 “Code Protection” for details. FIGURE 3-3: READ DATA FROM PROGRAM MEMORY COMMAND TDLY2 1 2 3 4 1 0 5 1 6 2 ICSPCLK ICSPDAT 3 4 5 15 16 TDLY3 1 0 0 x x strt_bit TDLY1 TSET1 MSb stp_bit LSb THLD1 Input DS41257B-page 4 Output Input © 2007 Microchip Technology Inc. PIC12F510 3.1.2.3 Increment Address The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 3-4. It is not possible to decrement the address counter. To reset this counter, the user must either exit and re-enter Program/Verify mode or increment the PC from 0x7FF to 0x000. FIGURE 3-4: INCREMENT ADDRESS COMMAND TDLY2 1 2 3 4 5 Next Command 1 6 2 ICSPCLK 0 ICSPDAT 1 0 1 x x TSET1 THLD1 3.1.2.4 Begin Programming (Externally Timed) A Load command must be given before every Begin Programming command. Programming will begin after this command is received and decoded. Programming requires (TPROG) time and is terminated using an End Programming command. This command programs the current location, no erase is performed. FIGURE 3-5: BEGIN PROGRAMMING (EXTERNALLY TIMED) TPROG 1 2 3 0 0 0 4 5 6 x x End Programming Command 1 2 ICSPCLK ICSPDAT TSET1 © 2007 Microchip Technology Inc. 1 0 1 THLD1 DS41257B-page 5 PIC12F510 3.1.2.5 End Programming The End Programming command terminates the program process. A delay of TDIS (see Table 6-1) is required before the next command to allow the internal programming voltage to discharge (see Figure 3-6). FIGURE 3-6: END PROGRAMMING (EXTERNALLY TIMED) TDIS 1 2 3 4 0 1 1 1 5 6 Next Command 1 2 ICSPCLK ICSPDAT x TSET1 3.1.2.6 Bulk Erase Program Memory After this command is performed, the entire program memory and Configuration Word is erased. Note 1: A fully erased part will read ‘1’s in every program memory location. 2: The oscillator calibration bits are erased if a Bulk Erase is invoked. They must be read and saved prior to erasing the device and restored during the programming operation. Oscillator calibration bits are stored at the Reset vector as the operand of a MOVLW instruction. To perform a Bulk Erase of the program memory and configuration fuses, the following sequence must be performed (see Figure 3-12). 1. 2. 3. 4. 5. x THLD1 To perform a full device Bulk Erase of the program memory, configuration fuses, user IDs and backup OSCCAL, the following sequence must be performed (see Figure 3-13). 1. 2. 3. 4. 5. 6. 7. Read and save 0x3FF oscillator calibration bits and 0x404 backup OSCCAL bits into computer/ programmer temporary memory. Enter Program/Verify mode. Increment PC to 0x400 (first user ID location). Perform a Bulk Erase command. Wait TERA to complete Bulk Erase. Restore OSCCAL bits. Restore backup OSCCAL bits. Read and save 0x3FF oscillator calibration bits and 0x404 backup OSCCAL bits into computer/ programmer temporary memory. Enter Program/Verify mode. PC is set to Configuration Word address. Perform a Bulk Erase Program Memory command. Wait TERA to complete Bulk Erase. Restore OSCCAL bits. DS41257B-page 6 © 2007 Microchip Technology Inc. PIC12F510 TABLE 3-2: BULK ERASE RESULTS Program Memory Space PC = Configuration Memory Space Program Memory Reset Vector Configuration Word User ID Backup OSCCAL Configuration Word or Program Memory Space E E E U U First User ID Location E E E E E Legend: E = Erased, U = Unaffected FIGURE 3-7: BULK ERASE PROGRAM MEMORY COMMAND TERA 1 2 3 0 0 4 5 6 Next Command 1 2 ICSPCLK 1 ICSPDAT 1 x x TSET1 THLD1 © 2007 Microchip Technology Inc. DS41257B-page 7 PIC12F510 FIGURE 3-8: READING AND TEMPORARY SAVING OF THE OSCCAL CALIBRATION BITS Start Enter Programming Mode Increment Address No PC = 0x3FF? Yes Read Calibration Bits and Save in Computer/Programmer Temp. Memory Increment Address No PC = 0x404? Yes Read Backup OSCCAL Calibration Bits and Save in Computer/Programmer Temp. Memory Exit Programming Mode Done DS41257B-page 8 © 2007 Microchip Technology Inc. PIC12F510 FIGURE 3-9: RESTORING/PROGRAMMING THE OSCCAL CALIBRATION BITS Start Enter Programming Mode Increment Address No PC = 0x3FF? Yes Read Calibration Bits from Computer/Programmer Temp. Memory Write Calibration Bits back as the operand of a MOVLW instruction to 0x3FF Increment Address No PC = 0x404? Yes Read Backup OSCCAL Calibration Bits from Computer/Programmer Temp. Memory Write Backup OSCCAL Bits back to 0x404 Exit Programming Mode Done © 2007 Microchip Technology Inc. DS41257B-page 9 PIC12F510 FIGURE 3-10: PROGRAM FLOWCHART – PIC12F510 PROGRAM MEMORY Start Read and Save OSCCAL bits (Figure 3-8) Enter Programming Mode PC = 0x7FF (Config Word) Increment Address Bulk Erase Device PROGRAM CYCLE Load Data for Program Memory One Word Program Cycle Begin Programming Command (Externally timed) Read Data from Program Memory Data Correct? No Yes Increment Address Command No All Programming Locations Done? Report Programming Failure Wait TPROG End Programming Wait TDIS Yes Exit Programming Mode Restore 0SCCAL bits (Figure 3-9) Program Configuration Memory (Figure 3-11) Done DS41257B-page 10 © 2007 Microchip Technology Inc. PIC12F510 FIGURE 3-11: PROGRAM FLOWCHART – PIC12F510 CONFIGURATION MEMORY Start Enter Programming Mode PC = 0x7FF (Config Word) Load Data Command Programs Configuration Word One-Word Programming Cycle (see Figure 3-10) Read Data Command Data Correct? No Report Programming Failure Yes Increment Address Command No Address = 0x400? Yes Load Data Command Programs User IDs One-Word Programming Cycle (see Figure 3-10) Read Data Command Data Correct? No Report Programming Failure Yes Increment Address Command No Address = 0x404? Yes Exit Programming Mode Done © 2007 Microchip Technology Inc. DS41257B-page 11 PIC12F510 FIGURE 3-12: PROGRAM FLOWCHART – ERASE PROGRAM MEMORY, CONFIGURATION WORD Start Bulk Erase Device Read and Save OSCCAL bits (Figure 3-8) Enter Program/Verify mode PC = 0x7FF (Config Word) Wait TERA Restore OSCCAL bits (Figure 3-9) Exit Programming Mode Done DS41257B-page 12 © 2007 Microchip Technology Inc. PIC12F510 FIGURE 3-13: PROGRAM FLOWCHART – ERASE PROGRAM MEMORY, CONFIGURATION WORD AND USER ID Read and Save OSCCAL bits (Figure 3-8) Start Enter Program/Verify mode PC = 0x7FF (Config Word) Increment PC No PC = 0x400? (First User ID) Yes Bulk Erase Device Wait TERA Restore OSCCAL bits (Figure 3-9) Exit Programming Mode Done © 2007 Microchip Technology Inc. DS41257B-page 13 PIC12F510 4.0 CONFIGURATION WORD The PIC12F510 has several Configuration bits. These bits can be programmed (reads ‘0’) or left unchanged (reads ‘1’), to select various device configurations. REGISTER 4-1: — — CONFIGURATION WORD – PIC12F510 — — — — IOSCFS MCLRE CP WDTE FOSC1 bit 11 FOSC0 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 11-6 Unimplemented: Read as ‘1’ bit 5 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz INTOSC Speed 0 = 4 MHz INTOSC Speed bit 4 MCLRE: Master Clear Enable bit 1 = MCLR/VPP/GP3 pin functions as MCLR 0 = MCLR/VPP/GP3 pin functions as GP3, MCLR internally tied to VDD bit 3 CP: Code Protection bit 1 = Code protection off 0 = Code protection on bit 2 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0 FOSC1:FOSC0: Oscillator Selection bits 00 = LP oscillator 01 = XT oscillator 10 = INTOSC 11 = EXTRC DS41257B-page 14 x = Bit is unknown © 2007 Microchip Technology Inc. PIC12F510 5.0 CODE PROTECTION 5.3 Checksum Computation For the PIC12F510, once code protection is enabled, all program memory locations 0x40-0x3FE, read all ‘0’s. Program memory locations 0x000-0x03F and 0x3FF are always unprotected. The user ID locations, backup OSCCAL location and the Configuration Word read out in an unprotected fashion. It is possible to program the user ID locations, backup OSCCAL location and the Configuration Word after code-protect is enabled. 5.3.1 5.1 The checksum is calculated by summing the following: Disabling Code Protection It is recommended that the following procedure be performed before any other programming is attempted. It is also possible to turn code protection off (CP = 1) using this procedure. However, all data within the program memory will be erased when this procedure is executed, and thus, the security of the code is not compromised. To disable code-protect: a) b) Enter Program mode Execute Bulk Erase command (001001) Wait TERA c) 5.2 Note: Checksum is calculated by reading the contents of the PIC12F510 memory locations and adding up the opcodes up to the maximum user addressable location (e.g., 0x3FF for the PIC12F510). Any CARRY bits exceeding 16 bits are neglected. Finally, the Configuration Word (appropriately masked) is added to the checksum. Checksum computation for the PIC12F510 is shown in Table 5-1. • The contents of all program memory locations • The Configuration Word, appropriately masked • Masked user ID locations (when applicable) The Least Significant 16 bits of this sum is the checksum. The following table describes how to calculate the checksum for each device. Note: Program Memory CHECKSUM The checksum calculation differs depending on the code-protect setting. The Configuration Word and user ID locations can always be read regardless of the code-protect settings. Embedding Configuration Word and User ID Information in the Hex File To allow portability of code, the programmer is required to read the Configuration Word and user ID locations from the hex file when loading the hex file. If Configuration Word information was not present in the hex file, then a simple warning message may be issued. Similarly, while saving a hex file, Configuration Word and user ID information must be included. An option to not include this information may be provided. Microchip Technology Incorporated feels strongly that this feature is important for the benefit of the end customer. © 2007 Microchip Technology Inc. DS41257B-page 15 PIC12F510 TABLE 5-1: Device PIC12F510 CHECKSUM COMPUTATIONS – PIC12F510(1) Code-Protect Checksum* Blank Value 0x723 at 0 and Max Address OFF SUM[0x000:0x3FE] + CFGW & 0x03F 0xEC40 0xDA88 ON SUM[0x00:0x3F] + CFGW & 0x03F + SUM_ID 0xEC37 0xD1A3 Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a to b inclusive] SUM_ID = User ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant nibble. For example, ID0 = 0x1, ID1 = 0x2, ID2 = 0x3, ID3 = 0x4, then SUM_ID = 0x1234. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND Note 1: Checksum shown assumes that SUM_ID contains the unprotected checksum. DS41257B-page 16 © 2007 Microchip Technology Inc. PIC12F510 6.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS TABLE 6-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE AC/DC CHARACTERISTICS Sym. Characteristics Standard Operating Conditions (unless otherwise stated) Operating Temperature 10°C ≤ TA ≤ 40°C Operating Voltage 4.5V ≤ VDD ≤ 5.5V Min. Typ. Max. Units VDDPROG VDD level for programming operations, program memory 4.5 — 5.5 V VDDERA VDD level for Bulk Erase operations, program memory 4.5 — 5.5 V IDDPROG IDD level for programming operations, program memory — — 0.5 mA IDDERA IDD level for Bulk Erase operations, program memory — — 0.5 mA VPP High voltage on MCLR for Program/Verify mode entry 12.5 — 13.5 V IPP MCLR pin current during Program/Verify mode — — 0.45 mA TVHHR MCLR rise time (VSS to VIHH) for Program/ Verify mode entry — — 1.0 μs 5 — — μs 0.8 VDD — — V Conditions/ Comments General TPPDP Hold time after VPP↑ VIH1 (ICSPCLK, ICSPDAT) input high-level VIL1 (ICSPCLK, ICSPDAT) input low-level TSET0 ICSPCLK, ICSPDAT setup time before MCLR↑ (Program/Verify mode selection pattern setup time) THLD0 ICSPCLK, ICSPDAT hold time after MCLR↑ (Program/Verify mode selection pattern setup time) — — 0.2 VDD V 100 — — ns 5 — — μs Serial Program/Verify TSET1 Data in setup time before clock↓ 100 — — ns THLD1 Data in hold time after clock↓ 100 — — ns TDLY1 Data input not driven to next clock input (delay required between command/data or command/command) 1.0 — — μs TDLY2 Delay between clock↓ to clock↑ of next command or data 1.0 — — μs TDLY3 Clock↑ to data out valid (during Read Data) — — 80 ns (1) TERA Erase cycle time — — 10 TPROG Programming cycle time (externally timed) — — 2(1) ms TDIS Time delay for internal programming voltage discharge 100 — — μs TRESET Time between exiting Program mode with VDD and VPP at GND and then re-entering Program mode by applying VDD. — 10 — ms Note 1: Minimum time to ensure that function completes successfully over voltage, temperature and device variations. © 2007 Microchip Technology Inc. ms DS41257B-page 17 PIC12F510 NOTES: DS41257B-page 18 © 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. 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