PIC16(L)F72X Memory Programming

PIC16(L)F72X
PIC16(L)F72X Memory Programming Specification
This document includes the
programming specifications for the
following devices:
The PIC16F72X devices operate from 1.8 to 5.5 volts
and the PIC16LF72X devices operate from 1.8 to 3.6
volts. All other aspects of the PIC16F72X with regards
to the PIC16LF72X devices are identical.
• PIC16F722
• PIC16F722A
• PIC16F723
• PIC16F723A
• PIC16F724
• PIC16F726
• PIC16F727
• PIC16LF722
• PIC16LF722A
• PIC16LF723
• PIC16LF723A • PIC16LF724
• PIC16LF726
• PIC16LF727
1.0
1.1
PIC16F72X and PIC16LF72X devices require one
power supply for VDD and one for VPP. (See
Section 8.0 “Electrical Specifications” for more
details.)
1.2
OVERVIEW
Pin Utilization
Five pins are needed for ICSP™ programming. The
pins are listed in Table 1-1.
The PIC16F72X and PIC16LF72X devices are
programmed using In-Circuit Serial Programming™
(ICSP™). This programming specification applies to
the PIC16F72X and PIC16LF72X devices in all
packages.
TABLE 1-1:
Hardware Requirements
PIN DESCRIPTIONS DURING PROGRAMMING
During Programming
Pin Name
Function
Pin Type
Pin Description
RB6
ICSPCLK
I
RB7
ICSPDAT
I/O
Data Input/Output – Schmitt Trigger Input
Program/Verify mode
P(1)
Program Mode Select/Programming Power Supply
VDD
VDD
P
Power Supply
VSS
VSS
P
Ground
MCLR/VPP
Clock Input – Schmitt Trigger Input
Legend: I = Input, O = Output, P = Power
Note 1: To activate the Program/Verify mode, high voltage needs to be applied to MCLR/VPP input. Since the
MCLR/VPP is used to provide high voltage during programming, the programmer must be able to supply
current on this pin.
 2011 Microchip Technology Inc.
DS41332D-page 1
PIC16(L)F72X
2.0
DEVICE PINOUTS
The pin diagrams for the PIC16(L)F72X family are
shown in Figure 2-1 through Figure 2-6. The pins that
are required for programming are listed in Table 1-1
and shown in bold lettering in the pin diagrams.
FIGURE 2-1:
PDIP/SOIC/SSOP DIAGRAM FOR PIC16F722/722A/723/723A/726 AND
PIC16LF722/722A/723/723A/726
28-Pin SOIC, SSOP, Skinny PDIP
DS41332D-page 2
1
28
RB7/ICSPDAT
SS/AN0/RA0
2
27
RB6/ICSPCLK
AN1/RA1
3
26
RB5/AN13/T1G
25
RB4/AN11
24
23
RB3/AN9/CCP2
22
21
RB1/AN10
RB0/AN12/INT
20
VDD
19
VSS
18
RC7/RX/DT
17
RC6/TX/CK
AN2/RA2
4
VREF/AN3/RA3
5
T0CKI/RA4
6
PIC16(L)F/722/722A/723/723A/726
VPP/MCLR/RE3
RB2/AN8
VCAP/SS/AN4/RA5
VSS
7
CLKI/OSC1/RA7
9
CLKO/OSC2/RA6
10
T1CKI/T1OSO/RC0
11
CCP2/T1OSI/RC1
12
CCP1/RC2
SCL/SCK/RC3
13
16
RC5/SDO
14
15
RC4/SDI/SDA
8
 2011 Microchip Technology Inc.
PIC16(L)F72X
FIGURE 2-2:
QFN PACKAGE DIAGRAM FOR PIC16F722/722A/723/723A/726 AND
PIC16LF722/722A/723/723A/726
 2011 Microchip Technology Inc.
RE3/MCLR/VPP
RB7/ICSPDAT
RB6/ICSPCLK
RB5/AN13/T1G
RB4/AN11
21
20
19
18
17
16
15
RB3/AN9/CCP2
RB2/AN8
RB1/AN10
RB0/AN12/INT
VDD
VSS
RC7/RX/DT
CCP1/RC2
SCL/SCK/RC3
SDA/SDI/RC4
SDO/RC5
CK/TX/RC6
1
2
3
4
5
6
7
T1CKI/T1OSO/RC0
CCP2/T1OSI/RC1
AN2/RA2
VREF/AN3/RA3
T0CKI/RA4
VCAP/SS/AN4/RA5
VSS
CLKI/OSC1/RA7
CLKO/OSC2/RA6
8
9
10
PIC16(L)F/722/722A/
11
723/723A/726
12
13
14
28
27
26
25
24
23
22
RA1/AN1
RA0/AN0/SS
28-Pin QFN, UQFN
DS41332D-page 3
PIC16(L)F72X
FIGURE 2-3:
PDIP PACKAGE DIAGRAM FOR PIC16F724/727 AND PIC16LF724/727
40-Pin PDIP
VPP/MCLR/RE3
1
40
RB7/ICSPDAT
SS/AN0/RA0
2
39
RB6/ICSPCLK
AN1/RA1
3
38
RB5/AN13/T1G
4
37
RB4/AN11
5
36
RB3/AN9/CCP2
T0CKI/RA4
6
35
RB2/AN8
VCAP/SS/AN4/RA5
AN5/RE0
7
34
33
RB1/AN10
RB0/AN12/INT
AN6/RE1
9
32
VDD
31
VSS
30
RD7
29
RD6
RD5
AN7/RE2
8
10
VDD
11
VSS
12
CLKI/OSC1/RA7
13
28
CLKO/OSC2/RA6
14
27
RD4
T1CKI/T1OSO/RC0
15
26
RC7/RX/DT
CCP2/T1OSI/RC1
16
25
RC6/TX/CK
CCP1/RC2
SCL/SCK/RC3
17
24
RC5/SDO
18
23
RD0
19
22
RC4/SDI/SDA
RD3
RD1
20
21
RD2
QFN PACKAGE DIAGRAM FOR PIC16F724/727 AND PIC16LF724/727
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
RA6/OSC2/CLKO
RA7/OSC1/CLKI
VSS
VSS
NC
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/SS(2)/VCAP
RA4/T0CKI
CCP2(1)/AN9/RB3
NC
AN11/RB4
T1G/AN13/RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
SS(2)/AN0/RA0
AN1/RA1
AN2/RA2
VREF/AN3/RA3
DT/RX/RC7
RD4
RD5
RD6
RD7
VSS
VDD
VDD
INT/AN12/RB0
AN10/RB1
AN8/RB2
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3
RD2
RD1
RD0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
RC0/T1OSO/T1CKI
44-Pin QFN
12
13
14
15
16
17 PIC16(L)F724/727
18
19
20
21
22
FIGURE 2-4:
PIC16(L)F724/727
AN2/RA2
VREF/AN3/RA3
DS41332D-page 4
 2011 Microchip Technology Inc.
PIC16(L)F72X
FIGURE 2-5:
TQFP PACKAGE DIAGRAM FOR PIC16F724/727 AND PIC16LF724/727
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
RC0/T1OSO/T1CKI
RA6/OSC2/CLKO
RA7/OSC1/CLKI
VSS
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/SS/VCAP
RA4/T0CKI
NC
NC
AN11/RB4
T1G/AN13/RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
SS/AN0/RA0
AN1/RA1
AN2/RA2
VREF/AN3/RA3
RC7/RX/DT
RD4
RD5
RD6
RD7
VSS
VDD
INT/AN12/RB0
AN10/RB1
AN8/RB2
CCP2/AN9/RB3
PIC16(L)F724/727
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3
RD2
RD1
RD0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
44-Pin TQFP
 2011 Microchip Technology Inc.
DS41332D-page 5
PIC16(L)F72X
FIGURE 2-6:
40-PIN UQFN PACKAGE DIAGRAM FOR PIC16F724/727
40
39
38
37
36
35
34
33
32
31
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/CPS11
RD2/CPS10
RD1/CPS9
RD0/CPS8
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2(1)
40-Pin UQFN
1
2
3
4
5
6
7
8
9
10
PIC16F724/727
30
29
28
27
26
25
24
23
22
21
RC0/T1OSO/T1CKI
RA6/OSC2/CLKO/VCAP
RA7/OSC1/CLKI
VSS
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/CPS7/SS(2)/VCAP
RA4/CPS6/T0CKI
CCP2(1)/CPS3/AN9/RB3
CPS4/AN11/RB4
T1G/CPS5/AN13/RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
VCAP/SS(2)/AN0/RA0
AN1/RA1
AN2/RA2
VREF/AN3/RA3
11
12
13
14
15
16
17
18
19
20
DT/RX/RC7
CPS12/RD4
CPS13/RD5
CPS14/RD6
CPS15/RD7
VSS
VDD
INT/CPS0/AN12/RB0
CPS1/AN10/RB1
CPS2/AN8/RB2
DS41332D-page 6
 2011 Microchip Technology Inc.
PIC16(L)F72X
3.0
MEMORY MAP
The memory for the PIC16(L)F72X devices is broken
into two sections: program memory and configuration
memory. Only the size of the program memory
changes between devices; the configuration memory
remains the same.
FIGURE 3-1:
PIC16(L)F722/722A PROGRAM MEMORY MAPPING
2 KW
0000h
Implemented
07FFh
Program Memory
2000h
User ID Location
2001h
User ID Location
2002h
User ID Location
2003h
User ID Location
2004h
Reserved
2005h
Reserved
2006h
Device ID
2007h
Configuration Word 1
2008h
Configuration Word 2
2009h
Calibration Word 1
200Ah
Calibration Word 2
Maps to
0-7FF
1FFFh
2000h
Implemented
2200h
Maps to
2000-21FFh
Configuration Memory
3FFFh
200Bh-20FFh
 2011 Microchip Technology Inc.
Reserved
DS41332D-page 7
PIC16(L)F72X
FIGURE 3-2:
PIC16(L)F723/723A/724 PROGRAM MEMORY MAPPING
4 KW
0000h
Implemented
0FFFh
Program Memory
2000h
User ID Location
2001h
User ID Location
2002h
2003h
User ID Location
User ID Location
2004h
Reserved
2005h
Reserved
2006h
Device ID
2007h
Configuration Word 1
2008h
Configuration Word 2
2009h
Calibration Word 1
200Ah
Calibration Word 2
Maps to
0-FFF
1FFFh
2000h
Implemented
2200h
Maps to
2000-21FFh
Configuration Memory
3FFFh
200Bh-20FFh
DS41332D-page 8
Reserved
 2011 Microchip Technology Inc.
PIC16(L)F72X
FIGURE 3-3:
PIC16(L)F726/727 PROGRAM MEMORY MAPPING
8 KW
0000h
Implemented
2000h
User ID Location
2001h
User ID Location
2002h
User ID Location
2003h
User ID Location
2004h
Reserved
2005h
Reserved
2006h
Device ID
2007h
Configuration Word 1
2008h
Configuration Word 2
2009h
Calibration Word 1
200Ah
Calibration Word 2
1FFFh
2000h
Program Memory
Implemented
2200h
Maps to
2000-21FFh
Configuration Memory
3FFFh
200Bh-20FFh
3.1
Reserved
User ID Location
A user may store identification information (user ID) in
four designated locations. The user ID locations are
mapped to 2000h-2003h. Each location is 14 bits in
length. Code protection has no effect on these memory
locations. Each location may be read with code
protection enabled or disabled.
Note:
3.2
Device ID
The device ID word for the PIC16F72X and the
PIC16LF72X devices is located at 2006h. This location
cannot be erased or modified.
MPLAB® IDE only displays the 7 Least
Significant bits (LSb) of each user ID
location, the upper bits are not read. It is
recommended that only the 7 LSbs be
used if MPLAB IDE is the primary tool
used to read these addresses.
 2011 Microchip Technology Inc.
DS41332D-page 9
PIC16(L)F72X
TABLE 3-1:
DEVICE ID VALUES
DEVICE ID VALUES
DEVICE
DEV
REV
PIC16F722
01 1000 100
x xxxx
PIC16F722A
01 1011 001
x xxxx
PIC16F723
01 1000 011
x xxxx
PIC16F723A
01 1011 000
x xxxx
PIC16F724
01 1000 010
x xxxx
PIC16F726
01 1000 001
x xxxx
PIC16F727
01 1000 000
x xxxx
PIC16LF722
01 1001 100
x xxxx
PIC16LF722A
01 1011 011
x xxxx
PIC16LF723
01 1001 011
x xxxx
PIC16LF723A
01 1011 010
x xxxx
PIC16LF724
01 1001 010
x xxxx
PIC16LF726
01 1001 001
x xxxx
PIC16LF727
01 1001 000
x xxxx
3.3
Configuration Words
The PIC16(L)F72X devices have two Configuration
Words, Configuration Word 1 (2007h) and
Configuration Word 2 (2008h). The individual bits
within these Configuration Words are used to enable or
disable device functions such as the Brown-out Reset,
code protection and Power-up Timer.
3.4
Calibration Words
For the PIC16(L)F72X devices, the 16 MHz internal
oscillator (INTOSC), and the Brown-out Reset (BOR),
are factory calibrated and stored in Calibration Words 1
and 2 (2009h and 200Ah).
The Calibration Words do not participate in erase
operations. The device can be erased without affecting
the Calibration Words.
DS41332D-page 10
 2011 Microchip Technology Inc.
PIC16(L)F72X
REGISTER 3-1:
R/P-1
DEBUG
(1)
CONFIGURATION WORD 1
R/P-1
U-1(2)
R/P-1
R/P-1
R/P-1
U-1(2)
PLLEN
—
BORV
BOREN1
BOREN0
—
bit 13
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
bit 0
Legend:
P = Programmable
x = Bit is unknown
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
-n = Default value
‘1’ = Bit is written to ‘1’
‘0’ = Bit is written to ‘0’
bit 13
DEBUG: Debugger mode bit(1)
1 = Background debugger is disabled
0 = Background debugger is enabled
bit 12
PLLEN: INTOSC PLL Enable bit
1 = INTOSC frequency is 16 MHz
0 = INTOSC frequency is 500 kHz
bit 11
Unimplemented: Read as ‘1’
bit 10
BORV: Brown-out Reset Voltage Selection bit
1 = Brown-out Reset Voltage (VBOR) set to 1.9V
0 = Brown-out Reset Voltage (VBOR) set to 2.5V
bit 9-8
BOREN<1:0>: Brown-out Reset Enable bits
0x = Brown-out Reset disabled
10 = Brown-out Reset enabled during operation and disabled in Sleep
11 = Brown-out Reset enabled
bit 7
Unimplemented: Read as ‘1’
bit 6
CP: Flash Program Memory Code Protection bit
For PIC16F/LF726/727:
0 = 0000h to 1FFFh code protection on
1 = Code protection off
For PIC16F/LF723/723A/724:
0 = 0000h to 0FFFh code protection on
1 = Code protection off
For PIC16F/LF722/722A:
0 = 0000h to 07FFh code protection on
1 = Code protection off
bit 5
MCLRE: RE3/MCLR/VPP Pin Function Select bit
1 = RE3/MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = RE3/MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up disabled.
bit 4
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
Note 1:
2:
DEBUG bit is ignored when code-protect is enabled (CP = 0).
MPLAB® IDE masks unimplemented Configuration bits to ‘0’.
 2011 Microchip Technology Inc.
DS41332D-page 11
PIC16(L)F72X
REGISTER 3-1:
bit 2-0
CONFIGURATION WORD 1 (CONTINUED)
FOSC<2:0>: Oscillator Selection bits
111 = RC with CLKOUT oscillator: CLKO function on RA6/OSC2/CLKO pin, RC on RA7/OSC1/CLKI
110 = RC NO CLKOUT oscillator: I/O function on RA6/OSC2/CLKO pin, RC on RA7/OSC1/CLKI
101 = INTOSC with CLKOUT oscillator: CLKO function on RA6/OSC2/CLKO pin, I/O function on
RA7/OSC1/CLKI
100 = INTOSC NO CLKOUT oscillator: I/O function on RA6/OSC2/CLKO pin, I/O function on
RA7/OSC1/CLKI
011 = EC oscillator: I/O function on RA6/OSC2/CLKO pin, CLKI on RA7/OSC1/CLKI
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI
Note 1:
2:
DEBUG bit is ignored when code-protect is enabled (CP = 0).
MPLAB® IDE masks unimplemented Configuration bits to ‘0’.
REGISTER 3-2:
CONFIGURATION WORD 2
U-1(1)
U-1(1)
U-1(1)
U-1(1)
U-1(1)
U-1(1)
U-1(1)
—
—
—
—
—
—
—
U-1(1)
R/P-1
R/P-1
U-1(1)
U-1(1)
U-1(1)
U-1(1)
—
VCAPEN1
VCAPEN0
—
—
—
—
bit 13
bit 0
Legend:
P = Programmable
x = Bit is unknown
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
-n = Default value
‘1’ = Bit is written to ‘1’
‘0’ = Bit is written to ‘0’
bit 13-6
Unimplemented: Read as ‘1’
bit 5-4
VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits
For PIC16LF72X:
These bits are ignored. All VCAP pin functions are disabled.
For PIC16F72X:
00 = VCAP functionality is enabled on RA0
01 = VCAP functionality is enabled on RA5
10 = VCAP functionality is enabled on RA6
11 = All VCAP pin functions are disabled
bit 3-0
Unimplemented: Read as ‘1’
Note 1:
MPLAB® IDE masks unimplemented Configuration bits to ‘0’.
DS41332D-page 12
 2011 Microchip Technology Inc.
PIC16(L)F72X
4.0
PROGRAM/VERIFY MODE
The VPP-first entry prevents the device from executing
code prior to entering Program/Verify mode (e.g., When
the Configuration Word has MCLR disabled (MCLRE = 0),
the power-up time disabled (PWRTE = 0), and the internal
oscillator is selected (FOSC = 10x), VPP-first entry mode is
strongly recommended for this reason. ICSPCLK or
ICSPDAT is driven high by the user code. See the timing
diagram in Figure 8-4.
In Program/Verify mode, the program memory and the
configuration memory can be accessed and programmed in serial fashion. ICSPDAT and ICSPCLK
are used for the data and the clock, respectively. All
commands and data words are transmitted LSb first.
Data changes on the rising edge of the ICSPCLK and
latched on the falling edge. In Program/Verify mode
both the ISCPDAT and ICSPCLK are Schmitt Trigger
inputs. The sequence that enters the device into
Program/Verify mode places all other logic into the
Reset state. Upon entering Program/Verify mode, all
I/O’s are automatically configured as high-impedance
inputs and the Program Counter (PC) is cleared.
4.1
4.1.2
VDD–FIRST ENTRY MODE
To enter Program/Verify mode via the VDD-first method
the following sequence must be followed:
1.
2.
Program/Verify Mode Entry and
Exit
Hold ICSPCLK and ICSPDAT low.
Raise the voltage on VDD from 0V to the desired
operating voltage.
Raise the voltage on MCLR from below VDD to
VPP.
3.
The VDD-first method is useful when programming the
device when VDD is already applied, for it is not
necessary to disconnect VDD to enter Program/Verify
mode. See the timing diagram in Figure 8-5.
There are 2 different methods of entering Program/
Verify mode:
• VPP – First entry mode
• VDD – First entry mode
4.1.3
4.1.1
VPP – FIRST ENTRY MODE
To exit Program/Verify mode take MCLR to VDD or
lower.
To enter Program/Verify mode via the VPP-first method
the following sequence must be followed:
1.
2.
3.
4.2
Hold ICSPCLK and ICSPDAT low. All other pins
should be unpowered.
Raise the voltage on MCLR from 0V to VIHH.
Raise the voltage on VDD from 0V to the desired
operating voltage.
TABLE 4-1:
PROGRAM/VERIFY MODE EXIT
Program/Verify Commands
The PIC16F72X and PIC16LF72X devices implement
10 programming commands, each six bits in length.
The commands are summarized in Table 4-1.
Commands that have data associated with them are
specified to have a minimum delay of TDLY between the
command and the data. After this delay 16 clocks are
required to either clock in or clock out the 14-bit data
word. The first clock is for the Start bit and the last clock
is for the Stop bit.
COMMAND MAPPING FOR PIC16F72X
Mapping
Data/Note
Command
Binary (MSb … LSb)
Hex
Load Configuration
x
0
0
0
0
0
00h
0, data (14), 0
Load Data For Program Memory
x
0
0
0
1
0
02h
0, data (14), 0
Read Data From Program Memory
x
0
0
1
0
0
04h
0, data (14), 0
Increment Address
x
0
0
1
1
0
06h
Reset Address
x
1
0
1
1
0
16h
Begin Internally Timed Programming
x
0
1
0
0
0
08h
Begin Externally Timed Programming
x
1
1
0
0
0
18h
End Externally Timed Programming
x
0
1
0
1
0
0Ah
Bulk Erase Program Memory
x
0
1
0
0
1
09h
Internally Timed
Row Erase Program Memory
x
1
0
0
0
1
11h
Internally Timed
 2011 Microchip Technology Inc.
DS41332D-page 13
PIC16(L)F72X
4.2.1
LOAD CONFIGURATION
After issuing the Load Configuration command, use the
Increment Address command until the proper address
to be programmed is reached. The address is then
programmed by issuing either the Begin Internally
Timed Programming or Begin Externally Timed
Programming command.
The Load Configuration command is used to access
the configuration memory (user ID locations,
Configuration Words, Calibration Words). The Load
Configuration command sets the Program Counter
(PC) to address 2000h and loads the data latches with
one word of data.
FIGURE 4-1:
After the configuration memory has been accessed by
the Load Configuration command, the only way to get
back to the program memory is to exit Program/Verify
mode or issue the Reset Address command.
LOAD CONFIGURATION
1
2
5
4
3
2
1
6
16
15
TDLY
ICSPCLK
ICSPDAT
4.2.2
0
0
0
0
X
0
0
LSb
1
2
MSb 0
LOAD DATA FOR PROGRAM
MEMORY
The Load Data for Program Memory command is used
to load one 14-bit word into the data latches. The word
in placed into program memory after the Begin
Internally Timed Programming or Begin Externally
Timed Programming command is issued.
FIGURE 4-2:
LOAD DATA FOR PROGRAM MEMORY
1
2
3
4
5
6
15
16
TDLY
ICSPCLK
ICSPDAT
DS41332D-page 14
0
1
0
0
0
X
0
LSb
MSb 0
 2011 Microchip Technology Inc.
PIC16(L)F72X
4.2.3
READ DATA FROM PROGRAM
MEMORY
After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently accessed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the first falling clock edge, and
it will revert to Input mode (high-impedance) after the
16th falling edge of the clock. If the program memory is
code-protected (CP), the data will be read as zeros.
FIGURE 4-3:
READ DATA FROM PROGRAM MEMORY
1
2
5
4
3
6 TDLY
1
2
X
0
LSb
15
16
MSb
0
ICSPCLK
ICSPDAT
0
0
1
0
0
4.2.4
Input
Output
Input
INCREMENT ADDRESS
The Program Counter (PC) is incremented when this
command is received. It is not possible to decrement
the PC. To reset this counter, the user must exit
Program/Verify mode and re-enter it or use the Reset
Address command.
FIGURE 4-4:
INCREMENT ADDRESS
Next Command
1
2
4
3
1
6
5
2
3
TDLY
ICSPCLK
0
1
1
0
ICSPDAT
PC
 2011 Microchip Technology Inc.
0
X
X
X
X
PC + 1
DS41332D-page 15
PIC16(L)F72X
4.2.5
RESET ADDRESS
After receiving this command the Program Counter
(PC) is set to 0000h. The PC will be reset independent
of addressing the program memory or the configuration
memory.
FIGURE 4-5:
RESET ADDRESS
Next Command
1
2
5
4
3
1
6
2
3
TDLY
ICSPCLK
0
1
1
0
1
X
X
X
X
ICSPDAT
0000h
PC
4.2.6
BEGIN INTERNALLY TIMED
PROGRAMMING
A Load Configuration or Load Data for Program
Memory command must be given before every Begin
Programming command. Programming of the
addressed memory will begin after this command is
received. An internal timing mechanism executes the
write. The user must allow for the program cycle time
for the programming to complete. The address that is
being programmed is not erased prior to being
programmed.
The End Externally Timed Programming command is
not needed when the Begin Internally Timed
Programming is used to start the programming.
FIGURE 4-6:
BEGIN INTERNALLY TIMED PROGRAMMING
1
2
4
3
5
Next Command
2
1
3
6
TPINT
ICSPCLK
ICSPDAT
DS41332D-page 16
0
0
0
1
0
X
X
X
X
 2011 Microchip Technology Inc.
PIC16(L)F72X
4.2.7
BEGIN EXTERNALLY TIMED
PROGRAMMING
A Load Configuration, Load Data for Program Memory
or Load Data for Data Memory command must be given
before every Begin Programming command.
Programming of the addressed memory will begin after
this command is received. To complete the
programming of the address, the End Externally Timed
Programming command must be sent in the specified
time window defined by TPEXT.
The Begin Externally Timed Programming command
cannot be used for programming the Configuration
Words.
FIGURE 4-7:
BEGIN EXTERNALLY TIMED PROGRAMMING
End Externally Timed Programming
Command
1
2
4
3
5
6
1
2
3
TPEXT
ICSPCLK
0
ICSPDAT
4.2.8
0
0
1
0
X
1
1
0
END EXTERNALLY TIMED
PROGRAMMING
This command is required after a Begin Externally
Timed Programming command is given. This
command must be sent within the time window
specified by TPEXT after the Begin Externally Timed
Programming command is sent.
After sending the End Externally Timed Programming
command, an additional delay (TDIS) is required before
sending the next command. This delay is longer than
the delay ordinarily required between other commands.
FIGURE 4-8:
END EXTERNALLY TIMED PROGRAMMING
1
2
5
4
3
Next Command
2
1
3
6
TDIS
ICSPCLK
ICSPDAT
 2011 Microchip Technology Inc.
0
1
0
1
1
X
X
X
X
DS41332D-page 17
PIC16(L)F72X
4.2.9
BULK ERASE PROGRAM MEMORY
After receiving the Bulk Erase Program Memory
command, the erase will not complete until the time
interval, TERAB, has expired.
The Bulk Erase Program Memory command performs
two different functions, dependant on the current state
of the Program Counter (PC).
Note 1: The code protection Configuration bit
(CP) has no effect on the Bulk Erase
Program Memory command.
PC 0000h-1FFFh:
Program Memory is erased
Configuration words are erased
Note 2: A Bulk Erase Program Memory command should not be issued when the PC
is greater than 2008h.
PC 2000h-2008h:
Program Memory is erased
Configuration Words are erased
User ID Locations are erased
FIGURE 4-9:
BULK ERASE PROGRAM MEMORY
1
2
5
4
3
Next Command
1
2
3
6
TERAB
ICSPCLK
ICSPDAT
4.2.10
1
0
0
0
1
X
X
X
X
ROW ERASE PROGRAM MEMORY
A row of program memory consists of 32 consecutive
14-bit words. A row is addressed by the Program
Counter PC<13:5>. The Row Erase Program Memory
command can be used to erase an individual row. If the
program memory is code-protected the Row Erase
Program Memory command will be ignored. When the
PC is 2000h-2008h the Row Erase Program Memory
command will only erase the user ID locations,
independent of the setting of the CP Configuration bit.
After receiving the Row Erase Program Memory
command, the erase will not complete until the time
interval, TERAR, has expired.
FIGURE 4-10:
ROW ERASE PROGRAM MEMORY
1
2
5
4
3
Next Command
2
1
3
6
TERAR
ICSPCLK
ICSPDAT
DS41332D-page 18
1
0
0
0
1
X
X
X
X
 2011 Microchip Technology Inc.
PIC16(L)F72X
5.0
PROGRAMMING ALGORITHMS
The PIC16(L)F72X devices have the capability of
storing eight 14-bit words in its data latches. The data
latches are internal to the PIC16(L)F72X devices and
are only used for programming. The data latches allow
the user to program up to eight program words with a
single Begin Externally Timed Programming or Begin
Internally Timed Programming command. The Load
Program Data or the Load Configuration Word
command is used to load a single data latch. The data
latch will hold the data until Begin Externally Timed
Programming or Begin Internally Timed Programming
command is given.
FIGURE 5-1:
The data latches are aligned with the 3 LSb of the PC.
The address of the PC, at the time the Begin Externally
Timed Programming or Begin Internally Timed
Programming command is given, will determine which
location(s) in memory are written. Writes cannot cross
a physical eight-word boundary. For example,
attempting to write from PC 0002h-0009h will result in
data being written to 0008h-000Fh.
If more than 8 data latches are written without a Begin
Externally Timed Programming or Begin Internally
Timed Programming command the data in the data
latches will be overwritten. The following diagrams
show the recommended flowcharts for programming.
ONE-WORD PROGRAMMING FLOWCHART
Start
Bulk Erase
Program
Memory(1)
One-word
Program Cycle
Increment
Address
Command
No
All Locations
Done?
Program Cycle
Load Data
for
Program Memory
Begin
Programming
Command
(Internally timed)
Begin
Programming
Command
(Externally timed)
Wait TPINT
Wait TPEXT
Yes
Done
End
Programming
Wait TDIS
Note 1:
This step is optional if the device has already been erased or has not been previously programmed.
 2011 Microchip Technology Inc.
DS41332D-page 19
PIC16(L)F72X
FIGURE 5-2:
EIGHT-WORD PROGRAMMING FLOWCHART
Program Cycle
Load Data
for
Program Memory
Data
Latch 1
Increment
Address
Command
Start
Bulk Erase
Program
Memory(1)
Load Data
for
Program Memory
Data
Latch 2
Eight-word
Program Cycle
Increment
Address
Command
No
Increment
Address
Command
All Locations
Done?
Yes
Done
Load Data
for
Program Memory
Data
Latch 8
Begin
Programming
Command
(Internally timed)
Begin
Programming
Command
(Externally timed)
Wait TPINT
Wait TPEXT
End
Programming
Wait TDIS
Note 1:
DS41332D-page 20
This step is optional if the device is erased or not previously programmed.
 2011 Microchip Technology Inc.
PIC16(L)F72X
FIGURE 5-3:
PROGRAM FLOWCHART – PIC16F72X CONFIGURATION MEMORY
Start
Load
Configuration
Bulk Erase
Program
Memory(1)
Program Cycle
Load Data
for
Program Memory
One-word
Program Cycle
(User ID)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
No
Address =
2004h?
Begin
Programming
Command
(Internally timed)
Begin
Programming
Command
(Externally timed)
Wait TPINT
Wait TPEXT
End
Programming
Yes
Increment
Address
Command
Wait TDIS
Increment
Address
Command
Increment
Address
Command
One-word
Program Cycle
(Config Word 1)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
One-word
Program Cycle
(Config Word 2)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Done
Note 1:
This step is optional if the device is erased or not previously programmed.
 2011 Microchip Technology Inc.
DS41332D-page 21
PIC16(L)F72X
FIGURE 5-4:
VERIFY FLOWCHART
Start
Enter
Programming Mode
Bulk Erase
Device
Write Program
Memory
Write User IDs
Verify Program Memory
Verify User IDs
Write Configuration
Words
Verify Configuration
Words
Exit Programming Mode
Done
DS41332D-page 22
 2011 Microchip Technology Inc.
PIC16(L)F72X
6.0
CODE PROTECTION
Code protection is controlled using the CP bit in
Configuration Word 1. When code protection is
enabled, all program memory locations (0000h-1FFFh)
read as all ‘0’. Further programming is disabled for the
program memory (0000h-1FFFh).
The user ID locations and Configuration Words can be
programmed and read out regardless of the code
protection settings.
6.1
Enabling Code Protection
Code protection is enabled by programming the CP bit
in Configuration Word 1 to ‘0’.
6.2
Disabling Code Protection
The only way to disable code protection is to use the
Bulk Erase Program Memory command.
 2011 Microchip Technology Inc.
DS41332D-page 23
PIC16(L)F72X
7.0
HEX FILE USAGE
7.2
In the hex file there are two bytes per program word
stored in the Intel® INH8M hex format. Data is stored
LSB first, MSB second. Because there are two bytes
per word, the addresses in the hex file are 2x the
address in program memory. (Example: The
Configuration Word 1 is stored at 2007h on the
PIC16(L)F72X. In the hex file this will be at location
400Eh-400Fh).
7.1
Configuration Word
To allow portability of code, it is strongly recommended
that the programmer is able to read the Configuration
Words and user ID locations from the hex file. If the
Configuration Words information was not present in the
hex file, a simple warning message may be issued.
Similarly, while saving a hex file, Configuration Words
and user ID information should be included.
EXAMPLE 7-1:
PIC16F726
Device ID and Revision
If a device ID is present in the hex file at 400Ch-400Dh
(2006h on the part), the programmer should verify the
device ID/revision against the value read from the part.
On a mismatch condition, the programmer should
generate a warning message.
7.3
Checksum Computation
The checksum is calculated by two different methods,
dependent on the setting of the CP Configuration bit.
7.3.1
CODE PROTECTION DISABLED
With the code protection disabled, the checksum is
computed by reading the contents of the PIC16(L)F72X
program memory locations and adding up the program
memory data, starting at address 0000h, up to the maximum user addressable location (e.g., 1FFFH for the
PIC16F726). Any Carry bit exceeding 16 bits are
neglected. Additionally, the relevant bits of the Configuration Words are added to the checksum. All unused
Configuration bits are masked to ‘0’.
CHECKSUM COMPUTED WITH CODE PROTECTION DISABLED, PIC16F726,
BLANK DEVICE
Sum of Memory addresses 0000h-1FFFh
E000h
Configuration Word 1
2AC3h
Configuration Word 1 mask
377Fh
Configuration Word 2
3FEFh
Configuration Word 2 mask
Checksum
0030h
= E000h + (2AC3h and 377Fh) + (3FEFh and 0030h)
= E000h + 2243h + 0020h
= 0263h
DS41332D-page 24
 2011 Microchip Technology Inc.
PIC16(L)F72X
7.3.2
CODE PROTECTION ENABLED
With the code protection enabled, the checksum is
computed in the following manner. The Configuration
Words are summed (all unused Configuration bits are
masked to ‘0’) with the Least Significant nibble of the
user ID’s.
EXAMPLE 7-2:
CHECKSUM COMPUTED WITH CODE PROTECTION ENABLED, PIC16F726,
BLANK DEVICE
PIC16F726 Configuration Word 1
2A83h
Configuration Word 1 mask
377Fh
Configuration Word 2
3FEFh
Configuration Word 2 mask
0030h
User ID (2000h)
0123h
User ID (2001h)
4567h
User ID (2002h)
89ABh
User ID (2003h)
CDEFh
Sum of User IDs = (0003h and 000Fh) << 12 + (0007h and 000Fh) << 8 +
(000Bh and 000Fh) << 4 + (000Fh and 000Fh)
= 3000h + 0700h +00B0h + 000Fh
= 37BFh
Checksum
= (2A83h and 377Fh) + (3FEFh and 0030h) + Sum of User IDs
= 2203h + 0020h + 37BFh
= 59E2h
 2011 Microchip Technology Inc.
DS41332D-page 25
PIC16(L)F72X
8.0
ELECTRICAL SPECIFICATIONS
Refer to the device specific data sheet for absolute
maximum ratings.
TABLE 8-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE
Standard Operating Conditions (unless otherwise stated)
Operating Temperature +10°C  TA +40°C
AC/DC CHARACTERISTICS
Sym.
Characteristics
Min.
Type.
Max.
Units
Conditions/Comments
Supply Voltages and currents
VDD
IDDI
IDDA
VIHH
TVHHR
IPP
VIH
VIL
VDD
PIC16F72X (excluding Bulk Erase)
PIC16LF72X (excluding Bulk Erase)
PIC16(L)F72X Bulk Erase
Current on VDD, Idle
Current on VDD, program cycle or
Bulk Erase in progress
VPP
1.8
1.8
2.7
—
—
5.5
3.6
—
1.0
V
V
V
mA
5.0
mA
High voltage on MCLR/VPP for
Program/Verify mode entry
8.0
—
9.0
V
MCLR rise time (VDD to VIHH) for
Program/Verify mode entry
—
—
1.0
s
5.0
mA
Current on MCLR/VPP
I/O pins
(ICSPCLK, ICSPDAT) input high
level
(ICSPCLK, ICSPDAT) input low level
ICSPDAT output high level
VOH
0.8 VDD
—
—
V
—
VDD-0.7
VDD-0.7
VDD-0.7
—
0.2 VDD
V
VDD
V
ICSPDAT output low level
VOL
TENTS
TENTH
TCKL
TCKH
TDS
TDH
TCO
TLZD
THZD
VSS+0.6
VSS+0.6
VSS+0.6
Programming mode entry and exit
Programing mode entry setup time:
100
—
—
ICSPCLK, ICSPDAT setup time
before VDD or MCLR
Programing mode entry hold time:
ICSPCLK, ICSPDAT hold time after
250
VDD or MCLR
Serial Program/Verify
Clock Low Pulse Width
100
—
—
Clock High Pulse Width
100
—
—
Data in setup time before clock
100
—
—
Data in hold time after clock
100
—
—
Clock to data out valid (during a
0
—
80
Read Data command)
Clock to data low-impedance
0
—
80
(during a Read Data command)
Clock to data high-impedance
0
—
80
(during a Read Data command)
IOH = 3.5 mA, VDD = 5V
IOH = 3 mA, VDD = 3.3V
IOH = 2 mA, VDD = 1.8V
IOH = 8 mA, VDD = 5V
IOH = 6 mA, VDD = 3.3V
IOH = 3 mA, VDD = 1.8V
DS41332D-page 26
VSS
V
ns
s
ns
ns
ns
ns
ns
ns
ns
 2011 Microchip Technology Inc.
PIC16(L)F72X
TABLE 8-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE (CONTINUED)
AC/DC CHARACTERISTICS
Sym.
TDLY
TERAB
TERAR
TPINT
TPEXT
TDIS
TEXIT
Characteristics
Data input not driven to next clock
input (delay required between
command/data or command/
command)
Bulk Erase cycle time
Row Erase cycle time
Internally timed programming
operation time
Externally timed programming pulse
Time delay from program to compare
(HV discharge time)
Time delay when exiting
Program/Verify mode
 2011 Microchip Technology Inc.
Standard Operating Conditions (unless otherwise stated)
Operating Temperature +10°C  TA +40°C
Min.
Type.
Max.
Units
1.0
—
—
s
—
—
—
—
—
—
—
—
5
2.5
2.5
5
ms
ms
ms
ms
1.0
—
2.1
ms
100
—
—
s
1
—
—
s
Conditions/Comments
Program memory
Configuration fuses
10°C  TA  +40°C
Program memory
DS41332D-page 27
PIC16(L)F72X
8.1
AC Timing Diagrams
FIGURE 8-2:
FIGURE 8-5:
PROGRAMMING MODE
ENTRY – VDD FIRST
TENTS
TENTH
PROGRAMMING MODE
EXIT – VDD LAST
TEXIT
VIHH
VPP VDD
VIL
VIHH
VPP VDD
VDD
VIL
ICSPDAT
VDD
ICSPCLK
ICSPDAT
ICSPCLK
FIGURE 8-6:
CLOCK AND DATA
TIMING
TCKH
FIGURE 8-3:
PROGRAMMING MODE
ENTRY – VPP FIRST
TENTS
TCKL
ICSPCLK
TENTH
TDS TDH
VIHH
ICSPDAT
as
Input
VPP
VIL
TCO
VDD
ICSPDAT
as
Output
ICSPDAT
TLZD
ICSPCLK
ICSPDAT
from Input
to Output
FIGURE 8-4:
PROGRAMMING MODE
EXIT – VPP LAST
TEXIT
THZD
ICSPDAT
from Output
to Input
VIHH
VPP
VIL
VDD
ICSPDAT
ICSPCLK
DS41332D-page 28
 2011 Microchip Technology Inc.
PIC16(L)F72X
FIGURE 8-7:
COMMAND-PAYLOAD TIMING
TDLY
1
2
3
4
5
X
X
X
X
X
1
6
2
15
16
ICSPCLK
X
0 LSb
MSb
ICSPDAT
Command
 2011 Microchip Technology Inc.
Payload
0
Next
Command
DS41332D-page 29
PIC16(L)F72X
APPENDIX A:
REVISION HISTORY
Revision A (11/2007)
Original release of this document.
Revision B (02/2009)
Updated minimum VDD for Bulk Erase in Table 8-1.
Various minor edits.
Clarified time of transition from input to output in Figure
4-3.
Corrected Reserved area range in Figures 3-1, 3-2,
and 3-3.
Corrected low-voltage range for Programming modes
shown in Figures 8-3 and 8-5.
Revision C (02/2010)
Added PIC16F722A, PIC16F723A, PIC16LF722A and
PIC16LF723A
devices
to
the
Programming
Specification; Other minor edits.
Revision D (03/2011)
Updated spec. to new format; Updated Figure 2-2 to
add UQFN; Added Figure 2-6; Added Note 2 to Register 3-1, and Note 1 to Register 3-2; Revised Examples
7-1 and 7-2.
DS41332D-page 30
 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-083-7
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2011 Microchip Technology Inc.
DS41332D-page 31
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02/18/11
DS41332D-page 32
 2011 Microchip Technology Inc.