PIC16(L)F720/721 PIC16(L)F720/721 Flash Memory Programming Specification This document includes the programming specifications for the following devices: 1.1 Hardware Requirements PIC16F/LF720 and PIC16F/LF721 devices require one power supply for VDD and one for MCLR/VPP. (See Section 8.0 “Electrical Specifications” for more details.) • PIC16F720 • PIC16LF720 • PIC16F721 1.2 • PIC16LF721 Five pins are needed for ICSP™ programming. The pins are listed in Table 1-1. 1.0 Pin Utilization OVERVIEW The PIC16F/LF720 and PIC16F/LF721 devices are programmed using In-Circuit Serial Programming™ (ICSP™). This programming specification applies to the PIC16F/LF720 and PIC16F/LF721 devices in all packages. With the exception of memory size and the voltage regulator, all other aspects of the PIC16F/LF720 and PIC16F/LF721 devices are identical. TABLE 1-1: PIN DESCRIPTIONS DURING PROGRAMMING During Programming Pin Name Function Pin Type Pin Description RA1 ICSPCLK I RA0 ICSPDAT I/O Data Input/Output – Schmitt Trigger Input Program/Verify mode P(1) Program Mode Select/Programming power supply VDD VDD P Power Supply VSS VSS P Ground MCLR/VPP Clock Input – Schmitt Trigger Input Legend: I = Input, O = Output, P = Power Note 1: To activate the Program/Verify mode, high voltage needs to be applied to MCLR/VPP input. Since the MCLR /VPP is used for a level source, MCLR/VPP does not draw any significant current. 2011 Microchip Technology Inc. Advance Information DS41409B-page 1 PIC16(L)F720/721 2.0 DEVICE PINOUTS The pin diagrams for the PIC16F/LF720 and PIC16F/ LF721 family are shown in Figure 2-1 and Figure 2-2. The pins that are required for programming are listed in Table 1-1 and shown in bold lettering in the pin diagrams. FIGURE 2-1: 20-PIN DIAGRAM FOR PIC16F/LF720 AND PIC16F/LF721 PDIP, SOIC, SSOP 20 2 19 VSS RA0/ICSPDAT 3 4 18 RA1/ICSPCLK RA3/MCLR/VPP 17 RA2 RC5 5 16 RC0 RC4 6 15 RC1 RC3 RC6 7 14 RC2 8 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6 PIC16F/LF721 1 PIC16F/LF720 VDD RA5 RA4 Note 1: Pin function is controlled by the CAPEN bit of Configuration Word 2. 20-PIN DIAGRAM FOR PIC16F/LF720 AND PIC16F/LF721 RA4 RA5 VDD Vss RA0/ICSPDAT FIGURE 2-2: QFN 4x4 20 19 18 17 16 RA3/MCLR/VPP RC5 RC4 RC3 RC6 1 2 PIC16F/LF720 3 4 PIC16F/LF721 5 15 14 13 12 11 - RA1/ICSPCLK RA2 RC0 RC1 RC2 RC7 RB7 RB6 RB5 RB4 6 7 8 9 10 DS41409B-page 2 Advance Information 2011 Microchip Technology Inc. PIC16(L)F720/721 3.0 MEMORY MAP The memory for the PIC16F/LF720 and PIC16F/LF721 devices is broken into two sections: program memory and configuration memory. The size of the program memory and the configuration memory is different between devices. FIGURE 3-1: PIC16F720 AND PIC16LF720 PROGRAM MEMORY MAPPING 2 KW 0000h 07FFh Program Memory 2000h User ID Location 2001h User ID Location 2002h User ID Location 2003h User ID Location 2004h Reserved 2005h Reserved 2006h Device ID 2007h Configuration Word 1 2008h Configuration Word 2 2009h Calibration Word 1 200Ah Calibration Word 2 Maps to 0000h-07FFh 1FFFh 2000h Implemented 2200h Maps to 2000h-2200h Configuration Memory 3FFFh 200Bh-21FFh 2011 Microchip Technology Inc. Reserved Advance Information DS41409B-page 3 PIC16(L)F720/721 FIGURE 3-2: PIC16F721 AND PIC16LF721 PROGRAM MEMORY MAPPING 4 KW 0000h 0FFFh Program Memory 2000h User ID Location 2001h User ID Location 2002h User ID Location 2003h User ID Location 2004h Reserved 2005h Reserved 2006h Device ID 2007h Configuration Word 1 2008h Configuration Word 2 2009h Calibration Word 1 200Ah Calibration Word 2 Maps to 0000h-0FFFh 1FFFh 2000h Implemented 2200h Maps to 2000h-2200h Configuration Memory 3FFFh 200Bh-21FFh DS41409B-page 4 Reserved Advance Information 2011 Microchip Technology Inc. PIC16(L)F720/721 3.1 User ID Location A user may store identification information (user ID) in four designated locations. The user ID locations are mapped to 2000h-2003h. Each location is 14 bits in length. Code protection has no effect on these memory locations. Each location may be read with code protection enabled or disabled. MPLAB® IDE only displays the 7 Least Significant bits (LSb) of each user ID location, the upper bits are not read. It is recommended that only the 7 LSbs be used if MPLAB IDE is the primary tool used to read these addresses. Note: 3.2 Device ID The device ID word for the PIC16F/LF720 and the PIC16F/LF721 is located at 2006h. This location cannot be erased or modified. DEVICEID: DEVICE ID REGISTER(1) REGISTER 3-1: R-q R-q R-q R-q R-q R-q R-q DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 bit 13 bit 7 R-q R-q R-q R-q R-q R-q R-q DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 6 bit 0 Legend: P = Programmable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit ‘0’ = Bit is cleared -n = Value at POR ‘1’ = Bit is set x = Bit is unknown bit 13-5 DEV<8:0>: Device ID bits These bits are used to identify the part number. bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. Note 1: This location cannot be written. TABLE 3-1: DEVICE ID VALUES DEVICE ID VALUES DEVICE DEV REV PIC16F720 01 1100 0000 x xxxx PIC16F721 01 1100 0010 x xxxx PIC16LF720 01 1100 0100 x xxxx PIC16LF721 01 1100 0110 x xxxx 2011 Microchip Technology Inc. Advance Information DS41409B-page 5 PIC16(L)F720/721 3.3 Configuration Words The PIC16F/LF720 and PIC16F/LF721 have two Configuration Words, Configuration Word 1 (2007h) and Configuration Word 2 (2008h). The individual bits within these Configuration Words are used to enable or disable device functions such as the Brown-out Reset, code protection and Power-up Timer. 3.4 Calibration Words For the PIC16F/LF720 and PIC16F/LF721 devices, the 16 MHz internal oscillator (INTOSC) and the Brown-out Reset (BOR) are factory calibrated and stored in Calibration Words 1 and 2 (2009h and 200Ah). The Calibration Words do not participate in erase operations. The device can be erased without affecting the Calibration Words. DS41409B-page 6 Advance Information 2011 Microchip Technology Inc. PIC16(L)F720/721 REGISTER 3-2: R/P-1 DEBUG( 1) bit 13 CONFIGURATION WORD 1 R/P-1 U-1 U-1 R/P-0 R/P-0 U-1 PLLEN — — BOREN1 BOREN0 — bit 7 R/P-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 CP MCLRE PWRTE WDTEN — FOSC1 R/P-1 FOSC0 bit 0 bit 6 Legend: R = Readable bit -n = Value for blank device W = Writable bit 1 = Bit is set U = Unimplemented bit, read as ‘1’ bit 13 DEBUG(1): Debugger Mode bit 0 = Background debugger is enabled 1 = Background debugger is disabled bit 12 PLLEN: INTOSC PLL Enable bit 0 = INTOSC Frequency is 500 kHz 1 = INTOSC Frequency is 16 MHz (32x) 0 = Bit is cleared x = Bit is unknown bit 11-10 Unimplemented: Read as ‘1’ bit 9-8 BOREN<1:0>: Brown-out Reset Enable bits (2) 0x = Brown-out Reset disabled (Preconditioned State) 10 = Brown-out Reset enabled during operation and disabled in Sleep 11 = Brown-out Reset enabled bit 7 Unimplemented: Read as ‘1’ bit 6 CP: Flash Program Memory Code Protection bit PIC16F720/721 0 = 0000h to 07FFh/0FFFh code protection on 1 = Code protection off bit 5 MCLRE: RA3/MCLR/VPP Pin Function Select bit 1 = RA3/MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = RA3/MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up disabled bit 4 PWRTE: Power-up Timer Enable bit 0 = PWRT enabled 1 = PWRT disabled bit 3 WDTEN: Watchdog Timer Enable bit 0 = WDT disabled 1 = WDT enabled bit 2 Unimplemented: Read as ‘1’ bit 1-0 FOSC<1:0>: Oscillator Selection bits 11 = EC oscillator: CLKO function on RA4/CLKO pin, CLKI on RA5/CLKI 10 = EC oscillator: I/O function on RA4/CLKO pin, CLKI on RA5/CLKI 01 = INTOSC oscillator: CLKO function on RA4/CLKO pin, I/O function on RA5/CLKI 00 = INTOSCIO oscillator: I/O function on RA4/CLKO pin, I/O function on RA5/CLKI Note 1: Debug bit is ignored when code-protect is enabled (CP= 0). 2: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled. 2011 Microchip Technology Inc. Advance Information DS41409B-page 7 PIC16(L)F720/721 REGISTER 3-3: CONFIGURATION WORD 2 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — bit 13 bit 7 U-1 U-1 R/P-1 U-1 U-1 R/P-1 R/P-1 — — VCAPEN — — WRT1 WRT0 bit 6 bit 0 Legend: R = Readable bit -n = Value for blank device W = Writable bit 1 = Bit is set U = Unimplemented bit, read as ‘1’ 0 = Bit is cleared x = Bit is unknown bit 13-5 Unimplemented: Read as ‘1’ bit 4 VCAPEN( 1): Voltage Regulator Capacitor Enable bits 0 = VCAP functionality is enabled on RA2. (VDDCORE is connected to the pad) 1 = All VCAP pin functions are disabled (Erased or Preconditioned State) bit 3-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 2 kW Flash memory: PIC16F/LF720 : 11 = Write protection off 10 = 000h to 1FFh write protected, 200h to 7FFh may be modified by PMCON control 01 = 000h to 3FFh write protected, 400h to 7FFh may be modified by PMCON control 00 = 000h to 7FFh write protected, no addresses may be modified by PMCON control 4 kW Flash memory: PIC16F/LF721: 11 = Write protection off 10 = 000h to 1FFh write protected, 200h to FFFh may be modified by PMCON control 01 = 000h to 7FFh write protected, 800h to FFFh may be modified by PMCON control 00 = 000h to FFFh write protected, no addresses may be modified by PMCON control Note 1: For the PIC16F720/721 only. DS41409B-page 8 Advance Information 2011 Microchip Technology Inc. PIC16(L)F720/721 4.0 PROGRAM/VERIFY MODE disabled (MCLRE = 0), the power-up time is disabled (PWRTE = 0), the internal oscillator is selected (FOSC = 10x), and RA0 and RA1 are driven by the user application, the device will execute code. Since this may prevent entry, VPP-First Entry mode is strongly recommended. See the timing diagram in Figure 8-2. In Program/Verify mode, the program memory and the configuration memory can be accessed and programmed in serial fashion. ICSPDAT and ICSPCLK are used for the data and the clock, respectively. All commands and data words are transmitted LSb first. Data changes on the rising edge of the ICSPCLK and latched on the falling edge. In Program/Verify mode, both the ICSPDAT and ICSPCLK are Schmitt Trigger inputs. The sequence that enters the device into Program/Verify mode places all other logic into the Reset state. Upon entering Program/Verify mode, all I/Os are automatically configured as high-impedance inputs and the address is cleared. 4.1 4.1.2 To enter Program/Verify mode via the VDD-first method, the following sequence must be followed: 1. 2. The VDD-first method is useful when programming the device, when VDD is already applied, for it is not necessary to disconnect VDD to enter Program/Verify mode. See the timing diagram in Figure 8-1. There are two different methods of entering Program/ Verify mode: 4.1.3 • VPP – First entry mode • VDD – First entry mode 2. 3. VPP – FIRST ENTRY MODE 4.2 Program/Verify Commands The PIC16F/LF720 and PIC16F/LF721 implement 10 programming commands, each six bits in length. The commands are summarized in Table 4-1. Hold ICSPCLK and ICSPDAT low. All other pins should be unpowered. Raise the voltage on MCLR from 0V to VIHH. Raise the voltage on VDD from 0V to the desired operating voltage. Commands that have data associated with them are specified to have a minimum delay of TDLY between the command and the data. After this delay 16 clocks are required to either clock in or clock out the 14-bit data word. The first clock is for the Start bit and the last clock is for the Stop bit. The VPP-first entry prevents the device from executing code prior to entering Program/Verify mode. For example, when the Configuration Word has MCLR TABLE 4-1: PROGRAM/VERIFY MODE EXIT To exit Program/Verify mode take MCLR to VDD or lower (VIL). See Figures 8-3 and 8-4. To enter Program/Verify mode via the VPP-first method the following sequence must be followed: 1. Hold ICSPCLK and ICSPDAT low. Raise the voltage on VDD from 0V to the desired operating voltage. Raise the voltage on MCLR from VDD or below to VIHH. 3. Program/Verify Mode Entry and Exit 4.1.1 VDD – FIRST ENTRY MODE COMMAND MAPPING FOR PIC16F/LF720 AND PIC16F/LF721 Mapping Data/Note Command Binary (MSb … LSb) Hex Load Configuration x 0 0 0 0 0 00h 0, data (14), 0 Load Data For Program Memory x 0 0 0 1 0 02h 0, data (14), 0 Read Data From Program Memory x 0 0 1 0 0 04h 0, data (14), 0 Increment Address x 0 0 1 1 0 06h Reset Address x 1 0 1 1 0 16h Begin Internally Timed Programming x 0 1 0 0 0 08h Begin Externally Timed Programming x 1 1 0 0 0 18h End Externally Timed Programming x 0 1 0 1 0 0Ah Bulk Erase Program Memory x 0 1 0 0 1 09h Internally Timed Row Erase Program Memory x 1 0 0 0 1 11h Internally Timed 2011 Microchip Technology Inc. Advance Information DS41409B-page 9 PIC16(L)F720/721 4.2.1 LOAD CONFIGURATION After issuing the Load Configuration command, use the Increment Address command until the proper address to be programmed is reached. The address is then programmed by issuing either the Begin Internally Timed Programming or Begin Externally Timed Programming command. The Load Configuration command is used to access the configuration memory (User ID Locations, Configuration Words, Calibration Words). The Load Configuration command sets the address to 2000h and loads the data latches with one word of data (see Figure 4-1). FIGURE 4-1: The only way to get back to the program memory (address 0) is to exit Program/Verify mode or issue the Reset Address command after the configuration memory has been accessed by the Load Configuration command. LOAD CONFIGURATION 1 2 5 4 3 2 1 6 16 15 TDLY ICSPCLK ICSPDAT 4.2.2 0 0 0 0 X 0 0 LSb 1 2 MSb 0 LOAD DATA FOR PROGRAM MEMORY The Load Data for Program Memory command is used to load one 14-bit word into the data latches. The word programs into program memory after the Begin Internally Timed Programming or Begin Externally Timed Programming command is issued (see Figure 4-2). FIGURE 4-2: LOAD DATA FOR PROGRAM MEMORY 1 2 3 4 5 6 15 16 TDLY ICSPCLK ICSPDAT DS41409B-page 10 0 1 0 0 0 X Advance Information 0 LSb MSb 0 2011 Microchip Technology Inc. PIC16(L)F720/721 4.2.3 READ DATA FROM PROGRAM MEMORY The Read Data from Program Memory command will transmit data bits out of the program memory map currently accessed, starting with the second rising edge of the clock input. The ICSPDAT pin will go into Output mode on the first falling clock edge, and it will revert to Input mode (high-impedance) after the 16th falling edge of the clock. If the program memory is code-protected (CP), the data will be read as zeros (see Figure 4-3). FIGURE 4-3: READ DATA FROM PROGRAM MEMORY 1 2 3 4 5 6 1 2 15 16 TDLY ICSPCLK ICSPDAT (from Programmer) 0 1 0 0 0 X ICSPDAT (from device) x MSb Input Output Input 4.2.4 LSb INCREMENT ADDRESS The address is incremented when this command is received. It is not possible to decrement the address. To reset this counter, the user must use the Reset Address command or exit Program/Verify mode and reenter it. If the address is incremented from address 1FFFh, it will wrap-around to location 0000h. If the address is incremented from 3FFFh, it will wrap-around to location 2000h. FIGURE 4-4: INCREMENT ADDRESS Next Command 1 2 4 3 2 1 6 5 3 TDLY ICSPCLK 0 1 1 0 0 X ICSPDAT Address 2011 Microchip Technology Inc. Advance Information X X X Address + 1 DS41409B-page 11 PIC16(L)F720/721 4.2.5 RESET ADDRESS The Reset Address command will reset the address to 0000h, regardless of the current value. The address is used in program memory or the configuration memory. FIGURE 4-5: RESET ADDRESS Next Command 1 2 4 3 5 2 1 6 3 TDLY ICSPCLK 0 1 1 0 1 X X X X ICSPDAT 4.2.6 0000h N Address BEGIN INTERNALLY TIMED PROGRAMMING A Load Configuration or Load Data for Program Memory command must be given before every Begin Programming command. Programming of the addressed memory will begin after this command is received. An internal timing mechanism executes the write. The user must allow for the program cycle time, TPINT, for the programming to complete. The End Externally Timed Programming command is not needed when the Begin Internally Timed Programming is used to start the programming. The program memory address that is being programmed is not erased prior to being programmed. FIGURE 4-6: BEGIN INTERNALLY TIMED PROGRAMMING 1 2 5 4 3 Next Command 1 2 3 6 TPINT ICSPCLK ICSPDAT DS41409B-page 12 0 0 0 1 0 X Advance Information X X X 2011 Microchip Technology Inc. PIC16(L)F720/721 4.2.7 BEGIN EXTERNALLY TIMED PROGRAMMING A Load Configuration or Load Data for Program Memory command must be given before every Begin Programming command. Programming of the addressed memory will begin after this command is received. To complete the programming, the End Externally Timed Programming command must be sent in the specified time window defined by TPEXT. The program memory address that is being programmed is not erased prior to being programmed. The Begin Externally Timed Programming command cannot be used for programming the Configuration Words (see Figure 4-7). FIGURE 4-7: BEGIN EXTERNALLY TIMED PROGRAMMING End Externally Timed Programming Command 1 2 5 4 3 1 6 2 3 TPEXT ICSPCLK 0 ICSPDAT 4.2.8 0 0 1 0 X 1 1 0 END EXTERNALLY TIMED PROGRAMMING This command is required after a Begin Externally Timed Programming command is given. This command must be sent within the time window specified by TPEXT after the Begin Externally Timed Programming command is sent. After sending the End Externally Timed Programming command, an additional delay (TDIS) is required before sending the next command. This delay is longer than the delay ordinarily required between other commands (see Figure 4-8). FIGURE 4-8: END EXTERNALLY TIMED PROGRAMMING 1 2 3 5 4 Next Command 2 1 3 6 TDIS ICSPCLK ICSPDAT 2011 Microchip Technology Inc. 0 1 0 1 1 X Advance Information X X X DS41409B-page 13 PIC16(L)F720/721 4.2.9 BULK ERASE PROGRAM MEMORY After receiving the Bulk Erase Program Memory command, the erase will not complete until the time interval, TERAB, has expired. The Bulk Erase Program Memory command performs two different functions dependent on the current state of the address. Note: Address 0000h-1FFFh: Program Memory is erased The code protection Configuration bit (CP) has no effect on the Bulk Erase Program Memory command. Configuration words are erased Address 2000h-2008h: Program Memory is erased Configuration Words are erased User ID Locations are erased A Bulk Erase Program Memory command should not be issued when the address is greater than 2008h. FIGURE 4-9: BULK ERASE PROGRAM MEMORY 1 2 4 3 5 Next Command 2 1 3 6 TERAB ICSPCLK ICSPDAT 4.2.10 1 0 0 0 1 X X X X ROW ERASE PROGRAM MEMORY This command erases the 32-word row of program memory pointed to by PC<13:5>. If the program memory array is protected (CP = 0) or the PC points to the configuration memory (> 0x2000), the command is ignored. When the address is 2000h-2008h, the Row Erase Program Memory command will only erase the user ID locations, regardless of the configuration bit CP setting. After receiving the Row Erase Program Memory command, the erase will not be complete until the time interval, TERAR, has expired. FIGURE 4-10: ROW ERASE PROGRAM MEMORY 1 2 4 3 5 Next Command 2 1 3 6 TERAR ICSPCLK ICSPDAT DS41409B-page 14 1 0 0 0 1 X Advance Information X X X 2011 Microchip Technology Inc. PIC16(L)F720/721 5.0 PROGRAMMING ALGORITHMS The PIC16F/LF720 and PIC16F/LF721 devices have the capability of storing 32 14-bit words in its data latches. The data latches are internal to the PIC16F/ LF720 and PIC16F/LF721 devices and are only used for programming. The data latches allow the user to program up to 32 program words with a single Begin Externally Timed Programming or Begin Internally Timed Programming command. The Load Program Data or the Load Configuration command is used to load a single data latch. The data latch will hold the data until the Begin Externally Timed Programming or Begin Internally Timed Programming command is given. The data latches are aligned with the 5 LSb of the address. The address at the time the Begin Externally Timed Programming or Begin Internally Timed Programming command is given will determine which location(s) in memory are written. Writes cannot cross a physical 32-word boundary. For example, attempting to write from address 0002h-0021h will result in data being written to 0020h-003Fh. If more than 32 data latches are written without a Begin Externally Timed Programming or Begin Internally Timed Programming command, the data in the data latches will be overwritten. The following figures show the recommended flowcharts for programming. 2011 Microchip Technology Inc. Advance Information DS41409B-page 15 PIC16(L)F720/721 FIGURE 5-1: DEVICE PROGRAM/VERIFY FLOWCHART Start Enter Programming Mode Bulk Erase Device(3) Write Program Memory(1) Write User IDs Verify Program Memory Verify User IDs Write Configuration Words(2) Verify Configuration Words Exit Programming Mode Done Note 1: DS41409B-page 16 See Figure 5-2. 2: See Figure 5-5. 3: See Figure 5-6. Advance Information 2011 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 5-2: PROGRAM MEMORY FLOWCHART Start Bulk Erase Program Memory(1, 2) Program Cycle(3) Read Data from Program Memory No Data Correct? Report Programming Failure Yes Increment Address Command No All Locations Done? Yes Done Note 1: This step is optional if the device has already been erased or has not been previously programmed. 2: If the device is code-protected or must be completely erased, then Bulk Erase the device per Figure 5-6. 3: See Figure 5-3 or Figure 5-4. 2011 Microchip Technology Inc. Advance Information DS41409B-page 17 PIC16(L)F720/721 FIGURE 5-3: ONE-WORD PROGRAM CYCLE Program Cycle Load Data for Program Memory Begin Programming Command (Internally timed) Begin Programming Command (Externally timed) Wait TPINT Wait TPEXT End Programming Command Wait TDIS DS41409B-page 18 Advance Information 2011 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 5-4: MULTIPLE-WORD PROGRAM CYCLE Program Cycle Load Data for Program Memory Latch 1 Increment Address Command Load Data for Program Memory Latch 2 Increment Address Command Load Data for Program Memory Latch 32 Begin Programming Command (Internally timed) Begin Programming Command (Externally timed) Wait TPINT Wait TPEXT End Programming Command Wait TDIS 2011 Microchip Technology Inc. Advance Information DS41409B-page 19 PIC16(L)F720/721 FIGURE 5-5: CONFIGURATION MEMORY PROGRAM FLOWCHART Start Load Configuration Bulk Erase Program Memory(1) One-word Program Cycle(2) (User ID) Read Data From Program Memory Command Data Correct? No Report Programming Failure Yes Increment Address Command No Address = 2004h? Yes Increment Address Command Increment Address Command Increment Address Command One-word Program Cycle(2) (Config. Word 1) Read Data From Program Memory Command Data Correct? No Report Programming Failure Yes Increment Address Command One-word Program Cycle(2) (Config. Word 2) Read Data From Program Memory Command Data Correct? No Report Programming Failure Yes Note 1: This step is optional if the device is erased or not previously programmed. 2: See Figure 5-3. DS41409B-page 20 Advance Information Done 2011 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 5-6: ERASE FLOWCHART Start Load Configuration Bulk Erase Program Memory Done Note: This sequence does not erase the Calibration Words. 2011 Microchip Technology Inc. Advance Information DS41409B-page 21 PIC16(L)F720/721 6.0 CODE PROTECTION Code protection is controlled using the CP bit in Configuration Word 1. When code protection is enabled, all program memory locations 0000h-0FFFh for the PIC16F/LF720 and 0000h-07FFh for the PIC16F/LF721 will read as ‘0’ and further programming of the program memory is disabled. Program memory can still be read by user code during program execution. The user ID locations and Configuration Words can be programmed and read out regardless of the code protection settings. 6.1 Enabling Code Protection Code protection is enabled by programming the CP bit in Configuration Word 1 to ‘0’. 6.2 Disabling Code Protection The only way to disable code protection is to use the Bulk Erase Program Memory command. DS41409B-page 22 Advance Information 2011 Microchip Technology Inc. PIC16(L)F720/721 7.0 HEX FILE USAGE 7.3 In the hex file there are two bytes per program word stored in the Intel® INH8M hex format. Data is stored LSB first, MSB second. Because there are two bytes per word, the addresses in the hex file are 2x the address in program memory. (Example: The Configuration Word 1 is stored at 2007h on the PIC16F/LF720 and PIC16F/LF721. In the hex file this will be at location 400Eh-400Fh). 7.1 Configuration Word To allow portability of code, it is strongly recommended that the programmer is able to read the Configuration Words and user ID locations from the hex file. If the Configuration Words information was not present in the hex file, a simple warning message may be issued. Similarly, while saving a hex file, Configuration Words and user ID information should be included. 7.2 Device ID and Revision If a device ID is present in the hex file at 400Ch-400Dh (2006h on the part), the programmer should verify the device ID (excluding the revision) against the value read from the part. On a mismatch condition, the programmer should generate a warning message. Checksum Computation The checksum is calculated by two different methods, dependent on the setting of the CP Configuration bit. TABLE 7-1: Device CONFIGURATION WORD MASK VALUES Config. Word 1 Mask Config. Word 2 Mask PIC16F720 337Bh 0013h PIC16LF720 337Bh 0003h PIC16F721 337Bh 0013h PIC16LF721 337Bh 0003h 7.3.1 CODE PROTECTION DISABLED With the code protection disabled, the checksum is computed by reading the contents of the PIC16F/ LF720 and PIC16F/LF721 program memory locations and adding up the program memory data, starting at address 0000h, up to the maximum user addressable location, 0FFFh for the PIC16F/LF720 and 07FFh for the PIC16F/LF721. Any Carry bit exceeding 16 bits are neglected. Additionally, the relevant bits of the Configuration Words are added to the checksum. All unused Configuration bits are masked to ‘0’. See Table 7-1 for Configuration Word Mask Values. Example 7-1 through Example 7-4 shown below are for a blank device and for a device with 00AAh at the first and last program memory locations. EXAMPLE 7-1: PIC16F720 CHECKSUM COMPUTED WITH CODE PROTECTION DISABLED (PIC16F720), BLANK DEVICE Sum of Memory addresses 0000h-07FFh(1) F800h Configuration Word 1(2) 3FFFh (3) Configuration Word 1 mask 337Bh Configuration Word 2(2) 3FFFh (3) Configuration Word 2 mask Checksum 0013h = F800h + (3FFFh and 337Bh) + (3FFFh and 0013h) = F800h + 337Bh + 0013h = 2B8Eh Note 1: Sum of Memory addresses = (Total number of program memory address locations) x (3FFFh) = F800h, truncated to 16 bits. 2: Configuration Word 1 and 2 = all bits are ‘1’; thus, code-protect is disabled. 3: Configuration Word 1 and 2 Mask = all bits are set to ‘1’, except for unimplemented bits that are ‘0’. 2011 Microchip Technology Inc. Advance Information DS41409B-page 23 PIC16(L)F720/721 EXAMPLE 7-2: PIC16LF720 CHECKSUM COMPUTED WITH CODE PROTECTION DISABLED (PIC16LF720), 00AAh AT FIRST AND LAST ADDRESS Sum of Memory addresses 0000h-07FFh(1) (2) 7956h Configuration Word 1 3FFFh Configuration Word 1 mask(3) 337Bh (2) Configuration Word 2 3FFFh Configuration Word 2 mask Checksum (4) 0003h = 7956h + (3FFFh and 337Bh) + (3FFFh and 0003h) = 7956h + 337Bh + 0003h = ACD4h Note 1: Total number of program memory address locations: 07FFh + 1 = 0800h. Then, 0800h - 2 = 07FEh. Thus, [(07FEh x 3FFFh) + (2 x 00AAh)] = 7956h, truncated to 16 bits. 2: Configuration Word 1 and 2 = all bits are ‘1’; thus, code-protect is disabled. 3: Configuration Word 1 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits that are ‘0’. 4: On the PIC16LF720 device, the VCAPEN bit is not implemented in Configuration Word 2; thus, all unimplemented bits are ‘0’. EXAMPLE 7-3: PIC16F721 CHECKSUM COMPUTED WITH CODE PROTECTION DISABLED (PIC16F721), BLANK DEVICE Sum of Memory addresses 0000h-0FFFh(1) F000h Configuration Word 1(2) 3FFFh Configuration Word 1 mask(3) 337Bh Configuration Word 2(2) 3FFFh Configuration Word 2 mask(3) Checksum = F000h + (3FFFh and 337Bh) + (3FFFh and 0013h) 0013h = F000h + 337Bh + 0013h = 238Eh Note 1: Sum of Memory addresses = (Total number of program memory address locations) x (3FFFh) = F800h, truncated to 16 bits. 2: Configuration Word 1 and 2 = all bits are ‘1’; thus, code-protect is disabled. 3: Configuration Word 1 and 2 Mask = all bits are set to ‘1’, except for unimplemented bits that are ‘0’. DS41409B-page 24 Advance Information 2011 Microchip Technology Inc. PIC16(L)F720/721 EXAMPLE 7-4: PIC16LF721 CHECKSUM COMPUTED WITH CODE PROTECTION DISABLED (PIC16LF721), 00AAh AT FIRST AND LAST ADDRESS Sum of Memory addresses 0000h-0FFFh(1) (2) 7156h Configuration Word 1 3FFFh Configuration Word 1 mask(3) 337Bh Configuration Word 2(2) 3FFFh Configuration Word 2 mask Checksum (4) 0003h =7156h + (3FFFh and 337Bh) + (3FFFh and 0003h) = 7156h + 337Bh + 0003h = A4D4h Note 1: Total number of program memory address locations: 0FFFh + 1 = 1000h. Then, 1000h - 2 = 0FFEh. Thus, [(0FFEh x 3FFFh) + (2 x 00AAh)] = 7156h, truncated to 16 bits. 2: Configuration Word 1 and 2 = all bits are ‘1’; thus, code-protect is disabled. 3: Configuration Word 1 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits that are ‘0’. 4: On the PIC16LF721 device, the VCAPEN bit is not implemented in Configuration Word 2; thus, all unimplemented bits are ‘0’. 2011 Microchip Technology Inc. Advance Information DS41409B-page 25 PIC16(L)F720/721 7.3.2 CODE PROTECTION ENABLED With the program code protection enabled, the checksum is computed in the following manner: the Least Significant nibble of each user ID is used to create a 16-bit value. The masked value of user ID location 2000h is the Most Significant nibble. This Sum of user IDs is summed with the Configuration Words (all unimplemented Configuration bits are masked to ’0’). Example 7-5 through Example 7-8 shown below are for a blank device and for a device with 00AAh at the first and last program memory locations. Also, see Table 7-1 for Configuration Word mask values with code protection enabled. EXAMPLE 7-5: CHECKSUM COMPUTED WITH CODE PROTECTION ENABLED (PIC16F720), BLANK DEVICE PIC16F720 Configuration Word 1(2) 3FBFh Configuration Word 1 mask(3) Configuration Word 2(2) 337Bh 3FFFh Configuration Word 2 mask(3) 0013h (1) 0001h User ID (2001h)(1) 0007h (2002h)(1) 000Ah User ID (2003h)(1) 000Fh User ID (2000h) User ID Sum of User IDs(4) = (0001h and 000Fh) << 12 + (0007h and 000Fh) << 8 + (000Ah and 000Fh) << 4 + (000Fh and 000Fh) = 1000h + 0700h + 00A0h + 000Fh = 17AFh Checksum = (3FBFh and 337Bh) + (3FFFh and 0013h) + Sum of User IDs = 333Bh +0013h + 17AFh = 4AFDh Note 1: User ID values in this example are random values. 2: Configuration Word 1 and 2 = all bits are ‘1’, except the code-protect enable bit. 3: Configuration Word 1 and 2 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits which read ‘0’. 4: << = shift left, thus the LSb of the first user ID value is the MSb of the sum of user IDs and so on until the LSb of the last user ID value becomes the LSb of the sum of user IDs. DS41409B-page 26 Advance Information 2011 Microchip Technology Inc. PIC16(L)F720/721 EXAMPLE 7-6: CHECKSUM COMPUTED WITH CODE PROTECTION ENABLED (PIC16F721), BLANK DEVICE PIC16F721 Configuration Word 1 (2) Configuration Word 1 mask(3) Configuration Word 2 (2) 3FBFh 337Bh 3FFFh Configuration Word 2 mask(3) 0013h (1) 0001h User ID (2001h)(1) 0007h (2002h)(1) 000Ah User ID (2003h)(1) 000Fh User ID (2000h) User ID (4) Sum of User IDs = (0001h and 000Fh) << 12 + (0007h and 000Fh) << 8 + (000Ah and 000Fh) << 4 + (000Fh and 000Fh) = 1000h + 0700h + 00A0h + 000Fh = 17AFh Checksum = (3FBFh and 337Bh) + (3FFFh and 0013h) + Sum of User IDs = 333Bh +0013h + 17AFh = 4AFDh Note 1: User ID values in this example are random values. 2: Configuration Word 1 and 2 = all bits are ‘1’, except the code-protect enable bit. 3: Configuration Word 1 and 2 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits which read ‘0’. 4: << = shift left, thus the LSb of the first user ID value is the MSb of the sum of user IDs and so on until the LSb of the last user ID value becomes the LSb of the sum of user IDs. 2011 Microchip Technology Inc. Advance Information DS41409B-page 27 PIC16(L)F720/721 EXAMPLE 7-7: CHECKSUM COMPUTED WITH CODE PROTECTION ENABLED (PIC16LF720), 00AAh AT FIRST AND LAST ADDRESS PIC16LF720 Configuration Word 1(2) 3FBFh Configuration Word 1 mask(3) Configuration Word 2 (2) 337Bh 3FFFh Configuration Word 2 mask(3), (5) 0003h (1) 0009h User ID (2001h)(1) 0008h (2002h)(1) 000Dh User ID (2003h)(1) 0005h User ID (2000h) User ID Sum of User IDs (4) = (0009h and 000Fh) << 12 + (0008h and 000Fh) << 8 + (000Dh and 000Fh) << 4 + (0005h and 000Fh) = 9000h + 0800h + 00D0h + 0005h = 98D5h Checksum = (3FBFh and 337Bh) + (3FFFh and 0003h) + Sum of User IDs = 333Bh +0003h + 98D5h = CC13h Note 1: User ID values in this example are random values. 2: Configuration Word 1 and 2 = all bits are ‘1’, except the code-protect enable bit. 3: Configuration Word 1 and 2 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits which read ‘0’. 4: << = shift left, thus the LSb of the first user ID value is the MSb of the sum of user IDs and so on until the LSb of the last user ID value becomes the LSb of the sum of user IDs. 5: On the PIC16LF720 device, the VCAPEN bit is not implemented in Configuration Word 2; thus, all unimplemented bits are ‘0’. DS41409B-page 28 Advance Information 2011 Microchip Technology Inc. PIC16(L)F720/721 EXAMPLE 7-8: CHECKSUM COMPUTED WITH CODE PROTECTION ENABLED (PIC16LF721), 00AAh AT FIRST AND LAST ADDRESS PIC16LF721 Configuration Word 1(2) 3FBFh Configuration Word 1 mask(3) Configuration Word 2 (2) 337Bh 3FFFh Configuration Word 2 mask(3), (5) 0003h (1) 0009h User ID (2001h)(1) 0008h (2002h)(1) 000Dh User ID (2003h)(1) 0005h User ID (2000h) User ID Sum of User IDs (4) = (0009h and 000Fh) << 12 + (0008h and 000Fh) << 8 + (000Dh and 000Fh) << 4 + (0005h and 000Fh) = 9000h + 0800h + 00D0h + 0005h = 98D5h Checksum = (3FBFh and 337Bh) + (3FFFh and 0003h) + Sum of User IDs = 333Bh +0003h + 98D5h = CC13h Note 1: User ID values in this example are random values. 2: Configuration Word 1 and 2 = all bits are ‘1’, except the code-protect enable bit. 3: Configuration Word 1 and 2 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits which read ‘0’. 4: << = shift left, thus the LSb of the first user ID value is the MSb of the sum of user IDs and so on until the LSb of the last user ID value becomes the LSb of the sum of user IDs. 5: On the PIC16LF721 device, the VCAPEN bit is not implemented in Configuration Word 2; thus, all unimplemented bits are ‘0’. 2011 Microchip Technology Inc. Advance Information DS41409B-page 29 PIC16(L)F720/721 8.0 ELECTRICAL SPECIFICATIONS Refer to device specific data sheet for absolute maximum ratings. TABLE 8-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE Standard Operating Conditions (unless otherwise stated) Operating Temperature +10°C TA +40°C AC/DC CHARACTERISTICS Sym. Characteristics Min. Type. Max. Units Conditions/ Comments Supply Voltages and currents VDD Read/Write and Row Erase operations VDD Bulk Erase operations PIC16F720 PIC16F721 2.1 — 5.5 V PIC16LF720 PIC16LF721 2.1 — 3.6 V PIC16F720 PIC16F721 2.7 — 5.5 V PIC16LF720 PIC16LF721 2.7 — 3.6 V IDDI Current on VDD, Idle — — 1.0 mA IDDA Current on VDD, program cycle or Bulk Erase in progress — — 5.0 mA High voltage on MCLR/VPP for Program/Verify mode entry 8.0 — 9.0 V TVHHR MCLR rise time (VDD to VIHH) for Program/Verify mode entry — — 1.0 s IPP Current on MCLR/VPP 600 A VIH VIL I/O pins (ICSPCLK, ICSPDAT) input high level (ICSPCLK, ICSPDAT) input low level ICSPDAT output high level VPP VIHH VOH 0.8 VDD — VDD-0.7 VDD-0.7 VDD-0.7 — — — 0.2 VDD V V — VDD V VSS — VSS+0.6 VSS+0.6 VSS+0.6 V — ns — s — — — — ns ns ns ns 80 ns 80 ns 80 ns — s ICSPDAT output low level VOL TENTS TENTH TCKL TCKH TDS TDH TCO TLZD THZD TDLY Programming mode entry and exit Programing mode entry setup time: ICSPCLK, 100 — ICSPDAT setup time before VDD or MCLR Programing mode entry hold time: ICSPCLK, 250 — ICSPDAT hold time after VDD or MCLR Serial Program/Verify Clock Low Pulse Width 100 — Clock High Pulse Width 100 — Data in setup time before clock 100 — Data in hold time after clock 100 — Clock to data out valid (during a Read Data 0 — command) Clock to data low-impedance (during a Read 0 — Data command) Clock to data high-impedance (during a Read 0 — Data command) Data input not driven to next clock input (delay required between command/data or command/ 1.0 — command) DS41409B-page 30 Advance Information IOH = 3.5 mA, VDD = 5V IOH = 3 mA, VDD = 3.3V IOH = 2 mA, VDD = 1.8V IOH = 8 mA, VDD = 5V IOH = 6 mA, VDD = 3.3V IOH = 3 mA, VDD = 1.8V 2011 Microchip Technology Inc. PIC16(L)F720/721 TABLE 8-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE Standard Operating Conditions (unless otherwise stated) Operating Temperature +10°C TA +40°C AC/DC CHARACTERISTICS Sym. TERAB TERAR TPINT TPEXT TDIS TEXIT Characteristics Bulk Erase cycle time Row Erase cycle time Internally timed programming operation time Externally timed programming pulse Time delay from program to compare (HV discharge time) Time delay when exiting Program/Verify mode 2011 Microchip Technology Inc. Min. Type. Max. Units — — — — — — — — 5 2.5 2.5 5 ms ms ms ms 1.0 — 2.1 ms 100 — — s 1 — — s Advance Information Conditions/ Comments Program memory Configuration fuses 10°C TA +40°C Program memory DS41409B-page 31 PIC16(L)F720/721 8.1 FIGURE 8-4: AC Timing Diagrams FIGURE 8-1: PROGRAMMING MODE ENTRY – VDD FIRST TENTS PROGRAMMING MODE EXIT – VDD LAST TEXIT VIHH TENTH MCLR/VPP is at VDD VIL VIHH MCLR/VPP is at VDD VIL VDD ICSPDAT VDD ICSPCLK ICSPDAT ICSPCLK FIGURE 8-5: CLOCK AND DATA TIMING TCKH FIGURE 8-2: PROGRAMMING MODE ENTRY – MCLR/VPP FIRST TENTS TCKL ICSPCLK TENTH TDS TDH VIHH ICSPDAT as Input MCLR/VPP VIL TCO VDD ICSPDAT as Output ICSPDAT TLZD ICSPCLK ICSPDAT from Input to Output FIGURE 8-3: PROGRAMMING MODE EXIT – MCLR/VPP LAST TEXIT THZD ICSPDAT from Output to Input VIHH MCLR/VPP VIL VDD ICSPDAT ICSPCLK DS41409B-page 32 Advance Information 2011 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 8-6: COMMAND-PAYLOAD TIMING TDLY 1 2 3 4 5 X X X X X 1 6 2 15 16 ICSPCLK X 0 LSb MSb ICSPDAT Command 2011 Microchip Technology Inc. Advance Information Payload 0 Next Command DS41409B-page 33 PIC16(L)F720/721 APPENDIX A: REVISION HISTORY Revision A (12/2009) Initial release of this document. Revision B (02/2011) Updated the Programming Specification to new format; Revised Figures 3-1, 3-2 and Example 7-3. DS41409B-page 34 Advance Information 2011 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-919-8 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2011 Microchip Technology Inc. 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