PIC18F2525/2620/4525/4620 PIC18F2525/2620/4525/4620 Rev. B4 Silicon Errata The PIC18F2525/2620/4525/4620 Rev. B4 parts you have received conform functionally to the Device Data Sheet (DS39626C), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC18F2525/2620/4525/4620 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues. The following silicon errata apply only to PIC18F2525/2620/4525/4620 devices with these Device/Revision IDs: Part Number Device ID Revision ID PIC18F2525 0000 1100 110 0 0110 PIC18F2620 0000 1100 100 0 0110 PIC18F4525 0000 1100 010 0 0110 PIC18F4620 0000 1100 000 0 0110 The Device IDs (DEVID1 and DEVID2) are located at addresses 3FFFFEh:3FFFFFh in the device’s configuration space. They are shown in binary in the format “DEVID2 DEVID1”. TABLE 1: Param No. 70 1. Module: MSSP In SPI Slave mode with slave select enabled (SSPM3:0 = 0100), the minimum time between the falling edge of the SS pin and the first SCK edge is greater than specified in parameter 70 in Table 26-16. The updated specification is shown in bold in Table 1. The minimum time between SS pin low and an SSPBUF write is also 3 TCY. If the falling edge of the SS pin occurs greater than 3 TCY before the first SCK edge or loading SSPBUF, the peripheral will function correctly. Also, if SSPBUF is written prior to the SS pin going low, the peripheral will function correctly. Work around None. Date Codes that pertain to this issue: All engineering and production devices. EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING) Symbol Characteristic TSSL2SCH, SS↓ to SCK↓ or SCK↑ Input TSSL2SCL © 2007 Microchip Technology Inc. Min 3 TCY Max Units Conditions — ns DS80282C-page 1 PIC18F2525/2620/4525/4620 2. Module: MSSP With MSSP in SPI Master mode, FOSC/64 or Timer2/2 clock rate, and CKE = 0, a write collision may occur if SSPBUF is loaded immediately after the transfer is complete. A delay may be required after the MSSP Interrupt Flag bit, SSPIF, is set or the Buffer Full bit, BF, is set and before writing SSPBUF. If the delay is insufficiently short, a write collision may occur as indicated by the WCOL bit being set. Work around Add a software delay of one SCK period after detecting the completed transfer and prior to updating the SSPBUF contents. Verify the WCOL bit is clear after writing SSPBUF. If the WCOL is set, clear the bit in software and rewrite the SSPBUF register. Date Codes that pertain to this issue: All engineering and production devices. 3. Module: Enhanced Capture/Compare/ PWM (ECCP) With the ECCP configured for Half-Bridge PWM mode (CCP1M3:0 = 1110), the output may be corrupted for particular duty cycle selections. Affected duty cycle values are 0 though 3, and every subsequent increment of 4 (i.e., 7, 11, 15, 19, etc.). Work around None. Date Codes that pertain to this issue: All engineering and production devices. 4. Module: Enhanced Universal Synchronous Receiver Transmitter (EUSART) One bit has been added to the BAUDCON register and one bit has been renamed. The added bit is RXDTP and is in the location, BAUDCON<5>. The renamed bit is the TXCKP bit (BAUDCON<4>), which had been named SCKP. The TXCKP (BAUDCON<4>) and RXDTP (BAUDCON<5>) bits enable the Asynchronous mode TX and RX signals to be inverted (polarity reversed). RXDTP has no effect on the Synchronous mode DT signal. Register 18-3, on page 204, will be changed as shown on page 3. Work around None required. Date Codes that pertain to this issue: All engineering and production devices. DS80282C-page 2 © 2007 Microchip Technology Inc. PIC18F2525/2620/4525/4620 REGISTER 18-3: R/W-0 BAUDCON: BAUD RATE CONTROL REGISTER R-1 ABDOVF RCIDL R/W-0 RXDTP R/W-0 TXCKP R/W-0 U-0 R/W-0 R/W-0 BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is Active bit 5 RXDTP: Receive Data Polarity Select bit (Asynchronous mode only) Asynchronous mode: 1 = Receive data (RX) is inverted. Idle state is a low level. 0 = No inversion of receive data (RX). Idle state is a high level. bit 4 TXCKP: Transmit/Clock Polarity Select bit Asynchronous mode: 1 = Transmit data (TX) is inverted. Idle state is a low level. 0 = No inversion of transmit data (TX). Idle state is a high level. Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level bit 3 BRG16: 16-bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode); SPBRGH value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin with the interrupt generated on the falling edge; bit cleared in hardware on following rising edge 0 = RX pin is not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. © 2007 Microchip Technology Inc. DS80282C-page 3 PIC18F2525/2620/4525/4620 REVISION HISTORY Rev A Document (07/2006) First revision of this document. Silicon issues 1-2 (MSSP) and 3 (ECCP). Rev B Document (04/2007 Added silicon issue 4 (Enhanced Universal Synchronous Receiver Transmitter – EUSART). Rev C Document (09/2007 Modified silicon issue 4 (EUSART). DS80282C-page 4 © 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007 Microchip Technology Inc. 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