MCP47DA1 6-Bit Windowed Volatile DAC with Command Code Package Types Features: MCP47DA1 • 6-Bit DAC: - 65 Taps: 64 Resistors with Taps to Full Scale and Zero Scale (Wiper Code 00h to 40h) - 7-bit Serial Data (00h to 7Fh, 00h - 20h = Zero Scale and 60h-7Fh = Full Scale) • VREF Pull-down Resistance: 30 k (typical) • VOUT Voltage Range: - 1/3 * VREF to 2/3 * VREF • I2C™ Protocol: - Supports SMBus 2.0 Write Byte/Word Protocol Formats - Supports SMBus 2.0 Read Byte/Word Protocol Formats - Slave Addresses: 5Ch and 7Ch • Brown-out Reset Protection (1.5V, typical) • Power-on Default Wiper Setting (Mid-scale) • Low-Power Operation: 100 µA Static Current (typ.) • Wide Operating Voltage Range: - 2.7V to 5.5V – Device Characteristics Specified - 1.8V to 2.7V – Device Operation • Low Tempco: 15 ppm (typical) • 100 kHz (typical) Bandwidth (-3 dB) Operation • Extended Temperature Range (-40°C to +125°C) • Small Packages, SOT-23-6, SC70-6 • Lead Free (Pb-free) Package VDD 1 A VSS 2 B W 6 VREF 5 VOUT SCL 3 4 SDA SOT-23-6, SC70-6 Device Block Diagram VSS SDA SCL 10 K Power-up and Brown-out Control VREF A Wiper Register (RAB = 10K) VDD 2-Wire Interface and Control Logic VOUT B 10 K Description: The MCP47DA1 devices are volatile, 6-Bit digital potentiometers with a buffered output. The wiper setting is controlled through an I2C serial interface. The MCP47DA1. I2C slave addresses of “010 1110” and “011 1110” are supported. The MCP47DA1 has a windowed output (1/3 to 2/3 of VREF). Applications: 2 • PC Servers (I C Protocol with Command Code) • Set Point or Offset Trimming • Cost-sensitive Mechanical Trim Pot Replacement 00h - 7Fh 40h 5Ch, 7Ch 1.8V to 5.5V VOUT Range POR/BOR Value 30.0 VDD Operating Range ( 1) Data Value Range 64 I2C™ Slave Address VREF Resistance I2C™ 65 # of Resistors MCP47DA1 # of Taps Device Interface Device Features Package(s) 1/3 VREF to SOT-23-6, SC70-6 2/3 VREF Note 1: Analog characteristics only tested from 2.7V to 5.5V. 2012-2013 Microchip Technology Inc. DS25118D-page 1 MCP47DA1 NOTES: DS25118D-page 2 2012-2013 Microchip Technology Inc. MCP47DA1 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Voltage on VDD with respect to VSS ......................................................................................................... 0.6V to +7.0V Voltage on SCL, and SDA with respect to VSS ..................................................................................................... -0.6V to VDD + 0.3V Voltage on all other pins (VOUT and VREF) with respect to VSS ..................................................................... -0.3V to VDD + 0.3V Input clamp current, IIK (VI < 0, VI > VDD) .............................................................................................................±20 mA Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA Maximum output current sunk by any Output pin ...................................................................................................25 mA Maximum output current sourced by any Output pin .............................................................................................25 mA Maximum current out of VSS pin ...........................................................................................................................100 mA Maximum current into VDD pin ..............................................................................................................................100 mA Maximum current into VREF pin..............................................................................................................................250 uA Maximum current sourced by VOUT pin ..................................................................................................................40 mA Maximum current sunk by VREF pin ........................................................................................................................40 mA Package power dissipation (TA = +50°C, TJ = +150°C) SOT-23-6...................................................................................................................................................525 mW SC70-6 ......................................................................................................................................................480 mW Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ...............................................................................................-40°C to +125°C ESD protection on all pins 6 kV (HBM) 400V (MM) 1.5 kV (CDM) (for SOT-23) 1.5 kV (CDM) (for SC-70) Latch-up (JEDEC JESD78A) at +125°C ............................................................................................................. ±100 mA Soldering temperature of leads (10 seconds) ....................................................................................................... +300°C Maximum Junction Temperature (TJ) ................................................................................................................... +150°C † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2012-2013 Microchip Technology Inc. DS25118D-page 3 MCP47DA1 AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to +5.5V. CL = 1 nF, RL = 5 k . Typical specifications represent values for VDD = 5.5V, TA = +25°C. Parameters Sym. Min. Typ. Max. Units Supply Voltage VDD 2.7 — 5.5 V Analog Characteristics specified 1.8 — 5.5 V Digital Characteristics specified — — 1.65 V RAM retention voltage (VRAM) < VBOR VDD Start Voltage to ensure wiper to default Reset state VBOR VDD Rise Rate to ensure Power-on Reset VDDRR Delay after device exits the Reset state (VDD > VBOR) to Digital Interface Active TBORD Delay after device exits the Reset state (VDD > VBOR) to VOUT valid TOUTV Supply Current (Note 6) VREF Input Range Note 1: 2: 3: 4: 5: 6: 7: IDD VREF Note 5 — — Conditions V/ms 1 µS 20 µS Within ± 0.5 LSb of VREF/2 (for default POR/BOR wiper value). — 130 200 µA Serial Interface Active, Write all 0’s to volatile wiper, No Load on VOUT VDD = 5.5V, VREF = 1.5V, FSCL = 400 kHz — 100 160 µA Serial Interface Inactive (Static), (Stop condition, SCL = SDA = VIH), No Load on VOUT Wiper = 0, VDD = 5.5V, VREF = 1.5V 1 — VDD V For VDD 3.0V VREF VDD For VDD < 3.0V VREF (VDD - 1.0V)/(2/3) (Note 7) Resistance is defined as the resistance between the VREF pin and the VSS pin. INL and DNL are measured at VOUT from Code = 20h (Zero Scale) through Code = 60h (Full Scale). This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. POR/BOR is not rate dependent. Supply current is independent of VREF current. See Section 7.1.3. DS25118D-page 4 2012-2013 Microchip Technology Inc. MCP47DA1 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) DC Characteristics Parameters All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to +5.5V. CL = 1 nF, RL = 5 k . Typical specifications represent values for VDD = 5.5V, TA = +25°C. Sym. Min. Typ. Max. Units Conditions Minimum Output Voltage VOUT(MIN) — VREF / 3 — V Device Output minimum drive Maximum Output Voltage VOUT(MAX) — 2 * VREF/3 — V Device Output maximum drive Output Amplifier Degree (°) CL = 400 pF, RL = Phase Margin PM — 66 — Slew Rate SR — 0.55 — V/µs Short Circuit Current ISC 5 15 24 mA Settling Time tSETTLING — 6 — µs External Reference (VREF) (Note 3) CVREF — 7 — pF THD — -73 — dB Major Code Transition Glitch — 45 — nV-s Digital Feedthrough — <10 — nV-s Input Capacitance Total Harmonic Distortion VREF = 1.65V ± 0.1V, Frequency = 1 kHz Dynamic Performance (Note 3) Note 1: 2: 3: 4: 5: 6: 7: 1 LSb change around major carry (40h to 3Fh) Resistance is defined as the resistance between the VREF pin and the VSS pin. INL and DNL are measured at VOUT from Code = 20h (Zero Scale) through Code = 60h (Full Scale). This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. POR/BOR is not rate dependent. Supply current is independent of VREF current. See Section 7.1.3. 2012-2013 Microchip Technology Inc. DS25118D-page 5 MCP47DA1 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) DC Characteristics Parameters Resistance (± 20%) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to +5.5V. CL = 1 nF, RL = 5 k . Typical specifications represent values for VDD = 5.5V, TA = +25°C. Sym. Min. Typ. Max. Units RVREF 24.0 30 36.0 k N Step Resistance RS — RVREF / 192 — Nominal Resistance Tempco RVREF/T — 50 — ppm/°C TA = -20°C to +70°C — 100 — ppm/°C TA = -40°C to +85°C — 150 — ppm/°C TA = -40°C to +125°C Ratiometeric Tempco VOUT/T — 15 — ppm/°C Code = Mid-scale (40h) 740 750 760 mV 3.0V VDD 3.6V VREF = 1.5V, code = 40h 5 — — k Resistive Load VOUT Load LVOUTR Taps Note 1 Resolution VOUT Accuracy 65 Conditions No Missing Codes Note 3 LVOUTC — — 1 nF Capacitive Load Maximum current through Terminal (VREF) Note 3 IVREF — — 230 µA VREF = 5.5V Leakage current into VREF IL — 100 — nA VREF = VSS Full-Scale Error (code = 60h) VFSE -1.5 ±0.35 +1.5 LSb 2.7V VDD 5.5V, VREF = 1.65V Zero-Scale Error (code = 20h) VZSE -1.5 ±0.35 +1.5 LSb 2.7V VDD 5.5V, VREF = 1.65V VOUT Integral Non-linearity INL -0.7 ±0.25 +0.7 LSb 2.7V VDD 5.5V (Note 2) VREF = 1.65V VOUT Differential Non-linearity DNL -0.35 ±0.125 +0.35 LSb 2.7V VDD 5.5V (Note 2) VREF = 1.65V Bandwidth -3 dB BW — 100 — kHz VREF = 1.5V ± 0.1V, Code = 40h CREF — 75 — pF f =1 MHz, Code = Full Scale Capacitance (VREF) Note 1: 2: 3: 4: 5: 6: 7: Resistance is defined as the resistance between the VREF pin and the VSS pin. INL and DNL are measured at VOUT from Code = 20h (Zero Scale) through Code = 60h (Full Scale). This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. POR/BOR is not rate dependent. Supply current is independent of VREF current. See Section 7.1.3. DS25118D-page 6 2012-2013 Microchip Technology Inc. MCP47DA1 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to +5.5V. CL = 1 nF, RL = 5 k . Typical specifications represent values for VDD = 5.5V, TA = +25°C. Parameters Sym. Min. Typ. Max. Units Conditions Digital Inputs/Outputs (SDA, SCK) 2.7V VDD 5.5V Schmitt Trigger High Input Threshold VIH 0.7 VDD — — V Schmitt Trigger Low Input Threshold VIL -0.5 — 0.3VDD V Hysteresis of Schmitt Trigger Inputs (Note 3) VHYS — 0.1VDD — V N.A. — — V N.A. — — V 0.1 VDD — — V 0.05 VD — — V VSS — 0.2VDD V VDD < 2.0V, IOL = 1 mA VSS — 0.4 V VDD 2.0V, IOL = 3 mA All inputs except SDA and SCL 100 kHz VDD < 2.0V VDD 2.0V SDA and VDD < 2.0V SCL 400 kHz VDD 2.0V D Output Low Voltage (SDA) VOL Input Leakage Current IIL -1 — 1 µA VREF = VDD and VREF = VSS CIN, COUT — 10 — pF fC = 400 kHz N 0h — 7Fh hex Zero Scale = 00h thru 20h, Full Scale = 60h thru 7Fh Pin Capacitance RAM (Wiper) Value Value Range Wiper POR/BOR Value 40h NPOR/BOR hex Power Requirements Power Supply Sensitivity Note 1: 2: 3: 4: 5: 6: 7: PSS — 0.0015 0.0035 %/% VDD = 2.7V to 5.5V, VREF = 1.65V, Code = 40h Resistance is defined as the resistance between the VREF pin and the VSS pin. INL and DNL are measured at VOUT from Code = 20h (Zero Scale) through Code = 60h (Full Scale). This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. POR/BOR is not rate dependent. Supply current is independent of VREF current. See Section 7.1.3. 2012-2013 Microchip Technology Inc. DS25118D-page 7 MCP47DA1 1.1 I2C Mode Timing Waveforms and Requirements SCL 93 91 90 92 SDA Start Condition Stop Condition I2C Bus Start/Stop Bits Timing Waveforms. FIGURE 1-1: 103 SCL 90 100 102 101 106 91 92 107 SDA In 110 109 109 SDA Out Note 1: Refer to specification D102 (Cb) for load conditions. I2C Bus Data Timing. FIGURE 1-2: I2C BUS START/STOP BITS REQUIREMENTS TABLE 1-1: I2C™ AC Characteristics Param. Symbol No. Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C TA +125C (Extended) Operating Voltage VDD range is described in Section 2.0 “Typical Performance Curves” Characteristic FSCL D102 Cb 90 TSU:STA 91 92 93 Bus capacitive loading Start condition Setup time THD:STA Start condition Hold time TSU:STO Stop condition Setup time THD:STO Stop condition Hold time DS25118D-page 8 Standard mode Fast mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min. Max. Units 0 0 — — 4700 600 4000 600 4000 600 4000 600 100 400 400 400 — — — — — — — — kHz kHz pF pF ns ns ns ns ns ns ns ns Conditions Cb = 400 pF, 1.8V-5.5V Cb = 400 pF, 2.7V-5.5V Only relevant for repeated Start condition After this period, the first clock pulse is generated 2012-2013 Microchip Technology Inc. MCP47DA1 TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE) I2C™ AC Characteristics Param. No. Sym. Characteristic 100 THIGH Clock high time 101 TLOW Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C TA +125C (Extended) Operating Voltage VDD range is described in “AC/DC characteristics” Min. Max. Units 100 kHz mode 4000 — ns 1.8V-5.5V 600 4700 — — ns ns 2.7V-5.5V Clock low time 400 kHz mode 100 kHz mode 1300 — — 1000 ns ns 102A(5) TRSCL SCL rise time 400 kHz mode 100 kHz mode 102B(5) TRSDA SDA rise time 400 kHz mode 100 kHz mode 20 + 0.1Cb — 300 1000 ns ns (5) TFSCL SCL fall time 400 kHz mode 100 kHz mode 20 + 0.1Cb — 300 300 ns ns SDA fall time 400 kHz mode 100 kHz mode 20 + 0.1Cb — 40 300 ns ns 400 kHz mode 300 ns 100 kHz mode 20 + 0.1Cb(5) 0 — ns 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 0 250 100 — — — — 3450 ns ns ns ns 400 kHz mode 100 kHz mode — 4700 900 — ns ns 400 kHz mode 1300 — ns 103A 103B (5) TFSDA 106 THD:DAT Data input hold time 107 TSU:DAT Data input setup time 109 TAA Output valid from clock 110 TBUF Bus free time 2: 3: 4: 5: 6: 1.8V-5.5V 2.7V-5.5V Cb is specified to be from 10 to 400 pF Cb is specified to be from 10 to 400 pF Cb is specified to be from 10 to 400 pF Cb is specified to be from 10 to 400 pF 1.8V-5.5V (Note 6) 2.7V-5.5V (Note 6) Note 5 Note 5 Time the bus must be free before a new transmission can start Philips spec. states N.A. Input filter spike 100 kHz mode — 50 ns suppression 400 kHz mode — 50 ns (SDA and SCL) As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement tsu; DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line. TR max.+tsu; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. The MCP47DA1 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not tested. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. TSP Note 1: Conditions 2012-2013 Microchip Technology Inc. DS25118D-page 9 MCP47DA1 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Sym. Min. Typ. Max. Units TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 6L-SOT-23 JA — 190 — °C/W Note 1 Thermal Resistance, 6L-SC70 JA — 207 — °C/W Note 1 Conditions Temperature Ranges Specified Temperature Range Thermal Package Resistances Note 1: Package Power Dissipation (PDIS) is calculated as follows: PDIS = (TJ - TA) / JA, where: TJ = Junction Temperature, TA = Ambient Temperature. DS25118D-page 10 2012-2013 Microchip Technology Inc. MCP47DA1 2.0 TYPICAL PERFORMANCE CURVES Note 1: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. Typical Device 0.25 0.10 0.10 0.05 0.05 0.00 Ͳ0.05 0.00 Ͳ0.05 Ͳ0.10 Ͳ0.10 Ͳ0.15 Ͳ0.15 Ͳ0.20 Ͳ0.20 Ͳ0.25 Ͳ0.25 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-1: INL vs. Code and Temperature. VDD = 5.5V, VREF = 5.5V. 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-4: INL vs. Code and Temperature. VDD = 3.6V, VREF = 3.6V. Typical Device 0.25 Typical Device 0.25 0.20 0.20 Ͳ40C +25C +85C +125C 0.15 Ͳ40C +25C +85C +125C 0.15 0.10 0.10 0.05 0.05 INL (LSb) INL (LSb) Ͳ40C +25C +85C +125C 0.15 INL (LSb) INL (LSb) 0.20 Ͳ40C +25C +85C +125C 0.15 0.00 Ͳ0.05 0.00 Ͳ0.05 Ͳ0.10 Ͳ0.10 Ͳ0.15 Ͳ0.15 Ͳ0.20 Ͳ0.20 Ͳ0.25 Ͳ0.25 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-2: INL vs. Code and Temperature. VDD = 5.5V, VREF = 1.65V. 0 8 48 56 0.20 Ͳ40C +25C +85C +125C 0.15 24 32 40 DAC Wiper Code 64 Typical Device 0.25 0.20 16 FIGURE 2-5: INL vs. Code and Temperature. VDD = 3.6V, VREF = 1.65V. Typical Device 0.25 Ͳ40C +25C +85C +125C 0.15 0.10 0.10 0.05 0.05 INL (LSb) INL (LSb) Typical Device 0.25 0.20 0.00 Ͳ0.05 0.00 Ͳ0.05 Ͳ0.10 Ͳ0.10 Ͳ0.15 Ͳ0.15 Ͳ0.20 Ͳ0.20 Ͳ0.25 Ͳ0.25 0 8 16 24 32 40 DAC Wiper Code 48 FIGURE 2-3: INL vs. Code and Temperature. VDD = 5.5V, VREF = 1.0V. 2012-2013 Microchip Technology Inc. 56 64 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-6: INL vs. Code and Temperature. VDD = 3.6V, VREF = 1.0V. DS25118D-page 11 MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. Typical Device 0.25 0.20 0.10 0.10 0.05 0.05 0.00 Ͳ0.05 0.00 Ͳ0.05 Ͳ0.10 Ͳ0.10 Ͳ0.15 Ͳ0.15 Ͳ0.20 Ͳ0.20 Ͳ0.25 Ͳ0.25 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-7: INL vs. Code and Temperature. VDD = 3.0V, VREF = 3.0V. 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-10: INL vs. Code and Temperature. VDD = 2.7V, VREF = 1.65V. Typical Device 0.25 Typical Device 0.25 0.20 0.20 Ͳ40C +25C +85C +125C 0.15 Ͳ40C +25C +85C +125C 0.15 0.10 0.10 0.05 0.05 INL (LSb) INL (LSb) Ͳ40C +25C +85C +125C 0.15 INL (LSb) INL (LSb) 0.20 Ͳ40C +25C +85C +125C 0.15 0.00 Ͳ0.05 0.00 Ͳ0.05 Ͳ0.10 Ͳ0.10 Ͳ0.15 Ͳ0.15 Ͳ0.20 Ͳ0.20 Ͳ0.25 Ͳ0.25 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-8: INL vs. Code and Temperature. VDD = 3.0V, VREF = 1.65V. 0 8 16 24 32 40 DAC Wiper Code 48 56 64 56 64 FIGURE 2-11: INL vs. Code and Temperature. VDD = 2.7V, VREF = 1.0V. Typical Device 0.25 Typical Device 0.20 0.20 Ͳ40C +25C +85C +125C 0.15 0.15 0.10 0.10 0.05 0.05 DNL (LSb) INL (LSb) Typical Device 0.25 0.00 Ͳ0.05 0.00 Ͳ0.05 Ͳ0.10 Ͳ0.10 Ͳ0.15 Ͳ40C +25C +85C +125C Ͳ0.15 Ͳ0.20 Ͳ0.25 Ͳ0.20 0 8 16 24 32 40 DAC Wiper Code 48 FIGURE 2-9: INL vs. Code and Temperature. VDD = 3.0V, VREF = 1.0V. DS25118D-page 12 56 64 0 8 16 24 32 40 DAC Wiper Code 48 FIGURE 2-12: DNL vs. Code and Temperature. VDD = 5.5V, VREF = 5.5V 2012-2013 Microchip Technology Inc. MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. 0.10 0.10 0.05 0.05 DNL (LSb) DNL (LSb) 0.15 0.15 0.00 Ͳ0.10 Ͳ0.10 Ͳ40C +25C +85C +125C Ͳ0.15 Ͳ40C +25C +85C +125C Ͳ0.15 Ͳ0.20 Ͳ0.20 0 8 16 24 32 40 DAC Wiper Code 48 56 0 64 16 24 32 40 DAC Wiper Code 48 56 64 56 64 56 64 Typical Device 0.20 Typical Device 0.20 8 FIGURE 2-16: DNL vs. Code and Temperature. VDD = 3.6V, VREF = 1.65V FIGURE 2-13: DNL vs. Code and Temperature. VDD = 5.5V, VREF = 1.65V 0.15 0.15 0.10 0.10 0.05 0.05 DNL (LSb) DNL (LSb) 0.00 Ͳ0.05 Ͳ0.05 0.00 0.00 Ͳ0.05 Ͳ0.05 Ͳ0.10 Ͳ0.10 Ͳ40C +25C +85C +125C Ͳ0.15 Ͳ40C +25C +85C +125C Ͳ0.15 Ͳ0.20 Ͳ0.20 0 8 16 24 32 40 DAC Wiper Code 48 56 0 64 16 24 32 40 DAC Wiper Code 48 Typical Device 0.20 Typical Device 0.20 8 FIGURE 2-17: DNL vs. Code and Temperature. VDD = 3.6V, VREF = 1.0V FIGURE 2-14: DNL vs. Code and Temperature. VDD = 5.5V, VREF = 1.0V 0.15 0.15 0.10 0.10 0.05 0.05 DNL (LSb) DNL (LSb) Typical Device 0.20 Typical Device 0.20 0.00 0.00 Ͳ0.05 Ͳ0.05 Ͳ0.10 Ͳ0.10 Ͳ40C +25C +85C +125C Ͳ0.15 Ͳ40C +25C +85C +125C Ͳ0.15 Ͳ0.20 Ͳ0.20 0 8 16 24 32 40 DAC Wiper Code 48 FIGURE 2-15: DNL vs. Code and Temperature. VDD = 3.6V, VREF = 3.6V 2012-2013 Microchip Technology Inc. 56 64 0 8 16 24 32 40 DAC Wiper Code 48 FIGURE 2-18: DNL vs. Code and Temperature. VDD = 3.0V, VREF = 3.0V DS25118D-page 13 MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. Typical Device 0.15 0.15 0.10 0.10 0.05 0.05 0.00 Ͳ0.05 Ͳ0.10 Ͳ40C +25C +85C +125C Ͳ0.15 Ͳ40C +25C +85C +125C Ͳ0.15 Ͳ0.20 Ͳ0.20 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-19: DNL vs. Code and Temperature. VDD = 3.0V, VREF = 1.65V 0 16 24 32 40 DAC Wiper Code 48 56 Typical Device 1.00 0.90 0.10 0.80 Full Scale Error (LSb) 0.15 0.05 0.00 Ͳ0.05 Ͳ0.10 64 FSE 0.70 0.60 0.50 0.40 0.30 Ͳ40C +25C +85C +125C Ͳ0.15 8 FIGURE 2-22: DNL vs. Code and Temperature. VDD = 2.7V, VREF = 1.0V Typical Device 0.20 DNL (LSb) 0.00 Ͳ0.05 Ͳ0.10 0.20 0.10 Ͳ0.20 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-20: DNL vs. Code and Temperature. VDD = 3.0V, VREF = 1.0V Ͳ40 0 20 40 60 Temperature (°C) 80 100 Typical Device 1.00 0.90 0.10 0.80 Full Scale Error (LSb) 0.15 0.05 0.00 Ͳ0.05 Ͳ0.10 120 FSE 0.70 0.60 0.50 0.40 0.30 Ͳ40C +25C +85C +125C Ͳ0.15 Ͳ20 FIGURE 2-23: Full-Scale Error (FSE) vs. Temperature. VDD = 5.5V, VREF = 5.5V. Typical Device 0.20 DNL (LSb) Typical Device 0.20 DNL (LSb) DNL (LSb) 0.20 0.20 0.10 Ͳ0.20 0 8 16 24 32 40 DAC Wiper Code 48 FIGURE 2-21: DNL vs. Code and Temperature. VDD = 2.7V, VREF = 1.65V DS25118D-page 14 56 64 Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-24: Full-Scale Error (FSE) vs. Temperature. VDD = 5.5V, VREF = 1.65V. 2012-2013 Microchip Technology Inc. MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. Typical Device 0.90 0.90 0.80 0.80 0.70 0.60 0.50 0.40 0.60 0.50 0.40 0.30 0.20 0.20 0.10 Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-25: Full-Scale Error (FSE) vs. Temperature. VDD = 5.5V, VREF = 1.0V. Typical Device 1.00 Ͳ40 0.90 0.90 0.80 0.80 0.60 0.50 0.40 0 20 40 60 Temperature (°C) 80 100 Typical Device 1.00 FSE 0.70 Ͳ20 120 FIGURE 2-28: Full-Scale Error (FSE) vs. Temperature. VDD = 3.6V, VREF = 1.0V Full Scale Error (LSb) Full Scale Error (LSb) FSE 0.70 0.30 0.10 FSE 0.70 0.60 0.50 0.40 0.30 0.30 0.20 0.20 0.10 0.10 Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-26: Full-Scale Error (FSE) vs. Temperature. VDD = 3.6V, VREF = 3.6V. Typical Device 1.00 Ͳ40 0.90 0.90 0.80 0.80 0.60 0.50 0.40 20 40 60 Temperature (°C) 80 100 120 FSE 0.70 0.60 0.50 0.40 0.30 0.30 0.20 0.20 0.10 0 Typical Device 1.00 FSE 0.70 Ͳ20 FIGURE 2-29: Full-Scale Error (FSE) vs. Temperature. VDD = 3.0V, VREF = 3.0V Full Scale Error (LSb) Full Scale Error (LSb) Typical Device 1.00 FSE Full Scale Error (LSb) Full Scale Error (LSb) 1.00 0.10 Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-27: Full-Scale Error (FSE) vs. Temperature. VDD = 3.6V, VREF = 1.65V. 2012-2013 Microchip Technology Inc. Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-30: Full-Scale Error (FSE) vs. Temperature. VDD = 3.0V, VREF = 1.65V. DS25118D-page 15 MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. Typical Device 0.90 0.90 0.80 0.80 0.70 0.60 0.50 0.40 0.60 0.50 0.40 0.30 0.20 0.20 0.10 Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-31: Full-Scale Error (FSE) vs. Temperature. VDD = 3.0V, VREF = 1.0V Typical Device 1.00 Ͳ40 0.90 0.90 0.80 0.80 0.60 0.50 0.40 0 20 40 60 Temperature (°C) 80 100 Typical Device 1.00 FSE 0.70 Ͳ20 120 FIGURE 2-34: Zero-Scale Error (ZSE) vs. Temperature. VDD = 5.5V, VREF = 5.5V Zero Scale Error (LSb) Full Scale Error (LSb) ZSE 0.70 0.30 0.10 ZSE 0.70 0.60 0.50 0.40 0.30 0.30 0.20 0.20 0.10 0.10 Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-32: Full-Scale Error (FSE) vs. Temperature. VDD = 2.7V, VREF = 1.65V. Typical Device 1.00 Ͳ40 0.90 0.90 0.80 0.80 0.60 0.50 0.40 20 40 60 DAC Wiper Code 80 100 120 ZSE 0.70 0.60 0.50 0.40 0.30 0.30 0.20 0.20 0.10 0 Typical Device 1.00 FSE 0.70 Ͳ20 FIGURE 2-35: Zero-Scale Error (ZSE) vs. Temperature. VDD = 5.5V, VREF = 1.65V Zero Scale Error (LSb) Full Scale Error (LSb) Typical Device 1.00 FSE Zero Scale Error (LSb) Full Scale Error (LSb) 1.00 0.10 Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-33: Full-Scale Error (FSE) vs. Temperature. VDD = 2.7V, VREF = 1.0V DS25118D-page 16 Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-36: Zero-Scale Error (ZSE) vs. Temperature. VDD = 5.5V, VREF = 1.0V 2012-2013 Microchip Technology Inc. MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. Typical Device 0.90 0.80 0.80 0.70 0.60 0.50 0.40 0.60 0.50 0.40 0.30 0.20 0.20 0.10 Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-37: Zero-Scale Error (ZSE) vs. Temperature. VDD = 3.6V, VREF = 3.6V Typical Device 1.00 Ͳ40 Ͳ20 0.90 0.90 0.80 0.80 0.60 0.50 0.40 20 40 60 Temperature (°C) 80 100 Typical Device 1.00 ZSE 0.70 0 120 FIGURE 2-40: Zero-Scale Error (ZSE) vs. Temperature. VDD = 3.0V, VREF = 3.0V Zero Scale Error (LSb) Zero Scale Error (LSb) ZSE 0.70 0.30 0.10 ZSE 0.70 0.60 0.50 0.40 0.30 0.30 0.20 0.20 0.10 0.10 Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-38: Zero-Scale Error (ZSE) vs. Temperature. VDD = 3.6V, VREF = 1.65V Typical Device 1.00 Ͳ40 Ͳ20 0.90 0.90 0.80 0.80 0.60 0.50 0.40 80 100 120 ZSE 0.70 0.60 0.50 0.40 0.30 0.30 0.20 0.20 0.10 20 40 60 Temperature (°C) Typical Device 1.00 ZSE 0.70 0 FIGURE 2-41: Zero-Scale Error (ZSE) vs. Temperature. VDD = 3.0V, VREF = 1.65V Zero Scale Error (LSb) Zero Scale Error (LSb) Typical Device 1.00 ZSE 0.90 Zero Scale Error (LSb) Zero Scale Error (LSb) 1.00 0.10 Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-39: Zero-Scale Error (ZSE) vs. Temperature. VDD = 3.6V, VREF = 1.0V 2012-2013 Microchip Technology Inc. Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-42: Zero-Scale Error (ZSE) vs. Temperature. VDD = 3.0V, VREF = 1.0V DS25118D-page 17 MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. Typical Device 1.00 0.80 Total Unadjusted Error (LSb) Zero Scale Error (LSb) 0.80 0.70 0.60 0.50 0.40 0.30 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.20 0.00 0.10 Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 8 16 24 32 40 48 56 64 DAC Wiper Code Typical Device 1.00 0 120 FIGURE 2-43: Zero-Scale Error (ZSE) vs. Temperature. VDD = 2.7V, VREF = 1.65V FIGURE 2-46: Total Unadjusted Error vs. Code and Temperature. VDD = 5.5V, VREF = 1.65V. ZSE Typical Device 1.00 0.90 Ͳ40C +25C +85C +125C 0.90 0.80 0.80 Total Unadjusted Error (LSb) Zero Scale Error (LSb) Ͳ40C +25C +85C +125C 0.90 0.90 0.70 0.60 0.50 0.40 0.30 0.70 0.60 0.50 0.40 0.30 0.20 0.20 0.10 0.10 Ͳ40 Ͳ20 0 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-44: Zero-Scale Error (ZSE) vs. Temperature. VDD = 2.7V, VREF = 1.0V Typical Device 1.00 Ͳ40C +25C +85C +125C 0.90 0.80 0.00 0 8 16 24 32 40 48 56 FIGURE 2-47: Total Unadjusted Error vs. Code and Temperature. VDD = 5.5V, VREF = 1.0V. Typical Device 1.00 Ͳ40C +25C +85C +125C 0.90 0.70 0.80 0.60 0.50 0.40 0.30 0.20 0.10 64 DAC Wiper Code Total Unadjusted Error (LSb) Total Unadjusted Error (LSb) Typical Device 1.00 ZSE 0.70 0.60 0.50 0.40 0.30 0.20 0.00 0 8 16 24 32 40 48 56 64 DAC Wiper Code FIGURE 2-45: Total Unadjusted Error vs. Code and Temperature. VDD = 5.5V, VREF = 5.5V. DS25118D-page 18 0.10 0.00 0 8 16 24 32 40 48 56 64 DAC Wiper Code FIGURE 2-48: Total Unadjusted Error vs. Code and Temperature. VDD = 3.6V, VREF = 3.6V. 2012-2013 Microchip Technology Inc. MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. Typical Device 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.70 0.60 0.50 0.40 0.30 0.20 0.20 0.10 0.10 0.00 0.00 0 8 16 24 32 40 48 56 64 0 8 16 DAC Wiper Code Typical Device 1.00 32 40 48 56 64 FIGURE 2-52: Total Unadjusted Error vs. Code and Temperature. VDD = 3.0V, VREF = 1.65V. Typical Device 1.00 Ͳ40C +25C +85C +125C 0.90 Ͳ40C +25C +85C +125C 0.90 0.80 Total Unadjusted Error (LSb) 0.80 Total Unadjusted Error (LSb) 24 DAC Wiper Code FIGURE 2-49: Total Unadjusted Error vs. Code and Temperature. VDD = 3.6V, VREF = 1.65V. 0.70 0.60 0.50 0.40 0.30 0.70 0.60 0.50 0.40 0.30 0.20 0.20 0.10 0.10 0.00 0.00 0 8 16 24 32 40 48 56 64 0 8 16 DAC Wiper Code Typical Device 1.00 24 32 40 48 56 64 DAC Wiper Code FIGURE 2-50: Total Unadjusted Error vs. Code and Temperature. VDD = 3.6V, VREF = 1.0V. FIGURE 2-53: Total Unadjusted Error vs. Code and Temperature. VDD = 3.0V, VREF = 1.0V. Typical Device 1.00 Ͳ40C +25C +85C +125C 0.90 Ͳ40C +25C +85C +125C 0.90 0.80 Total Unadjusted Error (LSb) 0.80 Total Unadjusted Error (LSb) Ͳ40C +25C +85C +125C 0.90 Total Unadjusted Error (LSb) 0.80 Total Unadjusted Error (LSb) Typical Device 1.00 Ͳ40C +25C +85C +125C 0.70 0.60 0.50 0.40 0.30 0.70 0.60 0.50 0.40 0.30 0.20 0.20 0.10 0.10 0.00 0.00 0 8 16 24 32 40 48 56 64 DAC Wiper Code FIGURE 2-51: Total Unadjusted Error vs. Code and Temperature. VDD = 3.0V, VREF = 3.0V. 2012-2013 Microchip Technology Inc. 0 8 16 24 32 40 48 56 64 DAC Wiper Code FIGURE 2-54: Total Unadjusted Error vs. Code and Temperature. VDD = 2.7V, VREF = 1.65V. DS25118D-page 19 MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. Typical Device 1.00 0.80 3.00 0.70 2.00 0.60 0.50 0.40 1.00 0.00 Ͳ1.00 0.30 Ͳ2.00 0.20 Ͳ3.00 0.10 Ͳ4.00 0.00 0 8 16 24 32 40 48 56 Ͳ5.00 64 0 8 16 DAC Wiper Code FIGURE 2-55: Total Unadjusted Error vs. Code and Temperature. VDD = 2.7V, VREF = 1.0V. Typical Device 5.00 2.0 1.00 1.0 PPM per °C PPM per °C 3.0 0.00 Ͳ1.00 Ͳ2.0 Ͳ3.0 Ͳ4.00 Ͳ4.0 Ͳ5.00 48 56 Typical Device Ͳ5.0 64 FIGURE 2-56: VOUT Tempco vs. Code ( ( ( (VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) ) / 165 ) * 1,000,000 ), VDD = 5.5V, VREF = 5.5V. 5.00 0 2.0 1.00 1.0 PPM per °C 3.0 0.00 Ͳ1.00 Ͳ2.0 Ͳ3.0 Ͳ4.00 Ͳ4.0 Ͳ5.00 48 56 64 FIGURE 2-57: VOUT Tempco vs. Code ( ( ( (VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) ) / 165 ) * 1,000,000 ), VDD = 5.5V, VREF = 1.65V. DS25118D-page 20 56 64 PPM C Ͳ1.0 Ͳ3.00 24 32 40 DAC Wiper Code 48 0.0 Ͳ2.00 16 24 32 40 DAC Wiper Code 4.0 2.00 8 16 Typical Device 5.0 3.00 0 8 FIGURE 2-59: VOUT Tempco vs. Code ( ( ( (VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) ) / 165 ) * 1,000,000 ), VDD = 3.6V, VREF = 3.6V. PPM C 4.00 PPM C 0.0 Ͳ3.00 24 32 40 DAC Wiper Code 64 Ͳ1.0 Ͳ2.00 16 56 4.0 2.00 8 48 Typical Device 5.0 3.00 0 24 32 40 DAC Wiper Code FIGURE 2-58: VOUT Tempco vs. Code ( ( ( (VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) ) / 165 ) * 1,000,000 ), VDD = 5.5V, VREF = 1.0V. PPM C 4.00 PPM per °C PPM C 4.00 PPM per °C Total Unadjusted Error (LSb) Typical Device 5.00 Ͳ40C +25C +85C +125C 0.90 Ͳ5.0 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-60: VOUT Tempco vs. Code ( ( ( (VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) ) / 165 ) * 1,000,000 ), VDD = 3.6V, VREF = 1.65V. 2012-2013 Microchip Technology Inc. MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. Typical Device 5.0 3.0 2.0 2.0 1.0 1.0 PPM per °C PPM per °C 3.0 0.0 Ͳ1.0 0.0 Ͳ1.0 Ͳ2.0 Ͳ2.0 Ͳ3.0 Ͳ3.0 Ͳ4.0 Ͳ4.0 Ͳ5.0 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-61: VOUT Tempco vs. Code ( ( ( (VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) ) / 165 ) * 1,000,000 ), VDD = 3.6V, VREF = 1.0V. Typical Device 5.0 0 8 16 24 32 40 DAC Wiper Code 48 56 Typical Device 5.0 PPM C 4.0 3.0 2.0 2.0 1.0 1.0 PPM per °C 3.0 0.0 Ͳ1.0 64 FIGURE 2-64: VOUT Tempco vs. Code ( ( ( (VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) ) / 165 ) * 1,000,000 ), VDD = 3.0V, VREF = 1.0V. PPM C 4.0 PPM per °C PPM C 4.0 Ͳ5.0 0.0 Ͳ1.0 Ͳ2.0 Ͳ2.0 Ͳ3.0 Ͳ3.0 Ͳ4.0 Ͳ4.0 Ͳ5.0 Ͳ5.0 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-62: VOUT Tempco vs. Code ( ( ( (VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) ) / 165 ) * 1,000,000 ), VDD = 3.0V, VREF = 3.0V. Typical Device 5.0 0 8 16 24 32 40 DAC Wiper Code 48 56 Typical Device 5.0 PPM C 4.0 3.0 2.0 2.0 1.0 1.0 PPM per °C 3.0 0.0 Ͳ1.0 0.0 Ͳ1.0 Ͳ2.0 Ͳ2.0 Ͳ3.0 Ͳ3.0 Ͳ4.0 Ͳ4.0 Ͳ5.0 64 FIGURE 2-65: VOUT Tempco vs. Code ( ( ( (VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) ) / 165 ) * 1,000,000 ), VDD = 2.7V, VREF = 1.65V. PPM C 4.0 PPM per °C Typical Device 5.0 PPM C 4.0 Ͳ5.0 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-63: VOUT Tempco vs. Code ( ( ( (VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) ) / 165 ) * 1,000,000 ), VDD = 3.0V, VREF = 1.65V. 2012-2013 Microchip Technology Inc. 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-66: VOUT Tempco vs. Code ( ( ( (VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) ) / 165 ) * 1,000,000 ), VDD = 2.7V, VREF = 1.0V. DS25118D-page 21 MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. Typical Device 0.25 0.20 2.55V 0.20 1.65V 1.0V 0.15 0.10 0.10 0.05 0.05 INL (LSb) INL (LSb) 0.15 0.00 Ͳ0.05 0.00 Ͳ0.05 Ͳ0.10 Ͳ0.10 Ͳ0.15 Ͳ0.15 Ͳ0.20 Ͳ0.20 Ͳ0.25 Ͳ0.25 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-67: INL vs. Code and VREF. VDD = 5.5V, VREF = 1V, 1.65V, 2.7V, and 5.5V, Temp = +25°C. Typical Device 0.25 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-70: INL vs. Code and VREF. VDD = 2.7V, VREF = 1V, 1.65V, and 2.55V, Temp = +25°C. Typical Device 0.20 3.6V 1.65V 1.0V 0.20 0.15 0.15 0.10 0.10 0.05 0.05 DNL (LSb) INL (LSb) Typical Device 0.25 5.5V 2.7V 1.65V 1.0V 0.00 Ͳ0.05 0.00 Ͳ0.05 Ͳ0.10 Ͳ0.10 Ͳ0.15 5.5V 2.7V 1.65V 1.0V Ͳ0.15 Ͳ0.20 Ͳ0.25 Ͳ0.20 0 8 16 24 32 40 DAC Wiper Code 48 56 FIGURE 2-68: INL vs. Code and VREF. VDD = 3.6V, VREF = 1V, 1.65V, and 3.6V, Temp = +25°C. Typical Device 0.25 0 64 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-71: DNL vs. Code and VREF. VDD = 5.5V, VREF = 1V, 1.65V, 2.7V, and 5.5V, Temp = +25°C. Typical Device 0.20 3.0V 1.65V 1.0V 0.20 8 0.15 0.15 0.10 0.05 0.05 DNL (LSb) INL (LSb) 0.10 0.00 Ͳ0.05 0.00 Ͳ0.05 Ͳ0.10 Ͳ0.10 Ͳ0.15 3.6V 1.65V 1.0V Ͳ0.15 Ͳ0.20 Ͳ0.20 Ͳ0.25 0 8 16 24 32 40 DAC Wiper Code 48 56 FIGURE 2-69: INL vs. Code and VREF. VDD = 3.0V, VREF = 1V, 1.65V, and 5.5V, Temp = +25°C. DS25118D-page 22 64 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-72: DNL vs. Code and VREF. VDD = 3.6V, VREF = 1V, 1.65V, and 3.6V, Temp = +25°C. 2012-2013 Microchip Technology Inc. MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. Typical Device 0.20 0.80 Total Unadjusted Error (LSb) 0.10 DNL (LSb) 0.05 0.00 Ͳ0.05 Ͳ0.10 0.70 0.60 0.50 0.40 0.30 0.20 3.0V 1.65V 1.0V Ͳ0.15 0.10 0.00 Ͳ0.20 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-73: DNL vs. Code and VREF. VDD = 3.0V, VREF = 1V, 1.65V, and 3.0V, Temp = +25°C. 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-76: Total Unadjusted Error vs. Code and VREF. VDD = 3.6V, VREF = 1V, 1.65V, and 3.6V, Temp = +25°C. Typical Device 0.20 Typical Device 1.00 3.0V 1.65V 1.0V 0.90 0.15 0.80 Total Unadjusted Error (LSb) 0.10 0.05 DNL (LSb) 3.6V 1.65V 1.0V 0.90 0.15 0.00 Ͳ0.05 Ͳ0.10 0.70 0.60 0.50 0.40 0.30 0.20 2.55V 1.65V Ͳ0.15 0.10 1.0V 0.00 Ͳ0.20 0 8 16 24 32 40 DAC Wiper Code 48 56 Typical Device 1.00 0 64 FIGURE 2-74: DNL vs. Code and VREF. VDD = 2.7V, VREF = 1V, 1.65V, and 2.55V, Temp = +25°C. 16 24 32 40 DAC Wiper Code 48 56 Typical Device 1.00 64 2.55V 0.90 1.65V 1.0V 0.80 Total Unadjusted Error (LSb) 0.80 8 FIGURE 2-77: Total Unadjusted Error vs. Code and VREF. VDD = 3.0V, VREF = 1V, 1.65V, and 5.5V, Temp = +25°C. 5.5V 2.7V 1.65V 1.0V 0.90 Total Unadjusted Error (LSb) Typical Device 1.00 0.70 0.60 0.50 0.40 0.30 0.20 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.10 0.00 0.00 0 8 16 24 32 40 48 56 64 DAC Wiper Code FIGURE 2-75: Total Unadjusted Error vs. Code and VREF. VDD = 5.5V, VREF = 1V, 1.65V, 2.7V, and 5.5V, Temp = +25°C. 2012-2013 Microchip Technology Inc. 0 8 16 24 32 40 DAC Wiper Code 48 56 64 FIGURE 2-78: Total Unadjusted Error vs. Code and VREF. VDD = 2.7V, VREF = 1V, 1.65V, and 2.55V, Temp = +25°C. DS25118D-page 23 MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. 1.0 170 0.9 0.7 0.6 0.5 130 120 110 100 90 0.3 80 70 0.2 Ͳ40 0 Ͳ20 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-79: VIH / VIL Threshold of SDA/SCL Inputs vs. Temperature and VDD. Ͳ40 0 Ͳ20 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-82: Interface Active Current (IDD) vs. SCL Frequency (fSCL) and Temperature VDD = 2.7V and 5.5V, VREF = 1.5V and VDD. (no load on VOUT). 0.14 [email protected] 0.12 170 [email protected] 0.10 160 [email protected] [email protected] [email protected] 150 0.08 [email protected] 140 IDD Static (ȝA) Voltage / VDD [email protected] 140 0.4 0.06 0.04 0.02 130 120 110 100 90 0.00 Ͳ40 0 Ͳ20 FIGURE 2-80: Temperature. 20 40 60 Temperature (°C) 80 100 120 70 Ͳ40 0 Ͳ20 20 40 60 Temperature (°C) 80 100 120 FIGURE 2-83: Interface Inactive Current (ISHDN) vs. Temperature. VDD = 2.7V and 5.5V, VREF = 1.5V and VDD. (no load on VOUT, SCL = SDA = VDD). Ͳ40C +25C +85C +125C 1.00 80 VOL (SDA) vs. VDD and 1.20 0.80 5 Code = FFFh Code = 000h 0.60 4 0.40 VOUT (V) VOUT (V) (VREF = 1.5V) [email protected] 150 IDD Active (ȝA) Voltage / VDD 0.8 [email protected] 160 [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] 0.20 3 2 0.00 0 0.3 0.6 0.9 1.2 VDD (V) 1.5 1.8 2.1 2.4 FIGURE 2-81: VOUT vs. VDD and Temperature. For VDD Power-Up and PowerDown with VREF = 1.5V. 2.7 1 0 0 3 6 9 ISOURCE/SINK (mA) 12 15 FIGURE 2-84: VOUT vs. Source/Sink Current. VDD = 5.0V. DS25118D-page 24 2012-2013 Microchip Technology Inc. MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. 3 5 Code = FFFh Code = FFFh 2.5 4 2 VOUT (V) VOUT (V) 3 1.5 2 1 1 0.5 0 0 0 1000 2000 3000 Load Resistance (RL) (:) FIGURE 2-85: VDD = 5.0V. 4000 5000 VOUT vs. Resistive Load. 0 1000 FIGURE 2-88: VDD = 3.0V. 2.0 4000 5000 VOUT vs. Resistive Load. 32000 1.5 [email protected] [email protected] 31800 1.0 [email protected] 0.5 Resistance (:) Voltage from Target (0.75V) (mV) 2000 3000 Load Resistance (RL) (:) 0.0 Ͳ0.5 31600 31400 [email protected] Ͳ1.0 31200 [email protected] Ͳ1.5 [email protected] 31000 Ͳ2.0 Ͳ40 0 Ͳ20 FIGURE 2-86: Temperature. 20 40 60 Temperature (°C) 80 100 120 VOUT Accuracy vs. VDD and Ͳ40 Ͳ20 0 FIGURE 2-89: and Temperature. 20 40 60 Temperature (°C) 80 100 120 RVREF Resistances vs. VDD 3 Code = FFFh Code = 000h 2.5 VOUT (V) 2 1.5 1 0.5 0 0 3 6 9 ISOURCE/SINK (mA) 12 15 FIGURE 2-87: VOUT vs. Source/Sink Current. VDD = 3.0V. 2012-2013 Microchip Technology Inc. DS25118D-page 25 MCP47DA1 Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF. FIGURE 2-90: Zero-Scale to Full-Scale Settling Time (20h to 60h), VDD = 5.0V, VREF = 5.0V, RL = 5k, CL = 1nF. FIGURE 2-92: Half-Scale Settling Time (30h to 50h), VDD = 5.0V, VREF = 5.0V, RL = 5k, CL = 1nF. FIGURE 2-91: Full-Scale to Zero-Scale Settling Time (60h to 20h), VDD = 5.0V, VREF = 5.0V, RL = 5k, CL = 1nF. FIGURE 2-93: Half-Scale Settling Time (50h to 30h), VDD = 5.0V, VREF = 5.0V, RL = 5k, CL = 1nF. FIGURE 2-94: Digital Feedthrough (SCL signal coupling to VOUT pin); VOUT = 40h, FSCL = 100kHz, VDD = 5.0V, VREF = 5.0V. DS25118D-page 26 2012-2013 Microchip Technology Inc. MCP47DA1 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follow. TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP47DA1 Package Pin Name SC70-6 Pin Type Buffer Type SOT-23-6 VDD 1 1 P — Positive Power Supply Input VSS 2 2 P — Ground SCL 3 3 I/O ST (OD) I2C™ Serial Clock pin SDA 4 4 I/O ST (OD) I2C Serial Data pin VOUT 5 5 I/O A Output voltage VREF 6 6 I/O A Reference Voltage for VOUT output Legend: A = Analog input I = Input 3.1 Function ST (OD) = Schmitt Trigger with Open Drain O = Output I/O = Input/Output Positive Power Supply Input (VDD) 3.5 P = Power Analog Output Voltage Pin (VOUT) The VDD pin is the device’s positive power supply input. The input power supply is relative to VSS and can range from 1.8V to 5.5V. A decoupling capacitor on VDD (to VSS) is recommended to achieve maximum performance. Analog specifications are tested from 2.7V. VOUT can swing from approximately VZS = 1/3 * VREF to VFS = 2/3 * VREF. In Normal mode, the DC impedance of the output pin is about 1. See Section 7.0 “Output Buffer” for more information. 3.2 3.6 Ground (VSS) The VSS pin is the device ground reference. 3.3 I2C Serial Clock (SCL) The SCL pin is the serial clock pin of the I2C interface. The MCP47DA1 acts only as a slave and the SCL pin accepts only external serial clocks. The SCL pin is an open-drain output. Refer to Section 5.0 “Serial Interface – I2C Module” for more details of I2C Serial Interface communication. 3.4 VOUT is the DAC analog output pin. The DAC output has an output amplifier. Voltage Reference Pin (VREF) This pin is the external voltage reference input. The VREF pin signal is unbuffered so the reference voltage must have the current capability not to drop its voltage when connected to the internal resistor ladder circuit (30 k typical). See Section 6.0 “Resistor Network” for more information. I2C Serial Data (SDA) The SDA pin is the serial data pin of the I2C interface. The SDA pin has a Schmitt Trigger input and an open-drain output. Refer to Section 5.0 “Serial Interface – I2C Module” for more details of I2C Serial Interface communication. 2012-2013 Microchip Technology Inc. DS25118D-page 27 MCP47DA1 NOTES: DS25118D-page 28 2012-2013 Microchip Technology Inc. MCP47DA1 4.0 GENERAL OVERVIEW VREF The MCP47DA1 device is a general purpose DAC intended to be used in applications where a programmable voltage output with moderate bandwidth is desired. R1 A Applications generally suited for the MCP47DA1 devices include: Computer servers Set point or offset trimming Sensor calibration Cost-sensitive mechanical trim pot replacement The MCP47DA1 has four main functional blocks. These are: • • • • POR/BOR Operation Serial Interface – I2C Module Resistor Network Output Buffer The POR/BOR operation is discussed in this section and the I2C and Resistor Network operation are described in their own sections. The commands are discussed in Section 5.3, Serial Commands. Figure 4-1 shows a block diagram for the resistive network of the device. An external pin, called VREF, is the DAC’s reference voltage. The resistance from the VREF pin to ground is typically 30 k. The reference voltage connected to the VREF pin needs to support this resistive load. This resistor network functions as a windowed voltage divider. This means that the VOUT pin’s voltage range is from approximately 1/3 * VREF to approximately 2/3 * VREF. This windowed range is determined by the 10 k resistors (R1 and R2) that window the 10 k digital potentiometer (see Figure 4-1). RW (1) RS RW (1) RS Goes to Output Buffer’s input RAB • • • • RFS W RW (1) RS RW (1) Analog Switch MUX RZS B R2 + Op Amp - VOUT Note 1: The wiper resistance is tap dependent. That is, each tap selection resistance has a small variation. 2: The RFS and RZS resistances are determined by the analog switches that connect the resistor network to the other circuitry. FIGURE 4-1: Resistor Network and Output Buffer Block Diagram. 2012-2013 Microchip Technology Inc. DS25118D-page 29 MCP47DA1 4.1 POR/BOR Operation 4.1.2 BROWN-OUT RESET The Power-on Reset is the case where the device is having power applied to it from VSS. The Brown-out Reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. When the device powers down, the device VDD will cross the VPOR/VBOR voltage (VBOR < 1.8V). Once the VDD voltage decreases below the VPOR/VBOR voltage, the following happens: The device’s RAM retention voltage (VRAM) is lower than the POR/BOR voltage trip point (VPOR/VBOR). This ensures that when the device Power-on Reset occurs, the logic can retain the default values that are loaded. The maximum VPOR/VBOR voltage is less than 1.8V. When VPOR/VBOR < VDD < 2.7V, the DACs’ electrical performance may not meet the data sheet specifications. If the VDD voltage decreases below the VRAM voltage, the following happens: Table 4-2 shows the DAC’s level of functionality across the entire VDD range, while Figure 4-2 illustrates the Power-up and Brown-out functionality. 4.1.1 POWER-ON RESET When the device powers up, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage crosses the VPOR/VBOR voltage, the following happens: • Volatile serial shift register/wiper register is loaded with the default values (see Table 4-1) • The device is capable of digital operation Note: At voltages below VDD(MIN), the electrical performance of the I2C interface may not meet the data sheet specifications TABLE 4-1: DEFAULT POR WIPER SETTING SELECTION Default POR Wiper Setting Serial Shift Register (SSR) Wiper Register Mid-scale 40h 20h TABLE 4-2: VDD Level • Serial Interface is disabled • Volatile Serial Shift Register (SSR) and wiper register may become corrupted As the voltage recovers above the VPOR/VBOR voltage, see Section 4.1.1 “Power-on Reset”. Serial commands not completed due to a brown-out condition may cause the memory location to become corrupted. 4.1.3 WIPER REGISTER (RAM) The wiper register is 7-bit volatile memory that starts functioning at the RAM retention voltage (VRAM). The wiper register will be loaded with the default wiper value when VDD rises above the VPOR/VBOR voltage. 4.1.4 DEVICE CURRENTS The current of the device can be classified into two modes of the device operation. These are: • Serial Interface Inactive (Static Operation) • Serial Interface Active Static Operation occurs when a Stop condition is received. Static Operation is exited when a Start condition is received. DEVICE FUNCTIONALITY AT EACH VDD REGION (Note 1) Serial Interface VDD < VTH Ignored VTH < VDD < VBOR Ignored VBOR VDD < 1.8V Unknown VOUT DAC Register Setting Comment Unknown Unknown DAC register loaded with POR/BOR value < 2.7V Accepted DAC register determines Electrical performance may 1.8V VDD serial Value not meet the data sheet specifications. DAC register determines Meets the data sheet 2.7V VDD 5.5V Accepted Operational serial value specifications Note 1: For system voltages below the minimum operating voltage, it is recommended to use a voltage supervisor to hold the system in Reset. This will ensure that MCP47X1 commands are not attempted out of the operating range of the device. DS25118D-page 30 Unknown Pulled Low Operational with reduced electrical specifications Operational with reduced electrical specifications 2012-2013 Microchip Technology Inc. MCP47DA1 Normal Operation Range VDD Outside Specified AC/DC Range Normal Operation Range 2.7V 1.8V VPOR/BOR VRAM VSS FIGURE 4-2: Analog characteristics not specified Analog characteristics not specified Device’s Serial Interface is VBOR delay “Not Operational” Wiper forced to default POR/BOR setting Power-up and Brown-out. 2012-2013 Microchip Technology Inc. DS25118D-page 31 MCP47DA1 NOTES: DS25118D-page 32 2012-2013 Microchip Technology Inc. MCP47DA1 5.0 SERIAL INTERFACE – I2C MODULE 5.1 A 2-wire I2C serial protocol is used to write or read the DAC’s wiper register. The I2C protocol utilizes the SCL input pin and SDA input/output pin. The I2C serial interface supports the following features: • Slave mode of operation • 7-bit addressing • The following clock rate modes are supported: - Standard mode, bit rates up to 100 kb/s - Fast mode, bit rates up to 400 kb/s • Support multi-master applications The serial clock is generated by the master. The I2C module is compatible with the NXP I2C specification (UM10204). Only the field types, field lengths, timings, etc. of a frame are defined. The frame content defines the behavior of the device. The frame content for the MCP47DA1 device is defined in this section of the data sheet. Figure 5-1 shows a typical I2C bus configuration. Single I2C™ Bus Configuration Device 1 Device 3 Device 2 FIGURE 5-1: Configurations. I2C specifications require active-low, passive-high functionality on devices interfacing to the bus. Since devices may be operating on separate power supply sources, ESD clamping diodes are not permitted. The specification recommends using open drain transistors tied to VSS (common) with a pull-up resistor. The specification makes some general recommendations on the size of this pull-up, but does not specify the exact value since bus speeds and bus capacitance impact the pull-up value for optimum system performance. Common pull-up values range from 1 k to a maximum of ~10 k. Power sensitive applications tend to choose higher values to minimize current losses during communication but these applications also typically utilize lower VDD. The SDA and SCL float (are not driving) when the device is powered down. A “glitch” filter is on the SCL and SDA pins when the pin is an input. When these pins are an output, there is a slew rate control of the pin that is independent of device frequency. 5.1.1 Device n Host Controller Device 4 I2C I/O Considerations SLOPE CONTROL The device implements slope control on the SDA output. The slope control is defined by the Fast mode specifications. For Fast (FS) mode, the device has spike suppression and Schmitt Trigger inputs on the SDA and SCL pins. Typical Application I2C Bus Refer to Section 2.0 “Typical Performance Curves”, AC/DC Electrical Characteristics table for detailed input threshold and timing specifications. 2012-2013 Microchip Technology Inc. DS25118D-page 33 MCP47DA1 5.2 I2C Bit Definitions If the slave address is not valid, the slave device will issue a Not A (A). The A bit will have the SDA signal high. I2C bit definitions include: • • • • • • Start Bit Data Bit Acknowledge (A) Bit Repeated Start Bit Stop Bit Clock Stretching If an error condition occurs (such as an A instead of A) then a Start bit must be issued to reset the command state machine. TABLE 5-1: Figure 5-8 shows the waveform for these states. 5.2.1 START BIT The Start bit (see Figure 5-2) indicates the beginning of a data transfer sequence. The Start bit is defined as the SDA signal falling when the SCL signal is “High”. Acknowledge Bit Response Event General Call A Slave Address valid A Slave Address not valid A Bus Collision N.A. 2nd Bit 1st Bit SDA SCL S FIGURE 5-2: 5.2.2 Start Bit. 5.2.4 DATA BIT The SDA signal may change state while the SCL signal is Low. While the SCL signal is High, the SDA signal MUST be stable (see Figure 5-3). 2nd Bit 1st Bit SDA SCL FIGURE 5-3: 5.2.3 REPEATED START BIT The Start bit is the beginning of a data transfer sequence and is defined as the SDA signal falling when the SCL signal is “High”. ACKNOWLEDGE (A) BIT SCL • SDA is sampled low when SCL goes from low to high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. SDA 8 I2C module resets, or a “Don’t Care” if the collision occurs on the masters “Start bit”. Note 1: A bus collision during the Repeated Start condition occurs if: Data Bit. D0 Comment The Repeated Start bit (see Figure 5-5) indicates the current master device wishes to continue communicating with the current slave device without releasing the I2C bus. The Repeated Start condition is the same as the Start condition, except that the Repeated Start bit follows a Start bit (with the data bits + A bit) and not a Stop bit. The A bit (see Figure 5-4) is a response from the slave device to the master device. Depending on the context of the transfer sequence, the A bit may indicate different things. Typically the slave device will supply an A response after the Start bit and eight “data” bits have been received. The A bit will have the SDA signal low. SDA MCP47DA1 A/A RESPONSES 1st Bit A 9 SCL FIGURE 5-4: Acknowledge Waveform. Sr = Repeated Start FIGURE 5-5: Waveform. DS25118D-page 34 Repeat Start Condition 2012-2013 Microchip Technology Inc. MCP47DA1 5.2.5 STOP BIT 5.2.7 If any part of the I2C transmission does not meet the command format, it is aborted. This can be intentionally accomplished with a Start or Stop condition. This is done so that noisy transmissions (usually an extra Start or Stop condition) are aborted before they corrupt the device. The Stop bit (see Figure 5-6) indicates the end of the I2C data transfer sequence. The Stop bit is defined as the SDA signal rising when the SCL signal is “High”. A Stop bit resets the I2C interface of the other devices. SDA A / A 5.2.8 SCL 5.2.6 IGNORING AN I2C TRANSMISSION AND “FALLING OFF” THE BUS The MCP47DA1 expects to receive entire, valid I2C commands and will assume any command not defined as a valid command is due to a bus corruption, and will enter a passive high condition on the SDA signal. All signals will be ignored until the next valid Start condition and control byte are received. P FIGURE 5-6: Transmit Mode. ABORTING A TRANSMISSION Stop Condition Receive or CLOCK STRETCHING “Clock Stretching” is something that the secondary device can do, to allow additional time to “respond” to the “data” that has been received. The MCP47DA1 will not stretch the clock signal (SCL) since memory read accesses occur fast enough. SDA SCL S FIGURE 5-7: 1st 2nd 3rd 4th 5th 6th 7th 8th A/A 1st 2nd 3rd 4th 5th 6th 7th 8th A/A Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit P Typical 16-bit I2C Waveform Format. SDA SCL Start Condition FIGURE 5-8: Data allowed to change Data or A valid Stop Condition I2C Data States and Bit Sequence. 2012-2013 Microchip Technology Inc. DS25118D-page 35 MCP47DA1 I2C COMMAND PROTOCOL 5.2.9 TABLE 5-2: The MCP47DA1 is a slave I2C device which supports 7-bit slave addressing. The slave address contains seven fixed bits. Figure 5-9 shows the control byte format. 5.2.9.1 Control Byte (Slave Address) The control byte is always preceded by a Start condition. The control byte contains the slave address consisting of seven fixed bits and the R/W bit. Figure 5-9 shows the control byte format and Table 5-2 shows the I2C address for the devices. Slave Address S A6 A5 A4 A3 A2 A1 A0 R/W “0” “1” “0” “1” “1” “1” “0” Start bit A/A Note 1: The MCP47DA1 device supports two different I2C address (A0 and A1). This allows two MCP47DA1 device on the same I2C bus. Hardware Address Pins The MCP47DA1 does not support hardware address bits. A bit (controlled by slave device) A = 0 = Slave device Acknowledges byte A = 1 = Slave device does not Acknowledge byte FIGURE 5-9: I2C Control Byte. I2C™ Address Binary Hex (1) Code Comment MCP47DA1 ‘0101110’ 0x5C A0 ‘0111110’ 0x7C A1 Note 1: The LSb of the 8-bit hex code is the I2C Read/Write (R/W) bit. This hex value has a R/W bit = “0” (write). If the R/W bit reflected a read, this values would be 0x5D and 0x7D. Device 5.2.9.2 R/W bit R/W = 0 = write R/W = 1 = read DEVICE I2C ADDRESS Slave Address Bits in the 5.2.10 GENERAL CALL The General Call is a method that the master device can communicate with all other slave devices. The MCP47DA1 devices do not respond to General Call address and commands, and therefore the communications are Not Acknowledged. Second Byte S 0 0 0 0 0 0 0 0 A General Call Address X X X X X X X 0 A P “7-bit Command” Reserved 7-bit Commands (By I2C™ Specification – NXP specification # UM10204, Ver. 03 16 January 2007) “0000 011”b - Reset and write programmable part of slave address by hardware “0000 010”b - Write programmable part of slave address by hardware “0000 000”b - NOT Allowed The Following is a “Hardware General Call” Format Second Byte S 0 0 0 0 0 0 0 0 A General Call Address FIGURE 5-10: DS25118D-page 36 n occurrences of (Data + A / A) X X X X X X X 1 A X X X X X X X X “7-bit Command” A P This indicates a “Hardware General Call”. MCP47DA1 will ignore this byte and all following bytes (and A), until a Stop bit (P) is encountered. General Call Formats. 2012-2013 Microchip Technology Inc. MCP47DA1 5.3 Serial Commands The MCP47DA1 devices support commands. These commands are: 5.3.2 two serial • Write Operation • Read Operation The I2C command formats have been defined to support the SMBus version 2.0 Write Byte/Word Protocol formats and Read Byte/Word Protocol formats. The SMBus specification that defines this operation is Section 5 of the Version 2.0 document (August 3, 2000). This protocol format may be convenient for customers using library routines for the I2C bus, where all they need to do is specify the command (Read, Write, ...) with the device address, the register address, and the data. 5.3.1 WRITE OPERATION The write operation requires the Start condition, control byte, acknowledge, command code, acknowledge, data byte, acknowledge and Stop (or Restart) condition. The control (slave address) byte requires the R/W bit equal to a logic zero (R/W = 0) to generate a write sequence. The MCP47DA1 is responsible for generating the Acknowledge (A) bits. Data is written to the MCP47DA1 after every byte transfer (during the A bit). If a Stop or Restart condition is generated during a data transfer (before the A bit), the data will not be written to MCP47DA1. READ OPERATION The read operation requires the Start condition, control byte, acknowledge, command code, acknowledge, Restart condition, control byte, acknowledge, data byte, the master generating the A and Stop (or Restart) condition. The first control byte requires the R/W bit equal to a logic zero (R/W = 0) to write the command code, while the second control byte requires the R/W bit equal to a logic one (R/W = 1) to generate a read sequence. The MCP47DA1 will A the slave address byte and A all the data bytes. The I2C master will A the slave address byte and the last data byte. If there are multiple data bytes, the I2C master will A all data bytes except the last data byte (which it will A). The MCP47DA1 maintains control of the SDA signal until all data bits have been clocked out. The command is terminated once a Stop (P) or Restart (S) condition occurs. Refer to Figure 5-14 for the read command sequence. For a single read, the master sends a Stop or Restart condition after the first data byte (and A bit) is sent from the slave. The MSb of each data byte is always a ‘0’, since the wiper register is only 7-bits wide. Figure 5-15 shows the I2C read communication behavior of the master device and the MCP47DA1 device and the resultant I2C bus values. Note: A command code with a non-zero value will cause the data not to be read from the wiper register Data bytes may be written after each Acknowledge. The command is terminated once a Stop (P) condition occurs. Refer to Figure 5-11 for the single byte write sequence and Figure 5-12 for the generic (multi-byte) write sequence. For a single byte write, the master sends a Stop or Restart condition after the first data byte is sent. The MSb of each data byte is a “Don’t Care”, since the wiper register is only 7-bits wide. The command is terminated once a Stop (P) or Restart (S) condition occurs. Figure 5-13 shows the I2C write communication behavior of the master device and the MCP47DA1 device and the resultant I2C bus values. Note: A command code with a non-zero value will cause the data not to be written to the wiper register 2012-2013 Microchip Technology Inc. DS25118D-page 37 MCP47DA1 Fixed Address S 0 1 0 1 1 Read/Write bit (“0” = Write) 1 0 0 A 0 0 0 0 0 0 0 0 Stop bit A X D6 D5 D4 D3 D2 D1 D0 A P Command Code Slave Address Byte Data Byte Legend S = Start Condition P = Stop Condition A = Acknowledge X = Don’t Care R/W = Read/Write bit D6:D0 = Data bits FIGURE 5-11: I2C Single Byte Write Command Format. Fixed Address S 0 1 0 1 1 Read/Write bit (“0” = Write) 1 1 0 A Slave Address Byte 0 0 0 0 0 0 0 0 Command Code A X D6 D5 D4 D3 D2 D1 D0 A Data Byte Stop bit X D6 D5 D4 D3 D2 D1 D0 A X D6 D5 D4 D3 D2 D1 D0 A P Data Byte Data Byte Legend S = Start Condition P = Stop Condition A = Acknowledge X = Don’t Care R/W = Read/Write bit D6:D0 = Data bits FIGURE 5-12: DS25118D-page 38 I2C Write Command Format. 2012-2013 Microchip Technology Inc. MCP47DA1 Write 1 Byte with Command Code = 00h S Slave Address Master R A / C W K Command Code A C K P S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 d d d d d d d 1 P MCP47DA1 I2C™ Bus A C K Data Byte 0 0 0 S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 d d d d d d d 0 P Write 2 Byte with Command Code = 00h S Slave Address Master A C K Data Byte 0 0 0 S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 d d d d d d d 0 Data Byte Master A C K P 0 d d d d d d d 1 P MCP47DA1 0 I2C Bus FIGURE 5-13: A C K S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 d d d d d d d 1 MCP47DA1 I2C Bus R A / C W K Command Code 0 d d d d d d d 0 P I2C Write Communication Behavior. 2012-2013 Microchip Technology Inc. DS25118D-page 39 MCP47DA1 Read/Write bit (0 = Write) S 0 1 0 1 1 1 0 0 A 0 0 0 0 0 0 0 0 A Command Code Slave Address Byte Stop bit Read/Write bit (1 = Read) S 0 1 0 1 1 1 0 1 A 0 D6 D5 D4 D3 D2 D1 D0 A(2) P Slave Address Byte Legend S = Start Condition P = Stop Condition A = Acknowledge X = Don’t Care R/W = Read/Write bit D6:D0 = Data bits Data Byte Note 1: Master device is responsible for ACK/NACK signal. If a NACK signal occurs, the MCP47DA1 will abort this transfer and release the bus. 2: The Master device will Not ACK, and the MCP47DA1 will release the bus so the master device can generate a Stop or Repeated Start condition. FIGURE 5-14: I2C Read Command Format. Read 1 Byte with Command Code = 00h S Slave Address Master R A / C W K Command Code R A / C WK S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 S 0 1 0 1 1 1 0 1 1 MCP47DA1 I2C™ Bus A C R K S Slave Address 0 0 0 S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 S 0 1 0 1 1 1 0 1 0 Data Byte Master A C K P 1 P MCP47DA1 0 d d d d d d d 1 I2C Bus 0 d d d d d d d 1 P Read 2 Byte with Command Code = 00h S Slave Address Master MCP47DA1 I2C Bus R A / C W K Command Code A C R K S Slave Address R A / C WK S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 S 0 1 0 1 1 1 0 1 1 0 0 0 S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 S 0 1 0 1 1 1 0 1 0 Data Byte Master A C K Data Byte A C K P 0 1 P MCP47DA1 0 d d d d d d d 1 0 d d d d d d d 1 I2C Bus 0 d d d d d d d 0 0 d d d d d d d 1 P FIGURE 5-15: DS25118D-page 40 I2C Read Communication Behavior. 2012-2013 Microchip Technology Inc. MCP47DA1 6.0 RESISTOR NETWORK The Resistor Network is made up of an R1 resistor, an RAB resistor ladder, and an R2 resistor connected together. These three resistors are equal (R1 = RAB = R2) each with a typical resistance of 10k. The R1 resistor is also connected to the external VREF pin while the R2 resistor is also internally connected to ground. Figure 6-1 shows a block diagram for the resistor network and output buffer. The resistance from the VREF pin to ground is referred to as RVREF. The 7-bit I2C data byte (00h-7Fh) is decoded to the 6-bit wiper value (00h-40h). Section 6.4 describes the serial shift buffer to wiper register decoding. 6.1 RVREF Resistance RVREF resistance is the resistance from the VREF pin to ground and is the sum of the R1, RAB, and R2 resistances. Equation 6-1 shows how to calculate RVREF. 6.1.1 VREF PIN CURRENT (IVREF) The current into the VREF pin is dependent on the voltage on the VREF pin (VREF) and the RVREF resistance. The VREF pin’s voltage source current capability should support a resistive load that is the minimum RVREF resistance. EQUATION 6-1: RVREF = CALCULATING RVREF (VREF) (IVREF) VREF is the voltage on the VREF pin. IVREF is the current into the VREF pin. 6.2 R1 and R2 Fixed Resistors The R1 and R2 resistors are implemented so that based on temperature and process variations, these resistors track the RAB resistor ladder. The typical R1 and R2 resistances are 10k . 6.3 RAB Resistor Ladder The RAB resistor ladder is a digital potentiometer in a voltage divider configuration. The RAB resistor ladder has 64 RS resistors in series. This resistor ladder has 65 wiper taps which allow wiper connectivity to the bottom (terminal B), Zero Scale, and the top (terminal A), Full Scale, of the resistor ladder (see Figure 6-1). With an even number of RS resistors in the RAB ladder, when the wiper is at the mid-scale value, VOUT equals VREF/2. The RAB resistance also includes the RFS and RZS resistances (see Section 6.3.2). The RAB (and RS) resistance has small variations over voltage and temperature. The typical RAB resistance is 10k. 6.3.1 THE WIPER The value in the volatile wiper register selects which analog switch to close, connecting the W terminal to the selected node of the resistor ladder. The wiper register value is derived from the SSR value (see Section 6.4). Any variation of the wiper resistance does not effect the voltage at the W terminal, and therefore the input of the output buffer. 6.3.2 RFS AND RZS RESISTORS The RFS and RZS resistances are artifacts of the RAB resistor implementation. These resistors are included in the block diagram to help better model the actual device operation. Equation 6-2 shows how to estimate the RS, RFS, and RZS resistances, based on the measured voltages of VREF, VFS, and VZS and the measured current IVREF. EQUATION 6-2: RFS = RZS = RS = ESTIMATING RS, RFS, AND RZS ( (VREF - (64 * VS) ) - VFS ) (IVREF) ( VZS - (64 * VS) ) (IVREF) VS IVREF Where: ( VFS - VZS ) VS = 64 VFS is the VOUT voltage when the wiper code is at full scale (SSR = 60h through 7Fh). VZS is the VOUT voltage when the wiper code is at zero scale (SSR = 00h through 20h). 2012-2013 Microchip Technology Inc. DS25118D-page 41 MCP47DA1 VREF R1 (64 * RS) Data value received (I2C™ interface) A RFS N = 64 (40h) RS 64 * RS RAB RVREF RS N = 63 (3Fh) N = 62 (3Eh) RS 60h 7Fh RW (1) 5Fh RW (1) 5Eh RW (1) W RS N=1 (01h) N=0 (00h) R2 (64 * RS) Op Amp 21h RW (1) RW (1) RZS B + 00h 20h Analog MUX - VOUT Output Buffer (Section 7.0) Wiper Value Resistor Network (Section 6.0) Note 1: The wiper resistance is tap dependent. That is, each tap selection resistance has a small variation. FIGURE 6-1: DS25118D-page 42 Resistor Network and Output Buffer Block Diagram. 2012-2013 Microchip Technology Inc. MCP47DA1 6.4 Serial Buffer to Wiper Register Decode The I2C’s data byte is 8-bits, where only the lower 7-bits are implemented. This register is called the Serial Shift Register (SSR). The wiper register supports addressing of 65 taps (6-bit resolution). This 6-bit resolution is centered about the 7-bit range (where 40h is midscale). So, SSR values 20h and below are zero-scale values, and SSR values 60h and above are full-scale values. Table 6-1 shows the decoding of the serial shift register to the wiper register value. Note 1: The I2C Write and Read commands access the value in the Serial Shift Register (SSR). 2: The MSb of the I2C data byte is ignored and not loaded into the SSR. A write of C0h, will result in the same VOUT voltage as a write of 40h (mid-scale). A subsequent Read command (of the SSR) will result in a value of 40h. 3: The 7-bit SSR value is decoded to a 6-bit (65 taps) value that controls the wiper’s position. TABLE 6-1: SERIAL SHIFT REGISTER VALUE TO WIPER VALUE Wiper I2C™ Write Comment SSR(1) Data Value(2) 00h - 20h or 80h - A0h 00h 20h 00h Wiper register at Zero Scale, VOUT = (1/3) * VREF 21h or A1h 21h 01h Wiper register = SSR - 20h 22h or A2h 22h 02h Wiper register = SSR - 20h : : : 40h or C0h 40h 20h Mid-Scale (POR value), VOUT = (1/2) * VREF : : : 5Eh or DEh 5Eh 3Eh Wiper register = SSR - 20h 5Fh or DFh 5Fh 3Fh Wiper register = SSR - 20h 60h - 7Fh or 60h 40h Wiper register at E0h - FFh 7Fh Full Scale, VOUT = (2/3) * VREF Note 1: The Serial Shift Register (SSR) is 7-bits wide and holds the value written from the I2C Write command. An I2C Read command will read the value in this register. 6.5 Resistor Variations (Voltage and Temperature) The R1, RAB, and R2 resistors are implemented to have minimal variations (by design). Any variations should occur uniformly on all the resistor elements, so the resistor’s elements will track each other over temperature and process variations. The variation of the resistive elements over the operating voltage range is also minimal. Therefore the VREF resistance (RVREF) of the device has minimal variation due to operating voltage. Since the VOUT pin’s voltage is ratiometric, the resistive elements change uniformly over temperature, process, and operating voltage variations. Minimal variation should be seen on the VOUT pin’s voltage. 6.6 POR Value A POR/BOR event will load the volatile serial shift register (and therefore wiper register) with the default value. Table 6-2 shows the default values offered. TABLE 6-2: POR/BOR SETTINGS Device Setting MCP47DA1 Mid-scale Register Value (1) SSR Wiper 40h 20h Note 1: Custom POR/BOR wiper setting options are available; contact the local Microchip Sales Office for additional information. Custom options have NRE and minimum volume requirements. 2: The wiper value is the value that controls the resistor ladder’s wiper position. 2012-2013 Microchip Technology Inc. DS25118D-page 43 MCP47DA1 NOTES: DS25118D-page 44 2012-2013 Microchip Technology Inc. MCP47DA1 7.0 OUTPUT BUFFER As the device powers up, the VOUT pin will float to an unknown value. When the device’s VDD is above the transistor threshold voltage of the device, the output will start being pulled low. After the VDD is above the POR/BOR trip point (VBOR/VPOR), the resistor network’s wiper will be loaded with the POR value (40h, which is mid-scale). The input voltage to the buffer will be the VREF/2. The output voltage of the buffer (VOUT) may not be within specification until the device VDD is at the minimum operating voltage (2.7V). The outputs’ slew rate and settling time must also be taken into account. 7.1 Output Buffer/VOUT Operation The DAC output is buffered with a low power and precision output amplifier (op amp). This amplifier provides a rail-to-rail output with low offset voltage and low noise. The amplifier’s output can drive the resistive and capacitive loads without oscillation. The amplifier provides a maximum load current which is enough for most programmable voltage reference applications. Figure 7-1 shows a block diagram. Note 1: The load resistance must stay higher than 5 k for the stable and expected analog output (to meet electrical specifications). Refer to: • • Section 1.0 “Electrical Characteristics” for the specifications of the output amplifier. Section 7.3 “Driving Resistive and Capacitive Loads” for additional design information. 2: The output amplifier’s input is not rail-torail, and requires a 1.0V delta to the VDD voltage to ensure output linearity. This is not an issue for most voltages, since the maximum voltage on the amplifier input is the Full-Scale voltage (VFS). VFS = 2/3 * VREF. But when the VDD (= VREF) voltage is lower than 3.0V, the delta voltage is less than 1.0V and the amplifier will not be in the linear region for the codes near the full-scale value. For device VDD voltages 3.0V, the VREF pin can be tied to VDD. For VDD voltages < 3.0V, the maximum VREF voltage is: (VDD - 1.0V) / (2/3) Gain =1x VW FIGURE 7-1: Diagram. 7.1.1 Op Amp VOUT Output Buffer Block OUTPUT VOLTAGE The volatile DAC register’s value controls the analog VOUT voltage. The volatile wiper register’s value is unsigned binary. The formula for the output voltage is given in Equation 7-1. EQUATION 7-1: CALCULATING OUTPUT VOLTAGE (VOUT) VOUT = VZS + (N * VS) When RFS = RZS = 0 : VZS = VREF 3 VZS is the VOUT voltage when the wiper code = 00h. N = wiper code = 0 to 64; The serial shift register’s value will be latched on the falling edge of the acknowledge pulse of the Write command’s last byte. Then the VOUT voltage will start driving to the new value. The following events update the analog voltage output (VOUT): • Power-On-Reset. • Falling edge of the acknowledge pulse of the last Write command byte. 7.1.2 STEP VOLTAGE (VS) The Step voltage is dependent on the device resolution (64 RS) and the output voltage range (VZS to VFS). Equation 7-2 shows the calculation for the step resistance. EQUATION 7-2: VS = VS CALCULATION (VFS - VZS) 64 VFS is the VOUT voltage when the wiper code is at full scale (SSR = 60h through 7Fh). VZS is the VOUT voltage when the wiper code is at zero scale (SSR = 00h through 20h). Table 7-1 shows the calculated VOUT voltages for the given volatile wiper register value. These calculations are based on different VREF voltage values (1.5V, 3.3V, and 5.0V) with an assumption that RFS = RZS = 0. 2012-2013 Microchip Technology Inc. DS25118D-page 45 MCP47DA1 Hex 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Note Dec SSR Value Wiper Value (Note 1) 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh VOUT (2) VREF Ratio 1.5 3.3 5.0 0.5000 0.0578 0.5156 0.5234 0.5313 0.5391 0.5469 0.5547 0.5625 0.5703 0.5781 0.5859 0.5938 0.6016 0.6094 0.6172 0.6250 0.6328 0.6406 0.6484 0.6563 0.6641 0.6719 0.6797 0.6875 0.6953 0.7031 0.7109 0.7188 0.7266 0.7344 0.7422 1.1000 1.1172 1.1344 1.1516 1.1688 1.1859 1.2031 1.2203 1.2375 1.2547 1.2719 1.2891 1.3063 1.3234 1.3406 1.3578 1.3750 1.3922 1.4094 1.4266 1.4438 1.4609 1.4781 1.4953 1.5125 1.5297 1.5469 1.5641 1.5813 1.5984 1.6156 1.6328 1.6667 1.6927 1.7188 1.7448 1.1771 1.7969 1.8229 1.8490 1.8750 1.9010 1.9271 1.9531 1.9792 2.0052 2.0313 2.0573 2.0833 2.1094 2.1354 2.1615 2.1875 2.2135 2.2396 2.2656 2.2917 2.3177 2.3438 2.3698 2.3958 2.4219 2.4479 2.4740 Hex Dec VOUT (2) VREF Ratio 1.5 3.3 20h 32 40h 0.5000 0.7500 1.6500 0 1 21h 33 41h 0.5052 0.7578 1.6672 2 22h 34 42h 0.5104 0.7656 1.6844 23h 35 43h 0.5156 0.7734 1.7016 3 4 24h 36 44h 0.5208 0.7813 1.7188 5 25h 37 45h 0.5260 0.7891 1.7359 26h 38 46h 0.5313 0.7969 1.7531 6 7 27h 39 47h 0.5365 0.8047 1.7703 8 28h 40 48h 0.5417 0.8125 1.7875 29h 41 49h 0.5469 0.8203 1.8047 9 10 2Ah 42 4Ah 0.5521 0.8281 1.8219 11 2Bh 43 4Bh 0.5573 0.8359 1.8391 12 2Ch 44 4Ch 0.5625 0.8438 1.8563 13 2Dh 45 4Dh 0.5677 0.8516 1.8734 14 2Eh 46 4Eh 0.5729 0.8594 1.8906 15 2Fh 47 4Fh 0.5781 0.8672 1.9078 16 30h 48 50h 0.5833 0.8750 1.9250 17 31h 49 51h 0.5885 0.8828 1.9422 18 32h 50 52h 0.5938 0.8906 1.9594 19 33h 51 53h 0.5990 0.8984 1.9766 20 34h 52 54h 0.6042 0.9063 1.9938 21 35h 53 55h 0.6094 0.9141 2.0109 22 36h 54 56h 0.6146 0.9219 2.0281 23 37h 55 57h 0.6198 0.9297 2.0453 24 38h 56 58h 0.6250 0.9375 2.0625 25 39h 57 59h 0.6302 0.9453 2.0797 26 3Ah 58 5Ah 0.6354 0.9531 2.0969 27 3Bh 59 5Bh 0.6406 0.9609 2.1141 28 3Ch 60 5Ch 0.6458 0.9688 2.1313 29 3Dh 61 5Dh 0.6510 0.9766 2.1484 3Eh 62 5Eh 0.6563 0.9844 2.1656 30 31 3Fh 63 5Fh 0.6616 0.9922 2.1828 40h 64 60h 0.6667 1.0000 2.2000 1: The I2C 7-bit write data value (serial shift register) will be offset by -20h, That is I2C 7-bit write value = 20h, wiper code = 00h. See Section 6.4 for additional information. 2: VOUT voltages based on RFS and RZS = 0 . DS25118D-page 46 0.3333 0.3385 0.3438 0.3490 0.3542 0.3594 0.3646 0.3698 0.3750 0.3802 0.3854 0.3906 0.3958 0.4010 0.4063 0.4115 0.4167 0.4219 0.4271 0.4323 0.4375 0.4427 0.4479 0.4531 0.4583 0.4635 04688 0.4740 0.4792 0.4844 0.4896 0.4948 Wiper Value (Note 1) SSR Value THEORETICAL DAC OUTPUT VALUES (WIPER VALUE = I2C WRITE DATA - 20H) TABLE 7-1: 5.0 2.5000 2.5260 2.5521 2.5781 2.6042 2.6302 2.6563 2.6823 2.7083 2.7344 2.7604 2.7865 2.8125 2.8385 2.8646 2.8906 2.9167 2.9427 2.9688 2.9948 3.0208 3.0469 3.0729 3.0990 3.1250 3.1510 3.1771 3.2031 3.2292 3.2552 3.2813 3.3073 3.3333 2012-2013 Microchip Technology Inc. MCP47DA1 7.1.3 AMPLIFIER INPUT VOLTAGE (VW) The input voltage into the Output Amplifier has requirements to ensure the input is in the linear range of the amplifier. To ensure that the amplifier is operating in its linear range, the amplifier’s input voltage (VW) has some requirements that must be met. For device VDD voltages 3.0V, the amplifier is in the linear region for all VREF voltages ( 1.0V) and DAC register codes. For device VDD voltages < 3.0V, then the interaction between the device VDD and the amplifier input voltage (VW) need to be taken into account. The VW voltage is dependent on the VREF voltage and the DAC register code. Here is the amplifier requirement that must be met: VW (VDD - 1.0V) / (2/3) The VREF pin voltage and the maximum DAC register code can be optimized between the maximum DAC register code desired and the VREF pin voltage. So when the VREF voltage < VDD voltage < 3.0V, then the DAC register code can be some value greater than the code shown in Table 7-3. Figure 7-2 shows the equations for solving for VOUT voltage, the VREF voltage, or the maximum DAC register code, based on knowing the requirements for two of these variables. The DAC register code of 64 is the full-scale code, and any number greater than 64 is invalid. VOUT = VREF = 2 * VREF 3 Table 7-2 shows the maximum VREF voltage (for VDD < 3.0V) if the DAC output (VOUT) will operate over the full range of DAC register codes. TABLE 7-2: VDD Comment VREF pin can be tied to VDD pin 3.0 3.00 2.55 2.5 2.25 2.2 1.80 2.0 1.50 1.8 1.20 64 DAC Code 64 DAC Code = 64 * +1 3 * VOUT 2 * VREF FIGURE 7-2: Solving for VOUT, VREF, or DAC Register Code. VREF VDD AND FULL-SCALE OUTPUT VREF 2.7 DAC Code 3 * VOUT If VREF = VDD and VOUT will have full-scale output, then: VREF (VDD - 1.0V) / (2/3) * Table 7-3 shows the maximum DAC register code when the VREF pin is tied to the VDD voltage (for VDD < 3.0V). For DAC register codes above this, the VOUT linearity may be degraded (out of specification). TABLE 7-3: VREF = VDD AND NOT FULL-SCALE OUTPUT Max DAC Register Comment Code VDD = VREF VW 3.0 3.00 60h-FFh 2.7 2.55 58h 2.5 2.25 53h 2.2 1.80 48h 2.0 1.50 40h 1.8 1.20 35h This is Full Scale 2012-2013 Microchip Technology Inc. DS25118D-page 47 MCP47DA1 7.2 Output Slew Rate Figure 7-3 shows an example of the slew rate of the VOUT pin. The slew rate can be affected by the characteristics of the circuit connected to the VOUT pin. VOUT(B) Wiper = A Wiper = B Time Slew Rate = | VOUT(B) - VOUT(A) | FIGURE 7-3: 7.2.1 T VOUT pin Slew Rate. SMALL CAPACITIVE LOAD With a small capacitive load, the output buffer’s current is not affected by the capacitive load (CL). But still, the VOUT pin’s voltage is not a step transition from one output value (wiper code value) to the next output value. The change of the VOUT voltage is limited by the output buffer’s characteristics, so the VOUT pin voltage will have a slope from the old voltage to the new voltage. This slope is fixed for the output buffer, and is referred to as the buffer slew rate (SRBUF). 7.2.2 Driving Resistive and Capacitive Loads The VOUT pin can drive up to 100 pF of capacitive load in parallel with a 5 k resistive load (to meet electrical specifications). Figure 2-84 shows the VOUT vs. Resistive Load. VOUT drops slowly as the load resistance decreases after about 3.5 k . It is recommended to use a load with RL greater than 5 k. VOUT VOUT(A) 7.3 LARGE CAPACITIVE LOAD With a larger capacitive load, the slew rate is determined by two factors: • The output buffer’s short circuit current (ISC) • The VOUT pin’s external load IOUT cannot exceed the output buffer’s short circuit current (ISC), which fixes the output buffer slew rate (SRBUF). The voltage on the capacitive load (CL), VCL, changes at a rate proportional to IOUT, which fixes a capacitive load slew rate (SRCL). So the VCL voltage slew rate is limited to the slower of the output buffer’s internally set slew rate (SRBUF) and the capacitive load slew rate (SRCL). Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response with overshoot and ringing in the step response. That is, since the VOUT pin’s voltage does not quickly follow the buffer’s input voltage (due to the large capacitive load), the output buffer will overshoot the desired target voltage. Once the driver detects this overshoot, it compensates by forcing it to a voltage below the target. This causes voltage ringing on the VOUT pin. So, when driving large capacitive loads with the output buffer, a small series resistor (RISO) at the output (see Figure 7-4) improves the output buffer’s stability (feedback loop’s phase margin) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. VW VOUT VCL RISO RL CL FIGURE 7-4: Circuit to Stabilize Output Buffer for Large Capacitive Loads (CL). The RISO resistor value for your circuit needs to be selected. The resulting frequency response peaking and step response overshoot for this RISO resistor value should be verified on the bench. Modify the RISO’s resistance value until the output characteristics meet your requirements. A method to evaluate the system’s performance is to inject a step voltage on the VREF pin and observe the VOUT pin’s characteristics. Note: DS25118D-page 48 Op Amp Additional insight into circuit design for driving capacitive loads can be found in AN884, “Driving Capacitive Loads With Op Amps” (DS00884). 2012-2013 Microchip Technology Inc. MCP47DA1 7.4 Output Errors TABLE 7-4: The output error is caused by two factors. These are: CALCULATION COMPARISON Example Theoretical Delta 30,180 — RVREF • Characteristics of the Resistor Network • Characteristics of the Output Buffer Figure 7-5 shows the components of the error on the output voltage. The first part of the error is from the resistor ladder and the RFS and RZS resistances. The second part is due to the output buffer’s input offset characteristics. The RFS and RZS resistances effect the voltage between VZS and VFS. The larger that RFS + RZS is, the smaller that the step voltage (VS) will be (from the theoretical step voltage). The increase in the RFS and RZS resistances also effects the Full-Scale Error (FSE), Zero-Scale Error (ZSE), and gain error. Table 7-4 compares theoretical resistor network voltages for full scale and zero scale, where RFS = RZS = 0, to an example where RFS and RZS and non-zero. The voltage calculations show cases of VREF = 5.0V and VREF = 1.5V. Figure 2-89 shows RVREF, RFS, and RZS resistances VDD. RFS 100 0 100 RZS 80 0 80 R1 + 64*RS + R2 30,000 30,180 - 180 R1, RAB, R2 10,000 10,060 - 60 VREF 5.00 V — VFS 3.3267 V 3.3333 V - 6.6 mV VZS 1.6700 V 1.6667 V + 3.3 mV VS 25.88 mV 26.04 mV - 0.16 mV VREF 1.5V 0.9980 V VFS — 1.0000 V - 2.0 mV VZS 0.5010 V 0.5000 V + 1.0 mV VS 7.766 mV 7.813 mV - 0.047mV Note 1: RVREF = R1 + RAB + R2 , RAB = RFS + 64*RS + RZS. VS = (VFS - VZS) / 64 So, as the voltage reference (VREF) decreases, the Step voltages (VS) decrease. At a low VREF voltage, the step voltage approaches the magnitude of the output buffer’s input offset voltage (design target of ± 4.5 mV). So, for low VREF voltages, the output buffer errors have greater influence on the VOUT voltage. R1 = 64*RS VREF Theoretical VFS ( (2/3) * VREF ) ( RFS 0 ) VFS-RL should be less than VDD - 1.0V (due to buffer input not being rail-to-rail, not meeting this requirement would only effect VOUT linearity at upper codes) RAB = 64*RS VOUT(FS) VFS-RL (Due to RFS 0) Variations due to Output Buffer’s Input Offset voltage and Buffer ‘s Impedance/Load. VZS-RL (Due to RZS 0) R2 = 64*RS VOUT(ZS) * VREF VS = VREF / 192 Theoretical VZS ( (1/3) * VREF ) ( RZS 0 ) VSS 64 When: RFS = RZS = 0 . VREF VS FIGURE 7-5: (VFS - VZS) Step Voltage (VS) = 5.0V 2.7V 1.8V 1.5V 1.0V 26.0mV 14.1mV 9.4mV 7.8mV 5.2mV when RFS = RZS = 0 . Output Voltage (VOUT) Error. 2012-2013 Microchip Technology Inc. DS25118D-page 49 MCP47DA1 NOTES: DS25118D-page 50 2012-2013 Microchip Technology Inc. MCP47DA1 8.0 APPLICATIONS EXAMPLES The MCP47DA1 family of devices are general purpose, single-channel voltage output DACs for various applications where a precision operation with low power is needed. The MCP47DA1 devices are rail-to-rail output DACs designed to operate with a VDD range of 2.7V to 5.5V. The internal output op amplifier is robust enough to drive common, small-signal loads directly, thus eliminating the cost and size of external buffers for most applications. Applications generally suited for the devices are: • • • • Set Point or Offset Trimming Sensor Calibration Portable Instrumentation (Battery Powered) Motor Control Application examples include: • • • • DC Set Point or Calibration Decreasing Output Step Size Building a “Window” DAC Selectable Gain and Offset Bipolar Voltage Output • Building Programmable Current Source • Serial Interface Communication Times • Software I2C Interface Reset Sequence In the design of a system with MCP47DA1 devices, the following considerations should be taken into account: • Power Supply Considerations (Noise) • PCB Area Requirements • Connecting to I2C BUS using Pull-Up Resistors 8.1 DC Set Point or Calibration A common application for the devices is a digitally-controlled set point and/or calibration of variable parameters, such as sensor offset or slope. For example, the MCP47DA1 provides 64 output steps over 1/3 of the voltage reference range. If voltage reference is 1.65V, the LSb size is 1.65V / 192, or ~ 8.6 mV. Applications that need accurate detection of an input threshold event often need several sources of error eliminated. Use of comparators and operational amplifiers (op amps) with low offset and gain error can help achieve the desired accuracy, but in many applications, the input source variation is beyond the designer’s control. If the entire system can be calibrated after assembly in a controlled environment (like factory test), these sources of error are minimized if not entirely eliminated. Figure 8-1 illustrates this example circuit. Equation 8-1 shows a quick estimation of the wiper value given the desired voltage trip (VTRIP) point. VREF VDD VCC+ VSENSE MCP47DA1 Comp. VTRIP C1 VOUT VO VCC– I2C™ 2-wire FIGURE 8-1: Calibration. Set Point or Threshold EQUATION 8-1: ESTIMATING THE WIPER VALUE (N) FROM THE DESIRED VTRIP VTRIP = VOUT = (1/3) * VREF + (N * VS) N = ( VTRIP - ( (1/3) * VREF ) ) VS Where: VS = VREF / 192 Note: 2012-2013 Microchip Technology Inc. Calculation does not take into account RFS and RZS resistors of the DAC’s resistor ladder (see Section 7.1 for DS25118D-page 51 MCP47DA1 8.1.1 DECREASING OUTPUT STEP SIZE Due to the step voltage and output range of the MCP47DA1, it may be desirable to reduce the step voltage while also modifying the range of the output. A common method to achieve this smaller step size is a voltage divider on the DAC’s output. This allows the VTRIP voltage to be lower than the minimum output voltage of the DAC (1/3 * VREF). Figure 8-2 illustrates this concept. Equation 8-2 shows a quick estimation of the wiper value given the desired voltage trip (VTRIP) point. So, for example, if R1 = R2, then the VTRIP voltage range is from 1/6 * VREF to 1/3 * VREF, where the VOUT voltage range is from 1/3 * VREF to 2/3 * VREF. Also at the VTRIP node, the step voltage is 1/2 the step voltage at the VOUT node. A bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the DAC and the induced noise from the environment. VREF VDD MCP47DA1 VCC+ R1 VSENSE VOUT R2 I2C™ Comp. VTRIP C1 BUILDING A “WINDOW” DAC When calibrating a set point or threshold of a sensor, typically only a small portion of the DAC output range is utilized. If the LSb size is adequate enough to meet the application’s accuracy needs, the unused range is sacrificed without consequences. If greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. If the threshold is not near VREF, 2 • VREF, or VSS then creating a “window” around the threshold has several advantages. One simple method to create this “window” is to use a voltage divider network with a pull-up and pull-down resistor. Figure 8-3 and Figure 8-4 illustrate this concept. VREF VDD MCP47DA1 VO VCC– 2-wire FIGURE 8-2: Example Circuit Of Set Point or Threshold Calibration. EQUATION 8-2: 8.1.2 VOUT AND VTRIP ESTIMATIONS VOUT = (1/3) * VREF + (N * VS) VS = VREF / 192 R1 VOUT DS25118D-page 52 R3 VTRIP Comp. C1 VO VCC– VCC– FIGURE 8-3: DAC. Single-Supply “Window” EQUATION 8-3: VOUT AND VTRIP ESTIMATIONS VOUT = (1/3) * VREF + (N * VS) VS = VREF / 192 VOUT * R23 + V23 * R1 R1 + R23 VTRIP = Thevenin Equivalent The VOUT voltage can also be scaled by a resistor from the VREF pin to the system reference voltage. Care should be taken with this implementation due to the ± 20% variation to the 30k typical resistance from the VREF pin to ground (RVREF). This variation in resistance directly effects the actual VOUT voltage. VCC+ R2 I2C™ 2-wire R2 VTRIP = VOUT * R + R 1 2 Note: VCC+ RSENSE VOUT R23 = R2 * R3 R2 + R3 V23 = (VCC+ * R2) * (VCC- * R3) R2 + R3 R1 VTRIP R23 V23 2012-2013 Microchip Technology Inc. MCP47DA1 8.2 Selectable Gain and Offset Bipolar Voltage Output In some applications, control of the output range is desirable. Figure 8-4 shows a circuit using a DAC device to achieve a bipolar or single-supply application. This circuit is typically used for linearizing a sensor whose slope and offset varies. Depending on the output range desired, resistor R4 or resistor R5 may not be required. Equation 8-4 shows the calculation of the gain, while Equation 8-5 shows the calculation of the VO voltage. This circuit can be simplified if the window range is limited (by removing either the R4 or R5 resistor). Figure 8-5 shows a circuit for the case where the R5 resistor is removed. Resistors R1 and R2 control the gain, while resistors R3 and R4 shift the DAC’s output to a selected offset. Equation 8-6 shows the calculation of the VO voltage. Note: R4 can be tied to VDD, instead of VSS, if a higher offset is desired. EQUATION 8-4: Gain = MCP47DA1 R5 VOUT R4 I2C™ 2-wire R1 EQUATION 8-5: BIPOLAR “WINDOW” DAC CALCULATIONS VCC+ VOA+ VO VCC– VCC– R2 R1 Offset Adjust VOA+ = V45 = VS = VREF VDD R4 Gain Adjust (VCC+ • R4) + (VCC- • R5) R4 + R5 R4 • R5 R4 + R5 (1) VREF 192 VO C1 VCC– I2C™ 2-wire R2 VIN SIMPLIFIED BIPOLAR “WINDOW” DAC CALCULATIONS VO = VOA+ • ( 1 + VOA+ = VOUT • ( VCC+ VOA+ ) R3 + R45 EQUATION 8-6: FIGURE 8-4: Bipolar Voltage Source with Selectable Gain and Offset Circuit. VOUT R1 (VOUT • R45) + (V45 • R3) Note: Capacitor C1 is recommended (0.1uF typical) R3 R1 R2 ) - VIN • ( Note 1: VOUT calculation does not take into account RFS and RZS resistors of the DAC’s resistor ladder (see Section 7.1 for additional information). C1 VIN MCP47DA1 R2 VO = VOA+ • ( 1 + VOUT = (1/3) * VREF + (N * VS) VCC+ R3 R2 If desired Gain = 0.5, and R1 is selected as 20 k then R2 would need to be 10 k . R45 = VREF VDD GAIN CALCULATION R2 R1 ) - VIN • ( R4 R3 + R4 R2 R1 ) ) VOUT = (1/3) * VREF + (N * VS) Note 1: VOUT calculation does not take into account RFS and RZS resistors of the DAC’s resistor ladder (see Section 7.1 for additional information). R1 Note: Capacitor C1 is recommended (0.1uF typical) FIGURE 8-5: Simplified Bipolar Voltage Source with Selectable Gain and Offset Circuit. 2012-2013 Microchip Technology Inc. DS25118D-page 53 MCP47DA1 8.3 Building Programmable Current Source 8.4 Figure 8-6 shows an example of building a programmable current source using a voltage follower. The current sensor resistor is used to convert the DAC voltage output into a digitally-selectable current source. The smaller RSENSE is, the less power is dissipated across it. However, this also reduces the resolution that the current can be controlled. VDD (or VREF) VREF VDD Table 8-1 shows the time for each I2C Serial Interface command as well as the effective data update rate that can be supported by the digital interface (based on the two I2C serial interface frequencies). The continuous Write command allows a higher data update frequency, since for the fixed overhead, more bytes are transferred. So, the serial interface performance along with the VOUT output performance (such as slew rate), is used to determine the application’s volatile DAC register update rate. Load VCC+ VOUT MCP47DA1 Serial Interface Communication Times IL Ib VCC– I2C™ 2-wire IL I b = ---- RSENSE V OUT I L = --------------- ------------R sense + 1 where Common-Emitter Current Gain FIGURE 8-6: Source. TABLE 8-1: Digitally-Controlled Current SERIAL INTERFACE TIMES / FREQUENCIES Command Time (µs) Example Command Write Single byte Write Continuous bytes Read byte Note 1: 2: # of Serial # Bytes # of Serial Interface bits(1) Transferred Interface bits Effective Data Update Frequency (kHz) (2) 100 kHz 400 kHz 100 kHz 400 kHz 29 1 29 290.0 72.5 3.4 13.8 20 + N * 9 5 65 650.0 162.5 7.7 30.8 39 1 39 390.0 97.5 2.6 10.3 Includes the Start or Stop bits. This is the command frequency multiplied by the number of bytes transferred. DS25118D-page 54 2012-2013 Microchip Technology Inc. MCP47DA1 Software I2C Interface Reset Sequence 8.5 Note: This technique should be supported by any I2C compliant device. The 24XXXX I2C Serial EEPROM devices support this technique, which is documented in AN1028. At times, it may become necessary to perform a Software Reset Sequence to ensure the MCP47DA1 device is in a correct and known I2C Interface state. This technique only resets the I2C state machine. This is useful if the MCP47DA1 device powers up in an incorrect state (due to excessive bus noise, etc), or if the master device is reset during communication. Figure 8-7 shows the communication sequence to software reset the device. S ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Start bit FIGURE 8-7: Format. S P Nine bits of ‘1’ Start bit Stop bit Software Reset Sequence The first Start bit will cause the device to reset from a state in which it is expecting to receive data from the master device. In this mode, the device is monitoring the data bus in Receive mode and can detect if the Start bit forces an internal Reset. 2012-2013 Microchip Technology Inc. The nine bits of ‘1’ are used to force a Reset of those devices that could not be reset by the previous Start bit. This occurs only if the MCP47DA1 is driving an A bit on the I2C bus, or is in Output mode (from a Read command) and is driving a data bit of ‘0’ onto the I2C bus. In both of these cases, the previous Start bit could not be generated due to the MCP47DA1 holding the bus low. By sending out nine ‘1’ bits, it is ensured that the device will see an A bit (the master device does not drive the I2C bus low to acknowledge the data sent by the MCP47DA1), which also forces the MCP47DA1 to reset. The second Start bit is sent to address the rare possibility of an erroneous write. This could occur if the master device was reset while sending a Write command to the MCP47DA1, AND then as the master device returns to normal operation and issues a Start condition, while the MCP47DA1 is issuing an Acknowledge. In this case, if the second Start bit is not sent (and the Stop bit was sent) the MCP47DA1 could initiate a write cycle. Note: The potential for this erroneous write ONLY occurs if the master device is reset while sending a Write command to the MCP47DA1. The Stop bit terminates the current I2C bus activity. The MCP47DA1 waits to detect the next Start condition. This sequence does not effect any other I2C devices which may be on the bus, as they should disregard this as an invalid command. DS25118D-page 55 MCP47DA1 VDD Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP47DA1’s performance. Careful board layout minimizes these effects and increases the Signal-to-Noise Ratio (SNR). Multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are suggested. Particularly harsh environments may require shielding of critical signals. The device’s power sources (VDD and VREF) should be as clean as possible. Any noise induced on the VDD and VREF signals can affect the DAC performance. Separate digital and analog ground planes are recommended. VREF VOUT FIGURE 8-8: Connections. Note: Breadboards and wire-wrapped boards are not recommended. DS25118D-page 56 SDA VSS Typical Microcontroller Optional Analog C1 C4 C5 VREF Optional Output C2 VDD 1 In this example, the recommended bypass capacitor value is 0.1 µF. This capacitor should be placed as close to the device power pin (VDD) as possible (within 4 mm). Figure 8-9 shows an example of using two bypass capacitors (a 10 µF tantalum capacitor and a 0.1 µF ceramic capacitor) in parallel on the VDD line. These capacitors should be placed as close to the VDD pin as possible (within 4 mm). If the application circuit has separate digital and analog power supplies, the VDD and VSS pins of the device should reside on the analog plane. SCL VSS Typical applications require a bypass capacitor in order to filter high-frequency noise on the VDD and VREF signals. The noise can be induced onto the power supply’s traces or as a result of changes on the DAC output. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-8 illustrates an appropriate bypass strategy. Separate digital and analog ground planes are recommended. In this case, the VSS pin and the ground pins of the VDD capacitors should be terminated to the analog ground plane and VDD and VSS should reside on the analog plane. 0.1 µF 0.1 µF PIC® Microcontroller POWER SUPPLY CONSIDERATIONS (NOISE) VDD MCP47DA1 8.6.1 Design Considerations VSS 2 SCL 3 MCP47DA1 8.6 C3 6 VREF 5 4 VDD VOUT SDA R1 R2 To MCU R1 and R2 are I2C™ pull-up resistors: R1 and R2: 5 k - 10 k for fSCL = 100 kHz to 400 kHz C1: 0.1 µF capacitor Ceramic C2: 10 µF capacitor Tantalum C3: ~ 0.1 µF Optional to reduce noise in VOUT pin. C4: 0.1 µF capacitor Ceramic C5: 10 µF capacitor Tantalum FIGURE 8-9: Circuit. Example MCP47DA1 2012-2013 Microchip Technology Inc. MCP47DA1 8.6.2 PCB AREA REQUIREMENTS 8.6.4 In some applications, PCB area is a criteria for device selection. Table 8-2 shows the typical package dimensions and area for the different package options. PACKAGE FOOTPRINT (1) Package Package Footprint Pins Dimensions (mm) 6 6 Type Code Length Width Area (mm2) TABLE 8-2: SOT-23 OT 3.10 3.20 9.92 SC70 LT 2.0 2.10 4.20 Note 1: Does not include recommended Land Pattern dimensions. Dimensions are max. values. 8.6.3 FOOTPRINT COMPATIBILITY WITH MCP40D18 The MCP47DA1 in the SC70 package is footprint compatible with the MCP40D18 device. The VREF pin is analogous to the A Terminal pin while the VOUT pin is analogous to the W Terminal pin. The VOUT pin is a buffered output so any buffering of the W Terminal pin may be able to be removed. Also, verify the resistor network’s resistance to ensure the voltage source on the VREF pin (A Terminal) can support the current requirements (IVREF vs. the IRAB). CONNECTING TO I2C BUS USING PULL-UP RESISTORS The SCL and SDA pins of the MCP47DA1 devices are open-drain configurations. These pins require a pull-up resistor as shown in Figure 8-9. The pull-up resistor values (R1 and R2) for SCL and SDA pins depend on the operating speed (standard, fast, and high speed) and loading capacitance of the I2C bus line. A higher value of the pull-up resistor consumes less power, but increases the signal transition time (higher RC time constant) on the bus line. Therefore, it can limit the bus operating speed. The lower resistor value, on the other hand, consumes higher power, but allows higher operating speed. If the bus line has higher capacitance due to long metal traces or multiple device connections to the bus line, a smaller pull-up resistor is needed to compensate the long RC time constant. The pull-up resistor is typically chosen between 1 kand 10 kranges for Standard and Fast modes. 8.6.4.1 Device Connection Test The user can test the presence of the device on the I2C bus line using a simple I2C command. This test can be achieved by checking an acknowledge response from the device after sending a Read or Write command. Figure 8-10 shows an example with a Read command. The steps are: a) b) c) Set the R/W bit “High” in the device’s address byte. Check the ACK bit of the address byte. If the device acknowledges (ACK = 0) the command, then the device is connected, otherwise it is not connected. Send Stop bit. Address Byte 1 2 SDA 1 1 0 Start Bit 3 4 5 6 7 8 1 A2 A1 A0 1 9 ACK SCL Stop Bit Device Code Address bits R/W Device Response FIGURE 8-10: 2012-2013 Microchip Technology Inc. I2C Bus Connection Test. DS25118D-page 57 MCP47DA1 NOTES: DS25118D-page 58 2012-2013 Microchip Technology Inc. MCP47DA1 9.0 DEVELOPMENT SUPPORT 9.1 Evaluation/Demonstration Boards Note: Since the SC70EV is a generic board, the noise immunity of the board will not be optimal. If noise immunity is a requirement, then you will need to develop a custom PCB for the MCP47DA1. This PCB would need to use good layout techniques to reduce noise coupling. The MCP47DA1 devices do not have a dedicated Evaluation or Demonstration board. Figure 9-1 shows the component connections to make an evaluation board using the SC70EV Bond Out PCB (order number SC70EV) with the MCP47DA1 in a SOT-23-6 package. This will allow the MCP47DA1’s capabilities to be evaluated with the PICkit™ Serial Analyzer (order number DV164122). 0 VDD 1.0 µF VREF (1) 0.1 µF VOUT 47DA1 VSS 0 4.7 k CL & RL 4.7 k SCL ™ SDA ™ Required components Recommended components for noise filtering Optional I2C™ bus pull-up resistors (value may need to be adjusted for your system). Optional VOUT loading components (stacked), CL = 1 nF max and RL = 5 k max. Note 1: The VREF pin (P8) will need to be connected to a reference voltage source (such as VDD). FIGURE 9-1: SC70EV Bond Out PCB – Top Layer and Silk-Screen. 2012-2013 Microchip Technology Inc. DS25118D-page 59 MCP47DA1 9.2 Technical Documentation Several additional technical documents are available to assist in your design and development. These technical documents include Application Notes, Technical Briefs, and Design Guides. Table 9-1 shows some of these documents. TABLE 9-1: Application Note Number TECHNICAL DOCUMENTATION Title Literature # AN1326 Using the MCP4728 12-Bit DAC for LDMOS Amplifier Bias Control Applications DS01326 — Signal Chain Design Guide DS21825 — Analog Solutions for Automotive Applications Design Guide DS01005 DS25118D-page 60 2012-2013 Microchip Technology Inc. MCP47DA1 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 6-Lead SOT-23 Example: MANN Part Number Code Part Number Code MCP47DA1T-A0E/OT MANN MCP47DA1T-A1E/OT M9NN 6-Lead SC-70 Example AZNN Part Number Code Part Number Code MCP47DA1T-A0E/LT AZNN MCP47DA1T-A1E/LT BBNN Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2012-2013 Microchip Technology Inc. DS25118D-page 61 MCP47DA1 /HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU27>627@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ b 4 N E E1 PIN 1 ID BY LASER MARK 1 2 3 e e1 D A A2 c φ L A1 L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H %6& 2XWVLGH/HDG3LWFK H %6& 2YHUDOO+HLJKW $ ± 0ROGHG3DFNDJH7KLFNQHVV $ ± 6WDQGRII $ ± 2YHUDOO:LGWK ( ± 0ROGHG3DFNDJH:LGWK ( ± 2YHUDOO/HQJWK ' ± )RRW/HQJWK / ± )RRWSULQW / ± )RRW$QJOH ± /HDG7KLFNQHVV F ± /HDG:LGWK E ± 1RWHV 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS25118D-page 62 2012-2013 Microchip Technology Inc. MCP47DA1 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012-2013 Microchip Technology Inc. DS25118D-page 63 MCP47DA1 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25118D-page 64 2012-2013 Microchip Technology Inc. MCP47DA1 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012-2013 Microchip Technology Inc. DS25118D-page 65 MCP47DA1 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25118D-page 66 2012-2013 Microchip Technology Inc. MCP47DA1 APPENDIX A: REVISION HISTORY Revision D (March 2013) The following is the list of modifications: 1. 2. 3. 4. 5. 6. 7. Changed the Typical Static Current value from 90 µA to 100 µA (on pages 1 and 4), and Maximum value from 130uA to 160uA (on page 4). Split the CDM Absolute Maximum Rating into SOT-23 and SC70 packages. Change CDM values. Changed the INL limit from ± 0.5 to ± 0.7. Changed the DNL limit from ± 0.25 to ± 0.35. Added new Figure 2-81. Updated Figure 2-82 and Figure 2-83. Corrected and enhanced Table 8-2. Revision C (July 2012) The following is the list of modifications: 1. 2. 3. 4. 5. 6. 7. 8. Added the SC70 package option (corrected applicable information). Corrected Capacitive Load (CL) for the Characterization graphs. Enhanced description in Figure 7-5. Added Section 8.6.3 “Footprint Compatibility with MCP40D18”. Corrected Typical current number on first page. In Electrical Specifications, clarified Interface Inactive to Interface Inactive (Static). Section 3.1 “Positive Power Supply Input (VDD)”, corrected and clarified pin description. Updated Table 7-1 to include columns for Serial Shift Register (SSR) value. Revision B (March 2012) • General Release of this Document. Revision A (January 2012) • Original Release of this Document. Requires NDA. 2012-2013 Microchip Technology Inc. DS25118D-page 67 MCP47DA1 APPENDIX B: B.1 TERMINOLOGY B.4 Resolution The resolution is the number of DAC output states that divide the full-scale range. For the 6-bit DAC, the resolution is 26, meaning the DAC code ranges from 0 to 64. B.2 Least Significant Bit (LSb) Normally, this is thought of as the ideal voltage difference between two successive codes. This bit has the smallest value or weight of all bits in the register. For a given output voltage range, which is typically the voltage between the full-scale voltage and the zeroscale voltage (VOUT(FS) - VOUT(ZS)), it is divided by the resolution of the device (Equation B-1). EQUATION B-1: LSb VOLTAGE CALCULATION Monotonic Operation Monotonic operation means that the device’s output voltage (VOUT) increases with every one code step (LSb) change (from terminal B to terminal A). The VOUT voltage (VW voltage) is the sum of all the Step voltages plus the voltage at zero scale (VZS). The zero-scale voltage is dependent on the resistance between the tap 0 point and the B Terminal. VS64 0x40 VS63 0x3F Wiper Code 0x3E VS3 0x03 VS1 0x02 VS0 0x01 0x00 VW n=? (@ tap) V = VSn + VZS(@ Tap 0) W n=0 Voltage (VW ~= VOUT) FIGURE B-1: DS25118D-page 68 See Figure 2-23 through characterization graphs. EQUATION B-2: FSE = Figure 2-33 for FSE FULL-SCALE ERROR VOUT(@FS) - VIDEAL(@FS) VLSb Where: FSE is expressed in LSb VOUT(@FS) is the VOUT voltage when the DAC register code is at Full Scale. VIDEAL(@FS) is the ideal output voltage when the DAC register code is at Full Scale. B.5 2N = 64 (MCP47DA1) B.3 The Full-Scale Error (FSE) is the difference between the ideal and measured DAC output voltage with the wiper’s position is set to its maximum (wiper code = 40h); see Figure B-3. Full-scale error may also be thought of as the sum of the offset error plus gain error. VLSb is the delta voltage of one DAC register code step (such as code 20h to code 21h). VOUT(FS) - VOUT(ZS) 2N VLSb = Full-Scale Error (FSE) Zero-Scale Error (ZSE) The Zero-Scale Error (ZSE) is the difference between the ideal and measured VOUT voltage with the wiper position set to its minimum (wiper code = 00h); see Figure B-3. The zero-scale error is the same as the offset error for this case (wiper code = 00h). See Figure 2-34 through characterization graphs. EQUATION B-3: ZSE = Figure 2-44 for ZSE ZERO-SCALE ERROR VOUT(@ZS) VLSb Where: FSE is expressed in LSb VOUT(@ZS) is the VOUT voltage when the DAC register code is at Zero Scale. VLSb is the delta voltage of one DAC register code step (such as code 20h to code 21h). B.6 Total Unadjusted Error The total unadjusted error is the difference between the ideal and measured VOUT voltage. Typically, calibration of the output voltage is implemented to improve system performance. See Figure 2-45 through Figure 2-55 and Figure 2-75 through Figure 2-78 for total unadjusted error characterization graphs. VW (VOUT). 2012-2013 Microchip Technology Inc. MCP47DA1 B.7 Offset Error B.9 The offset error (see Figure B-2) is the deviation from zero voltage output when the volatile DAC register value = 00h (zero-scale voltage). This error affects all codes by the same amount. The offset error can be calibrated by software in application circuits. Actual Transfer Function Analog Output Gain Error The gain error (see Figure B-3) is the difference between the actual full-scale output voltage, from the ideal output voltage of the DAC transfer curve. The gain error is calculated after nullifying the offset error, or full-scale error minus the offset error. The gain error indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The gain error is usually expressed as percent of full-scale range (% of FSR) or in LSb. The gain error is not calibrated at the factory and most of the gain error is contributed by the output buffer (op amp) saturation. Actual Transfer Function Ideal Transfer Function Offset Error (ZSE) Full-Scale Error 0 FIGURE B-2: B.8 DAC Input Code OFFSET ERROR. Offset Error Drift Gain Error Analog Output Actual Transfer Function after Offset Error is removed The offset error drift is the variation in offset error due to a change in ambient temperature. The offset error drift is typically expressed in ppm/°C. Ideal Transfer Function Zero-Scale Error 0 DAC Input Code FIGURE B-3: GAIN ERROR AND FULLSCALE ERROR EXAMPLE. B.10 Gain Error Drift The gain error drift is the variation in gain error due to a change in ambient temperature. The gain error drift is typically expressed in ppm/°C. 2012-2013 Microchip Technology Inc. DS25118D-page 69 MCP47DA1 B.11 Integral Nonlinearity (INL) The integral nonlinearity (INL) error is the maximum deviation of an actual transfer function from an ideal transfer function (straight line). In the MCP47DA1, INL is calculated using two end points (zero and full scale). INL can be expressed as a percentage of Full-Scale Range (FSR) or in a fraction of an LSb. INL is also called relative accuracy. Equation B-4 shows how to calculate the INL error in LSb and Figure B-4 shows an example of INL accuracy. INL error for these devices is the maximum deviation between an actual code transition point and its corresponding ideal transition point after offset and gain errors have been removed. These endpoints are from 0x00-0x20 to 0x60-0x7F for the MCP47DA1. Refer to Figure B-4. Positive INL means higher VOUT voltage than ideal. Negative INL means lower VOUT voltage than ideal. See Figure 2-1 through Figure 2-11 and Figure 2-67 through Figure 2-70 for INL characterization graphs. EQUATION B-4: INL ERROR VOUT – VIdeal INL = --------------------------------------LSb B.12 Differential Nonlinearity (DNL) The differential nonlinearity (DNL) error (see Figure B5) is the measure of step size between codes in actual transfer function. The ideal step size between codes is 1 LSb. A DNL error of zero would imply that every code is exactly 1 LSb wide. If the DNL error is less than 1 LSb, the DAC guarantees monotonic output and no missing codes. The DNL error between any two adjacent codes is calculated as follows: DNL error is the measure of variations in code widths from the ideal code width. A DNL error of zero would imply that every code is exactly 1 LSb wide. See Figure 2-12 through Figure 2-22 and Figure 2-71 through Figure 2-74 for DNL characterization graphs. EQUATION B-5: DNL ERROR V OUT – LSb DNL = ---------------------------------LSb Where: DNL is expressed in LSb. = The measured DAC output VOUT voltage difference between two adjacent input codes. Where: INL is expressed in LSb. = Code*LSb VIdeal VOUT = 111 The output voltage measured with a given DAC input code INL < 0 010 Actual transfer function Ideal transfer function Wide code, > 1 LSb 001 000 101 Wiper Code 101 Actual transfer function Wiper 100 Code 011 111 110 110 Narrow code < 1 LSb 100 011 010 VOUT Output Voltage Ideal transfer function FIGURE B-5: DNL ACCURACY. 001 000 INL < 0 VOUT Output Voltage FIGURE B-4: DS25118D-page 70 INL ACCURACY. 2012-2013 Microchip Technology Inc. MCP47DA1 B.13 Settling Time The Settling time is the time delay required for the VOUT voltage to settle into its new output value. This time is measured from the start of code transition, to when the VOUT voltage is within the specified accuracy. In the MCP47DA1, the settling time is a measure of the time delay until the VOUT voltage reaches within 0.5 LSb of its final value, when the volatile DAC register changes from 40h to 50h. See Figure 2-89 through Figure 2-92 for Settling Time oscilloscope screen captures. B.14 Major-Code Transition Glitch Major-code transition glitch is the impulse energy injected into the DAC analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-Sec, and is measured when the digital code is changed by 1 LSb at the major carry transition (Example: wiper code changes from “011111” to “100000”, or from “100000” to “011111”). B.15 Digital Feedthrough The Digital feedthrough is the glitch that appears at the analog output caused by coupling from the digital input pins of the device. The area of the glitch is expressed in nV-Sec, and is measured with a full-scale change (Example: all 0s to all 1s and vice versa) on the digital input pins. The digital feedthrough is measured when the DAC is not writing to the output register. 2012-2013 Microchip Technology Inc. B.16 Power-Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. The VOUT is measured while the VDD is varied +/- 10%, and expressed in dB or µV/V. B.17 Ratiometric Temperature Coefficient The ratiometric temperature coefficient quantifies the error in the ratio of the resistor setting (Resistance from VREF pin to wiper position (RVREF-W) and the wiper position to Ground (RW-VSS) due to temperature drift. This error also includes the drift of the output driver over temperature. This is typically the critical error when using a DAC. See Figure 2-56 through Figure 2-66 for Tempco characterization graphs. B.18 Absolute Temperature Coefficient The absolute temperature coefficient quantifies the error in the end-to-end output voltage (Nominal output voltage VOUT) due to temperature drift. For a DAC, this error is typically not an issue, due to the ratiometric aspect of the output. Note: Due to the three resistor implementation of the MCP47DA1 (R1, RAB, and R2), R1, RAB and R2 are implemented so that they have a common tempco over-process. DS25118D-page 71 MCP47DA1 NOTES: DS25118D-page 72 2012-2013 Microchip Technology Inc. MCP47DA1 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device Device: I2C™ X XXX /XX I2C Slave Temperature Package Address Range MCP47DA1: 6-bit Single DAC with I2C interface MCP47DA1T: 6-bit Single DAC with I2C interface (Tape and Reel) Slave Address: A0 = 5Ch A1 = 7Ch Temperature Range: E Package: OT = Plastic Small Outline Transistor (SOT-23), 6-lead LT = Plastic Small Outline Transistor (SC70), 6-lead Examples: a) MCP47DA1-A0E/OT: b) MCP47DA1T-A0E/OT: c) MCP47DA1-A1E/OT: d) MCP47DA1T-A1E/OT: e) MCP47DA1T-A0E/LT: f) MCP47DA1T-A1E/LT: = -40°C to +125°C 2012-2013 Microchip Technology Inc. 6-bit DAC, SOT-23-6, Address = 5Ch. 6-bit DAC, SOT-23-6, Address = 5Ch, Tape and Reel. 6-bit DAC, SOT-23-6, Address = 7Ch. 6-bit DAC, SOT-23-6, Address = 7Ch, Tape and Reel. 6-bit DAC, SC70-6, Address = 5Ch. 6-bit DAC, SC70-6, Address = 7Ch. DS25118D-page 73 MCP47DA1 NOTES: DS25118D-page 74 2012-2013 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2012-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620770900 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2012-2013 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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