NB4N527S D

NB4N527S
3.3V, 2.5Gb/s Dual
AnyLevel™ to LVDS
Receiver/Driver/Buffer/
Translator with Internal
Input Termination
http://onsemi.com
NB4N527S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevelTM input signal (LVPECL, CML,
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the
distance, noise immunity of the system design, and transmission line
media, this device will receive, drive or translate data or clock signals
up to 2.5 Gb/s or 1.5 GHz, respectively.
The NB4N527S has a wide input common mode range of
GND + 50 mV to VCC − 50 mV combined with two 50 W internal
termination resistors is ideal for translating differential or
single−ended data or clock signals to 350 mV typical LVDS output
levels without use of any additional external components (Figure 6).
The device is offered in a small 3 mm x 3 mm QFN−16 package.
NB4N527S is targeted for data, wireless and telecom applications as
well as high speed logic interface where jitter and package size are
main requirements. Application notes, models, and support
documentation are available on www.onsemi.com.
• Maximum Input Clock Frequency up to 1.5 GHz
• Maximum Input Data Rate up to 2.5 Gb/s (Figure 5)
• 470 ps Maximum Propagation Delay\
• 1 ps Maximum RMS Jitter
• 140 ps Maximum Rise/Fall Times
• Single Power Supply; VCC = 3.3 V $10%
• Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
• Internal 50 W Termination Resistor per Input Pin
• GND + 50 mV to VCC − 50 mV VCMR Range
• These are Pb−Free Devices
MARKING
DIAGRAM*
16
1
NB4N
527S
ALYW G
G
1
QFN−16
MN SUFFIX
CASE 485G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD0
50 W*
D0
D0
VTD0
VTD1
Q0
Q0
50 W*
50 W*
VOLTAGE (130 mV/div)
D1
D1
VTD1
Device DDJ = 10 ps
Q1
Q1
50 W*
Figure 1. Functional Block Diagram
*RTIN
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 5
1
Publication Order Number:
NB4N527S/D
NB4N527S
VTD0 D0
16
VTD1
1
D1
2
Exposed Pad (EP)
D0 VTD0
15
14
13
12 Q0
11 Q0
NB4N527S
D1
3
10 Q1
VTD1
4
9
5
6
7
8
GND
NC
NC
VCC
Q1
Figure 3. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
1
VTD1
−
2
D1
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Noninverted differential clock/data D1 input (Note 1).
3
D1
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Inverted differential clock/data D1 input (Note 1).
4
VTD1
−
Internal 50 W termination pin for D1. (RTIN)
5
GND
−
0 V. Ground.
6, 7
NC
No connect.
8
VCC
Positive Supply Voltage.
9
Q1
LVDS Output
Inverted D1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
10
Q1
LVDS Output
Noninverted D1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
11
Q0
LVDS Output
Inverted D0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
12
Q0
LVDS Output
Noninverted D0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
13
VTD0
−
14
D0
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Noninverted differential clock/data D0 input (Note 1).
15
D0
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Inverted differential clock/data D0 input (Note 1).
16
VTD0
−
EP
Description
Internal 50 W termination pin for D1. (RTIN)
Internal 50 W termination pin for D0.
Internal 50 W termination pin for D0.
Exposed pad. EP on the package bottom is thermally connected to the die
improved heat transfer out of package. The pad is not electrically connected
to the die, but is recommended to be soldered to GND on the PCB.
1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage
or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to self−oscillation.
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2
NB4N527S
Table 2. ATTRIBUTES
Characteristics
Value
Moisture Sensitivity (Note 2)
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 1 kV
Transistor Count
281
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
3.8
V
3.8
V
35
70
mA
mA
12
24
mA
−40 to +85
°C
−65 to +150
°C
VCC
Positive Power Supply
GND = 0 V
VI
Positive Input
GND = 0 V
IIN
Input Current Through RT (50 W Resistor)
Static
Surge
IOSC
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−End (Q or Q to GND)
Q or Q to GND
Q to Q
TA
Operating Temperature Range
QFN−16
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient) (Note 3)
0 lfpm
500 lfpm
QFN−16
QFN−16
41.6
35.2
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
1S2P (Note 3)
QFN−16
4.0
°C/W
Tsol
Wave Solder
265
265
°C
Pb
Pb−Free
VI = VCC
Continuous
Continuous
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB4N527S
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C
Symbol
ICC
Characteristic
Min
Power Supply Current (Note 8)
Typ
Max
Unit
40
53
mA
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 11, 12, 16, and 18)
Vth
Input Threshold Reference Voltage Range (Note 7)
GND +100
VCC − 100
mV
VIH
Single−ended Input HIGH Voltage
Vth + 100
VCC
mV
VIL
Single−ended Input LOW Voltage
GND
Vth − 100
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8, 9, 10, 17, and 19)
VIHD
Differential Input HIGH Voltage
100
VCC
mV
VILD
Differential Input LOW Voltage
GND
VCC − 100
mV
VCMR
Input Common Mode Range (Differential Configuration)
GND + 50
VCC − 50
mV
VID
Differential Input Voltage (VIHD − VILD)
100
VCC
mV
RTIN
Internal Input Termination Resistor
40
60
W
450
mV
25
mV
1375
mV
1
25
mV
1425
1600
mV
50
LVDS OUTPUTS (Note 4)
VOD
Differential Output Voltage
250
DVOD
Change in Magnitude of VOD for Complementary Output States (Note 9)
VOS
Offset Voltage (Figure 15)
DVOS
Change in Magnitude of VOS for Complementary Output States (Note 9)
VOH
Output HIGH Voltage (Note 5)
VOL
Output LOW Voltage (Note 6)
0
1
1125
0
900
1075
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 14.
5. VOHmax = VOSmax + ½ VODmax.
6. VOLmax = VOSmin − ½ VODmax.
7. Vth is applied to the complementary input when operating in single−ended mode.
8. Input termination pins open, Dx/Dx at the DC level within VCMR and output pins loaded with RL = 100 W across differential.
9. Parameter guaranteed by design verification not tested in production.
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4
NB4N527S
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 10)
−40°C
Characteristic
Symbol
Typ
220
200
25°C
Max
Min
Typ
350
300
220
200
85°C
Max
Min
Typ
Max
350
300
220
200
350
300
mV
1.5
2.5
1.5
2.5
Gb/s
270
370
470
270
370
470
ps
ps
VOUTPP
Output Voltage Amplitude (@ VINPPmin)
(Figure 4)
fDATA
Maximum Operating Data Rate
1.5
2.5
tPLH,
tPHL
Differential Input to Differential Output
Propagation Delay
270
370
470
tSKEW
Duty Cycle Skew (Note 11)
Within Device Skew (Note 17)
Device−to−Device Skew (Note 15)
8
5
30
45
25
100
8
5
30
45
25
100
8
5
30
45
25
100
tJITTER
RMS Random Clock Jitter (Note 13)
0.5
0.5
6
7
10
20
1
1
20
20
25
40
0.5
0.5
6
7
10
20
1
1
20
20
25
40
0.5
0.5
6
7
10
20
1
1
20
20
25
40
Deterministic Jitter (Note 14)
Crosstalk Induced Jitter (Note 16)
fin ≤ 1.0 GHz
fin= 1.5 GHz
Min
fin = 1.0 GHz
fin = 1.5 GHz
fDATA = 622 Mb/s
fDATA = 1.5 Gb/s
fDATA = 2.488 Gb/s
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 12)
tr
tf
Output Rise/Fall Times @ 250 MHz
(20% − 80%)
100
Q, Q
60
100
VCC−
GND
100
140
60
VCC−
GND
100
140
60
100
100
Unit
ps
VCC−
GND
mV
140
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured by forcing VINPPmin with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W across
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
11. See Figure 13 differential measurement of tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform @ 250 MHz.
12. Input voltage swing is a single−ended measurement operating in differential mode.
13. RMS jitter with 50% duty cycle input clock signal.
14. Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5.
15. Skew is measured between outputs under identical transition @ 250 MHz.
16. Crosstalk induced jitter is the additive deterministic jitter to channel one with channel two active both running at 622 Gb/s PRBS 223 −1 as
an asynchronous signals.
17. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
OUTPUT VOLTAGE AMPLITUDE (mV)
400
350
300
−40°C
250
85°C
200
25°C
150
100
50
0
0
0.5
1
1.5
2
2.5
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V)
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5
3
VOLTAGE (63.23 mV/div)
NB4N527S
Device DDJ = 10 ps
TIME (58 ps/div)
Figure 5. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 and OC48 mask
(VINPP = 100 mV; Input Signal DDJ = 14 ps)
RC
RC
1.25 kW
1.25 kW
Dx
50 W
1.25 kW
1.25 kW
I
VTDx
VTDx
50 W
Dx
Figure 6. Input Structure
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6
NB4N527S
VCC
NB4N527S
Dx
Zo = 50 W
LVPECL
Driver
VTDx
LVDS
Driver
50 W*
Zo = 50 W
GND
HSTL
Driver
50 W*
VTDx = VTDx = VCC
GND
GND
VCC
LVCMOS
Driver
VTDx
LVTTL
Driver
50 W*
GND
Dx
GND
VCC
VTDx
VTDx
Dx
NB4N527S
Dx
50 W*
50 W*
Dx
1.5 kW
2.5 kW
GND
50 W*
VTDx = VTDx = GND or VDD/2
Depending on Driver.
Zo = 50 W
50 W*
VTDx
50 W*
VTDx
VCC
NB4N527S
Dx
VTDx
NB4N527S
Dx
Figure 10. HSTL Interface
Figure 9. Standard 50 W Load CML Interface
VCC
VCC
Zo = 50 W
Dx
Zo = 50 W
GND
Zo = 50 W
50 W*
GND
Dx
VCC
NB4N527S
Dx
Zo = 50 W
50 W*
GND
VCC
VTDx
VTDx
Figure 8. LVDS Interface
VCC
CML
Driver
50 W*
VTDx
VTDx = VTDx
Figure 7. LVPECL Interface
Zo = 50 W
VCC
VTDx
NB4N527S
Dx
Zo = 50 W
Dx
VTDx = VTDx = VCC − 2.0 V
GND
Zo = 50 W
50 W*
VTDx
VCC
VCC
VCC
GND
GND
GND
VTDx = VTDx = OPEN
VTDx = OPEN
Figure 11. LVCMOS Interface
Figure 12. LVTTL Interface
*RTIN, Internal Input Termination Resistor.
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7
GND
NB4N527S
D
VINPP = VIH(Dx) − VIL(Dx)
D
Q
VOUTPP = VOH(Qx) − VOL(Qx)
Q
tPHL
tPLH
Figure 13. AC Reference Measurement
Q
LVDS
Driver
Device
Zo = 50 W
HI Z Probe
D
100 W
Q
Zo = 50 W
Oscilloscope
D
HI Z Probe
Figure 14. Typical LVDS Termination for Output Driver and Device Evaluation
QN
VOH
VOS
VOD
VOL
QN
Figure 15. LVDS Output
D
VIH
D
Vth
VIL
Vth
D
D
Figure 16. Differential Input Driven
Single−Ended
Figure 17. Differential Inputs Driven
Differentially
VCC
VCC
VIHmax
Vthmax
D
VIL
VILmax
VCMR
Vth
Vthmin
GND
VIH(MAX)
VIH
VINPP = VIHD − VILD
VIL
VIHmin
D
VIH
VILmin
VEE
Figure 18. Vth Diagram
VIL(MIN)
Figure 19. VCMR Diagram
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8
NB4N527S
ORDERING INFORMATION
Package
Shipping†
NB4N527SMNG
QFN−16
(Pb−Free)
123 Units / Rail
NB4N527SMNR2G
QFN−16
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NB4N527S
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G−01
ISSUE E
D
ÇÇÇ
ÇÇÇ
ÇÇÇ
PIN 1
LOCATION
2X
A
B
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
ÉÉ
ÉÉ
EXPOSED Cu
0.10 C
TOP VIEW
(A3)
DETAIL B
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
0.10 C
2X
L
L
A1
DETAIL B
A
0.05 C
ÉÉ
ÉÉ
ÇÇ
A3
MOLD CMPD
ALTERNATE
CONSTRUCTIONS
NOTE 4
A1
SIDE VIEW
C
SEATING
PLANE
16X
L
D2
16X
16X
0.58
PACKAGE
OUTLINE
8
4
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.18 TYP
0.30
0.50
0.00
0.15
RECOMMENDED
SOLDERING FOOTPRINT*
0.10 C A B
DETAIL A
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
1
9
2X
E2
K
2X
1.84 3.30
1
16X
16
e
e/2
BOTTOM VIEW
16X
0.30
b
0.10 C A B
0.05 C
0.50
PITCH
NOTE 3
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB4N527S/D