SC202F 3.5MHz, 500mA Step-down Regulator with Integrated Inductor POWER MANAGEMENT Features Description The SC202F is a high efficiency 500mA step-down regulator that includes an integrated inductor inside the package. The input voltage range makes it ideal for battery operated applications with space limitations. The SC202F operates at a fixed 3.5MHz switching frequency in normal PWM (Pulse-Width Modulation) mode. The SC202F also includes fifteen programmable output voltage settings that can be selected using the four control pins, eliminating the need for external feedback resistors. The output voltage can be fixed to a single setting or dynamically switched between different levels. Pulling all four control pins low disables the output. Input Voltage — 2.9V to 5.5V Output Voltage — 0.8V to 3.3V Output current capability — 500mA Internal inductor 15 programmable output voltages Fast transient response Temperature range — -40 to +85°C Oscillator frequency — 3.5MHz 100% duty cycle capability Quiescent current — 11mA typ Shutdown current — 0.1μA typ Internal soft-start Over-voltage protection Current limit and short circuit protection Over-temperature protection Under-voltage lockout Floating control pin protection MLPQ-13 — 2.5 x 3.0 x 1.0 (mm) package Lead-free and halogen-free WEEE and RoHS compliant The SC202F provides several protection features to safeguard the device under stressed conditions. These include short circuit protection, over-temperature protection, under-voltage lockout, and soft-start to control in-rush current. These features, coupled with the small 2.5 x 3.0 x 1.0 (mm) package, make the SC202F a versatile device ideal for step-down regulation in products needing high efficiency and a small PCB footprint. Applications Optical modules, GN1157B, GN1599 etc Set top boxes Telecommunication equipment Power rails demand small voltage ripple and compact size Typical Application Circuit V IN 2 .9V to 5 .5V SC202F IN C IN 4 .7 μF SNS V OUT 0.8 V to 3.3 V OUT CTL3 C o n tro l L o g ic L in e s CTL2 CTL1 CTL0 Rev 2.0 C OUT 1 0μF GND LX NC © 2016 Semtech Corporation 1 SC202F Pin Configuration Ordering Information LX 1 13 OUT LX 2 12 OUT LX 3 11 OUT SNS 4 10 GND CTL3 5 CTL0 6 Device Package SC202FMLTRT(1)(2) MLPQ-13 — 2.5 x 3.0 SC202FEVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and RoHS compliant and halogen-free. T O P V IE W 9 7 IN 8 C T L1 C T L2 MLPQ-13; 2.5 x 3.0, 13 LEAD θJA = 58°C/W Table 1 – Output Voltage Settings Marking Information 202F yyw w xxxx yyww = Date Code xxxx = Semtech Lot Number CTL3 CTL2 CTL1 CTL0 Vout 0 0 0 0 Off 0 0 0 1 0.80 0 0 1 0 1.00 0 0 1 1 1.20 0 1 0 0 1.40 0 1 0 1 1.50 0 1 1 0 1.60 0 1 1 1 1.80 1 0 0 0 2.3 1 0 0 1 2.35 1 0 1 0 2.00 1 0 1 1 2.4 1 1 0 0 2.45 1 1 0 1 2.8 1 1 1 0 3.00 1 1 1 1 3.30 2 SC202F Absolute Maximum Ratings Recommended Operating Conditions IN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 Input Voltage Range (V) . . . . . . . . . . . . . . . . . . . . . +2.9 to +5.5 LX Voltage (V). . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0 to VIN + 0.5 Operating Temperature Range (°C) . . . . . . . . . . -40 to +85 Other Pins (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to VIN + 0.3 Output Short Circuit to GND . . . . . . . . . . . . . . . . Continuous ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal Information Thermal Resistance, Junction to Ambient(2) (°C/W). . . . . 58 Junction Temperature Range (°C) . . . . . . . . . . . -40 to +150 Storage Temperature Range (°C) . . . . . . . . . . . . -65 to +150 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114-B. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB per JESD51 standards. Electrical Characteristics Unless otherwise specified: VIN= 3.6V, CIN= 4.7μF, COUT=10μF, VOUT=2.0V, TJ(MAX)=125°C, TA= -40 to +85 °C. Typical values are TA=+25 °C Parameter Output Voltage Range Symbol Condition VOUT Min Typ Max Units 0.8 3.3 (1) V -2.0 2.0 % Output Voltage Tolerance VOUT_TOL IOUT = 200mA Line Regulation ΔVLINEREG 2.9 ≤ VIN ≤ 5.5V, IOUT = 200mA 0.3 %/V Load Regulation ΔVLOADREG 200mA ≤ IOUT ≤ 500mA -1 %/A Output Current Capability IOUT 500 Current Limit Threshold ILIMIT 800 Foldback Current Limit IFB_LIM Under-Voltage Lockout VUVLO ILOAD > ILIMIT mA 1300 150 Rising VIN mA mA 2.9 V Hysteresis 200 mV mA Quiescent Current IQ No switching, IOUT = 0mA 11 Shutdown Current ISD VCTL 0-3= 0V 0.1 1.0 μA Output Leakage Current IOUT Into OUT pin 0.1 1.0 μA High Side Switch Resistance(2) RDSON_P IOUT= 100mA 250 Low Side Switch Resistance(3) RDSON_N IOUT= 100mA 350 mΩ Switching Frequency fSW 2.8 3.5 4.2 MHz 3 SC202F Electrical Characteristics (continued) Parameter Symbol Condition Soft-Start tSS Thermal Shutdown TOT Thermal Shutdown Hysteresis Min Typ Max Units VOUT = 90% of final value 100 500 μs Rising temperature 160 °C 20 °C THYST Logic Inputs - CTL0, CTL1, CTL2, and CTL3 Input High Voltage VIH 1.6 Input Low Voltage VIL Input High Current IIH VCTL 0-3= VIN Input Low Current IIL VCTL 0-3= GND V 0.4 V -2.0 5.0 μA -2.0 2.0 μA Notes (1) Maximum output voltage is limited to VIN if the input is less than 3.3V. (2) Measured from IN to LX. (3) Measured from LX to GND. 4 SC202F Typical Characteristics CIN = 4.7μF, COUT = 10μF, TA = 25°C unless otherwise noted. Efficiency vs Load, Vin=3.6V Load Regulation, Vin=3.6V Efficiency vs Load, Vin=4.2V Load Regultation, Vin=4.2V Efficiency vs Load, Vin=5.5V Load Regulation, Vin=5.5V 5 SC202F Typical Characteristics (continued) Switching Frequency vs Temperature Output Voltage vs Temperature Soft Start, Light Load 3 Steps Current Limit, Vout Ramp to Regulation Soft Start, Heavy Load 4 Steps Current Limit, Vout Ramp to Regulation 50mV/div 50mV/div 1V/div 1V/div 5V/div 5V/div 1A/div 1A/div Time (400us/div) Time (400us/div) 5Vin, 2Vout, 3.5MHz, Vout Ripple VID Transition (CTL2 Low_High_Low) 5V/div 10mV/div 2V/div 5V/div 5V/div 500mA/div 500mA/div Time (200ns/div) Time (200us/div) 6 SC202F Typical Characteristics (continued) VID Transition: Voltage Rise, CTL2 Low to High 5V/div VID Transition - Voltage Fall, CTL2 High to Low 5V/div 2V/div 2V/div 5V/div 5V/div 500mA/div 500mA/div Time (10us/div) Time (10us/div) Approaching 100 % Duty Cycle Operation Vin=3.7V, Vout=3.3V Heavy Load 0A to 200mA Load Step Response 50mV/div 50mV/div 5V/div 5V/div 500mA/div 500mA/div Time (1μs/div) Short Circuit Protection:Current Limit for 32 Cycles then to Foldback I-Limit Time (100μs/div) Recovery From Short Circuit: Operating with Foldback I-Limit Ramp up Vout to Regulation 2V/div 2V/div 5V/div 5V/div 1A/div 1A/div Time (4μs/div) Time (10μs/div) 7 SC202F Pin Descriptions Pin Pin Name Pin Function 1, 2, 3 LX 4 SNS Output sense pin — connect to output capacitor for proper sensing of output voltage. 5 CTL3 Control bit 3 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at reset that is removed when CTL3 is pulled above the logic high threshold. 6 CTL0 Control bit 0 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at reset that is removed when CTL0 is pulled above the logic high threshold. 7 CTL1 Control bit 1 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at reset that is removed when CTL1 is pulled above the logic high threshold. 8 CTL2 Control bit 2 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at reset that is removed when CTL2 is pulled above the logic high threshold. 9 IN 10 GND Ground reference and power ground for the SC202F. 11, 12, 13 OUT Regulator output pin — connect a 10μF ceramic capacitor to this pin for proper filtering. Switching node sense pin — for test purposes only. Input power supply pin — connect a bypass capacitor from this pin to GND. 8 SC202F Block Diagram P lim it A m p 9 IN C u rre n t A m p O S C & S lo p e G e n e ra to r A LX C o n tro l L o g ic 1 μH B OUT PW M Com p 5 0 0m V Ref E rro r A m p N lim it A m p 1 0 GND CTL3 5 CTL2 8 CTL1 7 CTL0 6 SNS 4 V o lta g e S e le ct A = p in s 1 , 2 , 3 B = p in s 1 1, 1 2 , 1 3 9 SC202F Applications Information General Description The SC202F is a synchronous step-down PWM (Pulse Width Modulated) DC-DC regulator utilizing a 3.5MHz fixed-frequency voltage-mode architecture and an internal 1μH inductor. The device is designed to operate in fixed-frequency PWM mode. Two capacitors are the only external components required — one for input decoupling and one for output filtering. The output voltage is programmable, eliminating the need for external programming resistors. Loop compensation is also internal, eliminating the need for external components to control stability. Programmable Output Voltage The SC202F has 15 fixed output voltage levels which can be individually selected by programming the CTL control pins (CTL3-0 — see Table 1 on page 2 for settings). The device is disabled whenever all four CTL pins are pulled low and enabled whenever at least one of the CTL pins is pulled high. This configuration eliminates the need for a dedicated enable pin. Each CTL pin is internally pulled down via 1MΩ if VIN is below 1.5V or if the voltage on the control pin is below the input high voltage. This ensures that the output is disabled when power is applied if there are no inputs to the CTL pins. Each weak pull-down is disabled whenever its pin is pulled high and remains disabled until all CTL pins are pulled low. The output voltage can be set using different approaches. If a static output voltage is required, the CTL pins can be tied to either IN or GND to set the desired voltage whenever power is applied at IN. If enable control is required, each CTL pin can be tied to either GND or to a microprocessor I/O line to create the desired control code whenever the control signal is forced high. This approach is equivalent to using the CTL pins collectively as a single enable pin. A third option is to connect each of the four CTL pins to individual microprocessor I/O lines. Any of the 15 output voltages can be programmed using this approach. If only two output voltages are needed, the CTL pins can be combined in a way that will reduce the number of I/O lines to 1, 2, or 3, depending on the control code for each desired voltage. Other CTL pins could be hard-wired to GND or IN. This option allows dynamic voltage adjustment for systems that reduce the supply voltage when entering sleep states. Note that applying all zeros to the CTL pins when changing the output voltage will temporarily disable the device, so it is important to avoid this combination when dynamically changing levels. Adjustable Output Voltage Selection If an output voltage other than one of the 15 programmable settings is needed, an external resistor divider network can be added to the SC202F to adjust the output voltage setting. This network scales the output based on the resistor ratio and the programmed output setting. The resistor values can be determined using the equation VOUT ª R RFB 2 º VSET u « FB1 » ISNS u RFB1 ¬ RFB2 ¼ where VOUT is the desired output voltage, VSET is the voltage setting selected by the CTL pins, R FB1 is the resistor between the output capacitor and the SNS pin, RFB2 is the resistor between the SNS pin and ground, and ISNS is the leakage current into the SNS pin during normal operation. The current into the SNS pin is typically 1μA, so the last term of the equation can be neglected if the current through RFB2 is much larger than 1μA. Selecting a resistor value of 10kΩ or lower will simplify the design. If ISNS is neglected and RFB2 is fixed, RFB1 can be determined using the equation RFB1 RFB2 u VOUT VSET VSET Inserting resistance in the feedback loop will adversely affect the system’s transient performance if feed-forward capacitance is not included in the circuit. The circuit in Figure 1 illustrates how the resistor divider and feedforward capacitor can be added to the SC202F schematic. The value of feed-forward capacitance needed can be determined using the equation VSET VOUT 0.5 RFB1 VOUT VSET VSET 0.5 2 CFF 4 u 10 6 u 10 SC202F Applications Information (continued) SC202F V IN IN V OUT OUT C IN C OUT C FF C T L3 C T L2 E nable SNS C T L1 C T L0 R FB1 R FB2 GND Figure 1 – Application Circuit with External Resistors To simplify the design, it is recommended to program the output setting to 1.0V, use resistor values smaller than 10kΩ, and include a feed-forward capacitance calculated with the previous equation. If the output voltage is set to 1.0V, the previous equation reduces to CFF 8 u 10 6 u VOUT 0.52 RFB1 VOUT 1 Example: An output voltage of 1.3V is desired, but this is not a programmable option. What external component values for Figure 1 are needed? Solution: To keep the circuit simple, set RFB2 to 10kΩ so current into the SNS pin can be neglected and set the CTL3-0 pins to 0010 (1.0V setting). The necessary component values for this situation are RFB1 CFF RFB 2 u operation. An internal synchronous NMOS rectifier turns on complementary to the top PMOSFET. VOUT VSET VSET 8 u 10 6 u 3k: VOUT 0.52 RFB1 VOUT 1 5.69nF PWM Operation In order to start up from pre-charged output voltage, SC202F does not allow inductor current to go negative in soft start stage, refer to the soft start waveforms in the Typical Characteristics page. When the output voltage exceeds 90% of the set point, determined by the CTLx combinations, the device will enter fixed 3.5MHz PWM 100% Duty Cycle Operation The duty cycle (percentage of time PMOS is active) increases as VIN decreases to maintain output voltage regulation. As the input voltage approaches the programmed output voltage, the duty cycle approaches 100% (PMOS always on) and the device enters a pass through mode until the input voltage increases or the load decreases enough to allow PWM switching to resume. Protection Features The SC202F provides the following protection features: • • • • • Soft-Start Operation Over-Voltage Protection Current Limit Thermal Shutdown Under-Voltage Lockout Soft Start with Current Limit The soft-start sequence is activated after a CTL code transition from an all zeros code to a non-zero code enables the start up process. From the beginning of a start-up process, the internal reference start-up takes typically 50μs, then PMOS current limit is stepped through four levels: 25%, 40%, 60%, and 100%. Each step is maintained for typically 75μs. A complete 4 steps start-up period could take 350μs. Before VOUT reaches 90%, the inductor current is not allowed to go negative. The inductor current is confined between different current limit levels, 25%, 40%, 60%, or 100% to zero. As VOUT reaches 90% of the target value, the device will transition into a fixed 3.5MHz operation allowing inductor current in both directions. Due to current limit operation, if the load is heavy or the output capacitor is large, the soft start process may experience all 4 current limit steps before reaching 90% target voltage. This will make the soft start time long. If the load is light and output capacitor is small, the device may only need the first current limit step, reaching 90% of target, and transition into PWM operation. This makes the soft 11 SC202F Applications Information (continued) start time shorter. capacitor above this minimum value will reduce the crossover frequency and provide greater phase margin. Over-Voltage Protection Over-voltage protection ensures the output voltage does not rise to a level that could damage its load. When VOUT exceeds the regulation voltage by 15%, the PWM drive is disabled. Switching does not resume until VOUT has fallen below the regulation voltage by 2%. Capacitors with X7R or X5R ceramic dielectric are recommended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application. Current Limit The SC202F switching stage is protected by a current limit function. If the output load exceeds the PMOS current limit for 32 consecutive switching cycles, the device enters fold-back current limit mode and the output current is limited to approximately 150mA. Under these conditions, the output voltage will be the product of IFB-LIM and the load resistance. The load must fall below IFB-LIM for the device to exit fold-back current limit mode. This function makes the device capable of sustaining an indefinite short circuit on its output under fault conditions. In addition to ensuring stability, the output capacitor serves other important functions. This capacitor determines the output voltage ripple — as capacitance increases, ripple voltage decreases. It also supplies current during a large load step for a few switching cycles until the control loop responds (typically 3 switching cycles). Once the loop responds, regulation is restored and the desired output is reached. During the period prior to PWM operation resuming, the relationship between output voltage and output capacitance can be approximated using the equation Thermal Shutdown The SC202F has a thermal shutdown feature to protect the device if the junction temperature exceeds 160°C. During thermal shutdown, the PMOS and NMOS switches are both disabled, tri-stating the LX output. When the junction temperature drops by the hysteresis value (20°C), the device goes through the soft-start process and resumes normal operation. Under-Voltage Lockout UVLO (Under-Voltage Lockout) activates when the supply voltage drops below the falling UVLO threshold. This prevents the device from entering an ambiguous state in which regulation cannot be maintained. Hysteresis of approximately 200mV is included to prevent chattering near the threshold. COUT Selection The internal voltage loop compensation in the SC202F limits the minimum output capacitor value to 10μF. This is due to its influence on the loop crossover frequency, phase margin, and gain margin. Increasing the output COUT 3 u 'ILOAD VDROOP u f This equation can be used to approximate the minimum output capacitance needed to ensure voltage does not droop below an acceptable level. For example, a load step from 50mA to 400mA requiring droop less than 50mV would require the minimum output capacitance to be COUT 3 u 0 .4 0.05 u 3.5 u 10 6 6.0PF In this example, using a standard 10μF capacitor would be adequate to keep voltage droop less than the desired limit. Note that if the voltage droop limit were decreased from 50mV to 25mV, the output capacitance would need to be increased to at least 12μF (twice as much capacitance for half the droop). Capacitance will decrease from the nominal value when a ceramic capacitor is biased with a DC current, so it is important to select a capacitor whose value exceeds the necessary capacitance value at the programmed output voltage. Check the manufacturer’s capacitance vs. DC voltage graphs when selecting an 12 SC202F Applications Information (continued) output capacitor to ensure the capacitance will be adequate. Table 2 lists the manufacturers of recommended output capacitor options. Table 2 — Recommended Output Capacitors Value (μF) Type Rated Voltage (VDC) Dimensions LxWxH (mm) Case Size Murata GRM188R60J106ME47D 10±20% X5R 6.3 1.6x0.8x0.8 0603 Murata GRM21BR60J106K 10±10% X5R 6.3 2.0x1.25x1.25 0805 Taiyo Yuden JMK107BJ106MA-T 10±20% X5R 6.3 1.6x0.8x0.8 0603 TDK C1608X5R0J106MT 10±20% X5R 6.3 1.6x0.8x0.8 0603 Manufacturer Part Number CIN Selection The SC202F input source current will appear as a DC supply current with a triangular ripple imposed on it. To prevent large input voltage ripple, a low ESR ceramic capacitor is required. A minimum value of 4.7μF should be used. It is important to consider the DC voltage coefficient characteristics when determining the actual required value. For example, a 10μF, 6.3V, X5R ceramic capacitor with 5V DC applied may exhibit a capacitance as low as 4.5μF. The value of required input capacitance is estimated by determining the acceptable input ripple voltage and calculating the minimum value required for CIN using the equation CIN VOUT § VOUT · ¨1 ¸ VIN ¨© VIN ¸¹ § 'V · ¨¨ ESR ¸¸f © IOUT ¹ The input voltage ripple is at maximum level when the input voltage is twice the output voltage (50% duty cycle scenario). The input capacitor provides a low impedance loop for the edges of pulsed current drawn by the PMOS switch. Low ESR/ESL X5R ceramic capacitors are recommended for this function. To minimize stray inductance, the capaci- tor should be placed as closely as possible to the IN and GND pins. Table 3 lists recommended input capacitor options from different manufacturers. Table 3 — Recommended Input Capacitors Manufacturer Part Number Value (μF) Type Rated Voltage (VDC) Dimensions LxWxH (mm) Case Size Murata GRM188R60J475K 4.7±10% X5R 6.3 1.6x0.8x0.8 0603 Murata GRM188R60J106K 10±10% X5R 6.3 1.6x0.8x0.8 0603 Taiyo Yuden JMK107BJ475KA 4.7±10% X5R 6.3 1.6x0.8x0.8 0603 TDK C1608X5R0J475KT 4.7±10% X5R 6.3 1.6x0.8x0.8 0603 PCB Layout Considerations The layout diagram in Figure 3 shows a recommended PCB top-layer for the SC202F and supporting components. Specified layout rules must be followed since the layout is critical for achieving the performance specified in the Electrical Characteristics table. Poor layout can degrade the performance of the DC-DC converter and can contribute to EMI problems, ground bounce, and resistive voltage losses. Poor regulation and instability can also result. The following guidelines are recommended for designing a PCB layout: 1. CIN should be placed as close to the IN and GND pins as possible. This capacitor provides a low impedance loop for the pulsed currents present at the buck converter’s input. Use short wide traces to minimize trace impedance. This will also minimize EMI and input voltage ripple by localizing the high frequency current pulses. 2. COUT should be connected as closely as possible to the OUT pin. 3. Use a ground plane referenced to the GND pin. Use several vias to connect to the component side ground to further reduce noise and interference on sensitive circuit nodes. 4. Route the output voltage feedback/sense trace 13 SC202F Applications Information (continued) b e e le ctrica lly co n n e cte d to th e P C B . (connected to the SNS pin) away from the LX node as shown in Figure 2 to minimize noise and magnetic interference. 5. Minimize the resistance from the OUT and GND pins to the load. This will reduce errors in DC regulation due to voltage drops in the traces. 6. The two smaller exposed pads on this package should not be connected to any traces. The area beneath these two pads must be kept clear so that they do not make electrical contact with any traces, including ground. C TL1 IN C TL0 C IN C TL3 GND SNS 3 .5 m m SC 202F LX (n o co n n e ctio n needed) C OUT OUT 3 .8 m m Figure 2 — Recommended PCB Layout 14 SC202F Outline Drawing — MLPQ-13 15 SC202F Land Pattern — MLPQ-13 16 SC202F © Semtech 2016 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. 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Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com 17