JFET Chopper Transistors

J111, J112
JFET Chopper Transistors
N−Channel — Depletion
Features
• Pb−Free Packages are Available*
http://onsemi.com
1 DRAIN
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Drain −Gate Voltage
VDG
−35
Vdc
Gate −Source Voltage
VGS
−35
Vdc
Gate Current
IG
50
mAdc
Total Device Dissipation @ TA = 25°C
Derate above = 25°C
PD
350
2.8
mW
mW/°C
Lead Temperature
TL
300
°C
TJ, Tstg
−65 to +150
°C
Operating and Storage Junction
Temperature Range
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
3
GATE
2 SOURCE
TO−92
CASE 29−11
STYLE 5
1
2
3
MARKING DIAGRAM
J11x
AYWW G
G
J11x = Device Code
x = 1 or 2
A
= Assembly Location
Y
= Year
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 2
1
Publication Order Number:
J111/D
J111, J112
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Max
Unit
V(BR)GSS
35
−
Vdc
IGSS
−
− 1.0
nAdc
− 3.0
− 1.0
− 10
− 5.0
−
1.0
20
5.0
2.0
−
−
−
−
−
30
50
OFF CHARACTERISTICS
Gate −Source Breakdown Voltage
(IG = −1.0 mAdc)
Gate Reverse Current
(VGS = −15 Vdc)
Gate Source Cutoff Voltage
(VDS = 5.0 Vdc, ID = 1.0 mAdc)
VGS(off)
J111
J112
Drain−Cutoff Current
(VDS = 5.0 Vdc, VGS = −10 Vdc)
ID(off)
Vdc
nAdc
ON CHARACTERISTICS
Zero−Gate−Voltage Drain Current(1)
(VDS = 15 Vdc)
IDSS
J111
J112
Static Drain−Source On Resistance
(VDS = 0.1 Vdc)
mAdc
W
rDS(on)
J111
J112
Drain Gate and Source Gate On−Capacitance
(VDS = VGS = 0, f = 1.0 MHz)
Cdg(on)
+
Csg(on)
−
28
pF
Drain Gate Off−Capacitance
(VGS = −10 Vdc, f = 1.0 MHz)
Cdg(off)
−
5.0
pF
Source Gate Off−Capacitance
(VGS = −10 Vdc, f = 1.0 MHz)
Csg(off)
−
5.0
pF
1. Pulse Width = 300 ms, Duty Cycle = 3.0%.
ORDERING INFORMATION
Device
J111RL1
Package
TO−92
J111RL1G
TO−92
(Pb−Free)
J111RLRA
TO−92
J111RLRAG
J111RLRP
J111RLRPG
J112
J112G
J112RL1
TO−92
(Pb−Free)
2000 Units / Tape & Reel
2000 Units / Tape & Reel
TO−92
TO−92
(Pb−Free)
2000 Units / Tape & Reel
TO−92
TO−92
(Pb−Free)
1000 Units / Bulk
TO−92
J112RL1G
TO−92
(Pb−Free)
J112RLRA
TO−92
J112RLRAG
Shipping †
TO−92
(Pb−Free)
2000 Units / Tape & Reel
2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
2
J111, J112
TYPICAL SWITCHING CHARACTERISTICS
1000
TJ = 25°C
500
RK = RD′
200
J111
J112
J113
100
500
VGS(off) = 12 V
= 7.0 V
= 5.0 V
50
20
10
RK = 0
5.0
RK = RD′
200
t r , RISE TIME (ns)
t d(on), TURN−ON DELAY TIME (ns)
1000
TJ = 25°C
VGS(off) = 12 V
= 7.0 V
= 5.0 V
100
50
20
10
RK = 0
5.0
2.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
20
30
1.0
0.5 0.7 1.0
50
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
Figure 1. Turn−On Delay Time
1000
1000
TJ = 25°C
500
J111
J112
J113
200
100
VGS(off) = 12 V
= 7.0 V
= 5.0 V
RK = RD′
J111
J112
J113
200
20
10
RK = 0
5.0
30
50
TJ = 25°C
500
RK = RD′
50
20
Figure 2. Rise Time
t f , FALL TIME (ns)
t d(off), TURN−OFF DELAY TIME (ns)
J111
J112
J113
100
VGS(off) = 12 V
= 7.0 V
= 5.0 V
50
20
RK = 0
10
5.0
2.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
20
30
1.0
0.5 0.7 1.0
50
Figure 3. Turn−Off Delay Time
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
20
30
50
Figure 4. Fall Time
NOTE 1
+VDD
RD
SET VDS(off) = 10 V
INPUT
RK
RGEN
50 W
RT
OUTPUT
50 W
RGG
VGEN
INPUT PULSE
tr ≤ 0.25 ns
tf ≤ 0.5 ns
PULSE WIDTH = 2.0 ms
DUTY CYCLE ≤ 2.0%
50 W
VGG
RGG & RK
RD(RT ) 50)
RDȀ +
RD ) RT ) 50
Figure 5. Switching Time Test Circuit
The switching characteristics shown above were measured using a test
circuit similar to Figure 5. At the beginning of the switching interval,
the gate voltage is at Gate Supply Voltage (−VGG). The Drain−Source
Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due
to the voltage divider. Thus Reverse Transfer Capacitance (Crss) or
Gate−Drain Capacitance (Cgd) is charged to VGG + VDS.
During the turn−on interval, Gate−Source Capacitance (Cgs)
discharges through the series combination of RGen and RK. Cgd must
discharge to VDS(on) through RG and RK in series with the parallel
combination of effective load impedance (R′D) and Drain−Source
Resistance (rds). During the turn−off, this charge flow is reversed.
Predicting turn−on time is somewhat difficult as the channel resistance
rds is a function of the gate−source voltage. While Cgs discharges, VGS
approaches zero and rds decreases. Since Cgd discharges through rds,
turn−on time is non−linear. During turn−off, the situation is reversed
with rds increasing as Cgd charges.
The above switching curves show two impedance conditions; 1) RK
is equal to RD, which simulates the switching behavior of cascaded
stages where the driving source impedance is normally the load
impedance of the previous stage, and 2) RK = 0 (low impedance) the
driving source impedance is that of the generator.
http://onsemi.com
3
20
15
J112
10
J111
10
J113
7.0
5.0
Cgs
C, CAPACITANCE (pF)
y fs, FORWARD TRANSFER ADMITTANCE (mmho
J111, J112
Tchannel = 25°C
VDS = 15 V
7.0
5.0
Cgd
3.0
2.0
3.0
Tchannel = 25°C
(Cds IS NEGLIGIBLE)
1.5
2.0
0.5 0.7
1.0
2.0 3.0
5.0 7.0 10
ID, DRAIN CURRENT (mA)
20
30
1.0
0.03 0.05
50
0.1
Figure 6. Typical Forward Transfer Admittance
IDSS
= 10
160 mA
25
mA
50mA
75mA 100mA
80
0
Tchannel = 25°C
0
1.0
2.0
3.0
4.0
5.0
6.0
VGS, GATE−SOURCE VOLTAGE (VOLTS)
30
2.0
125mA
120
40
10
Figure 7. Typical Capacitance
7.0
rds(on), DRAIN−SOURCE ON−STATE
RESISTANCE (NORMALIZED)
rds(on), DRAIN−SOURCE ON−STATE
RESISTANCE (OHMS)
200
0.3 0.5
1.0
3.0 5.0
VR, REVERSE VOLTAGE (VOLTS)
8.0
ID = 1.0 mA
VGS = 0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
−70
Figure 8. Effect of Gate−Source Voltage
On Drain−Source Resistance
−40
−10
20
50
80
110
Tchannel, CHANNEL TEMPERATURE (°C)
140
170
Figure 9. Effect of Temperature On
Drain−Source On−State Resistance
NOTE 2
90
10
Tchannel = 25°C
9.0
80
70
8.0
7.0
rDS(on) @ VGS = 0
60
50
6.0
VGS(off)
5.0
40
4.0
30
3.0
20
2.0
10
1.0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
IDSS, ZERO−GATE−VOLTAGE DRAIN CURRENT (mA)
Figure 10. Effect of IDSS On Drain−Source
Resistance and Gate−Source Voltage
VGS, GATE−SOURCE VOLTAGE (VOLTS)
rds(on), DRAIN−SOURCE ON−STATE
RESISTANCE (OHMS)
100
The Zero−Gate−Voltage Drain Current (IDSS), is the
principle determinant of other J-FET characteristics.
Figure 10 shows the relationship of Gate−Source Off
Voltage (VGS(off) and Drain−Source On Resistance
(rds(on)) to IDSS. Most of the devices will be within ±10%
of the values shown in Figure 10. This data will be useful
in predicting the characteristic variations for a given part
number.
For example:
Unknown
rds(on) and VGS range for an J112
The electrical characteristics table indicates that an J112
has an IDSS range of 25 to 75 mA. Figure 10, shows
rds(on) = 52 W for IDSS = 25 mA and 30 W for
IDSS = 75 mA. The corresponding VGS values are 2.2 V
and 4.8 V.
http://onsemi.com
4
J111, J112
PACKAGE DIMENSIONS
TO−92 (TO−226)
CASE 29−11
ISSUE AL
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
BEYOND DIMENSION K MINIMUM.
B
R
P
L
SEATING
PLANE
K
DIM
A
B
C
D
G
H
J
K
L
N
P
R
V
D
X X
G
J
H
V
C
SECTION X−X
1
N
N
INCHES
MIN
MAX
0.175
0.205
0.170
0.210
0.125
0.165
0.016
0.021
0.045
0.055
0.095
0.105
0.015
0.020
0.500
−−−
0.250
−−−
0.080
0.105
−−− 0.100
0.115
−−−
0.135
−−−
MILLIMETERS
MIN
MAX
4.45
5.20
4.32
5.33
3.18
4.19
0.407
0.533
1.15
1.39
2.42
2.66
0.39
0.50
12.70
−−−
6.35
−−−
2.04
2.66
−−−
2.54
2.93
−−−
3.43
−−−
STYLE 5:
PIN 1. DRAIN
2. SOURCE
3. GATE
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
Literature Distribution Center for ON Semiconductor
USA/Canada
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Phone: 81−3−5773−3850
Email: [email protected]
http://onsemi.com
5
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
J111/D