AND8381/D SOT-963 527AD Dual MOSFET Package Board Level Application and Thermal Performance http://onsemi.com Prepared by: Anthony M. Volpe APPLICATION NOTE ON Semiconductor INTRODUCTION and aforementioned vias is shown in Figure 3 of the subsequent section. Mounting the device on a pcb requires careful attention toward soldering techniques. Negligent soldering practices may result in a short circuit due to the formation of a conducting bridge across the minuscule distance (0.15 mm) between pins. ON Semiconductor dual small signal MOSFETs offered in the ultra−small SOT−963 527AD package are optimized for power management in space−constrained portable electronics. The package exhibits a 30% smaller mount area than comparable MOSFET solutions offered in a single SOT−723 package and a 60% smaller footprint than SOT−563 devices. This technical note discusses the SOT−963 527AD package overview, pad pattern, evaluation board layout and thermal performance. PACKAGE OVERVIEW Figure 1 illustrates a dual site SOT−963 527AD semiconductor device package and pin−out description. This 1 mm x 0.8 mm package features short legs which reduce the thermal path to an external heatsink/pcb. Also, the low vertical clearance (< 0.5 mm) allows for an easy fit in extremely thin environments. The efficient and compact design of this package promotes increased thermal dissipation and reduced electrical parasitics. 1 Figure 2. Minimum Recommended Pad Pattern STYLE 9: PIN 1. SOURCE 1 2. GATE 1 3. DRAIN 2 4. SOURCE 2 5. GATE 2 6. DRAIN 1 EVALUATION BOARD The evaluation board, shown in Figure 3, measures 0.6 in by 0.5 in. The board contains 1.0 oz copper thickness on top−side and 1.0 oz copper thickness on the underside. Vias are added through to the underside of the board where contact is made with a copper pad area of approximately 0.198 square inch. On top−side, the copper pad areas surrounding the two drain leads are each increased to approximately 0.031 square inch for a total dissipation path area of 0.229 square inch per drain. Figure 1. SOT−963 527AD PAD PATTERN A recommended solder−mask defined mounting footprint is defined in Figure 2. Increased thermal dissipation is promoted by adding vias to other pcb layers. An evaluation board containing the minimum recommended pad pattern © Semiconductor Components Industries, LLC, 2009 January, 2009 − Rev. 0 1 Publication Order Number: AND8381/D AND8381/D Front of Board Back of Board Figure 3. Evaluation Board This 6−pin DIP design allows the use of sockets which facilitates wire interfacing. Figure 4 represents a SOT−963 527AA package mounted on the evaluation board with and without test pins. A quick thermal analysis of this board is conducted by inducing a saturation current of 829 mA. This yields a junction temperature of 143.0°C and a board temperature of 53.9°C. Figure 5 shows a thermal image of this board under the aforementioned conditions. Figure 4. Mounted Device Figure 5. Thermal Image of Mounted Device Further results from the measured thermal performance of this package are described in the subsequent section. Testing included a thermal analysis of the package surface mounted on a FR4 board using the minimum recommended pad size. http://onsemi.com 2 AND8381/D THERMAL PERFORMANCE Foster network is used to calculate various thermal characteristics. For example, as seen in Figure 8, a particular thermal resistance occurs between the junction and C1/C2 node (denoted here as YJn−L). Then, the sum of all thermal references between the C1/C2 node and the Cn−1/Cn node is called a junction−to−foot thermal reference (YJn−Fn). Therefore, in the case of Figure 8, the junction−to−ambient thermal resistance (RqJnA) is measured as the sum of thermal references such that; Assumptions and Definitions The subsequent sections outline the thermal performance of a SOT−963 527AD. All values and equations are obtained from simulations and pertain to the Theta(DC) matrix with both MOSFETs operating at maximum power unless otherwise specified. A 10% duty cycle is arbitrarily chosen to evaluate various thermal responses. Refer to Figure 10 for thermal responses at different duty cycles. The simulation models used to derive the results in this section are modeled around results obtained from physical testing and are considered reliable. Table 1 defines a set of parameters used throughout this section. R qJnA + Y Jn*Fn ) Y Fn*A Junction C1 Table 1. THERMAL ANALYSIS PARAMETERS Symbol R1 YJ−Fn R2 YL−L’ C2 (eq. 1) YL’−Fn Rn YFn−A Cn−1 Cn Ambient (Thermal Ground) Definition TJn Junction Temperature of MOSFET “n” TA Ambient Temperature PDn Power Dissipation of MOSFET “n” PTOTAL Total Power Dissipation Rq−JnL Thermal Resistance from Junction “n” to Location ”L” Figure 7. Grounded Capacitor Thermal Network (“Cauer” Ladder) Junction R(u)EFF Effective (maximum) Thermal Resistance of Package YFn−L Thermal Reference between Foot ”n” and location ”L” YJn−L Thermal Reference between Junction “n” and location ”L” R1 YJ−Fn R2 YL−L’ C1 C2 YL’−Fn Rn YFn−A Cn−1 Cn Ambient (Thermal Ground) Figure 8. Non−Grounded Capacitor Thermal Network (“Foster” Ladder) Junction−to−Foot / Foot−to−Ambient The number designation associated with “foot” in the subscript of each Y (read psi) term corresponds to the pin identification number as shown in Figure 6. The Foster Network junction−to−foot thermal references and foot−to−ambient thermal references under steady state conditions at TA = 25°C are outlined in Table 2. The values below are derived using J1 as an initial reference. It is important to note that using J2 as an initial reference yields different values for the psi terms in Table 2 but the thermal resistance value does not change. Table 2. THERMAL REFERENCE PARAMETERS 10% Duty Cycle PD1 = PD2 Copper Area Figure 6. Foot and Junction Identification 100 mm2 (1 oz) 0.210 mW 500 mm2 (1 oz) 369.4°C/W 346.8°C/W YJ1−F6 231.7°C/W 241.7°C/W PD1 = PD2 Foot−to−Ambient 0.175 mW 0.210 mW 100 mm2 (1 oz) 500 mm2 (1 oz) YF3−A 159.0°C/W 105.8°C/W YF6−A 296.7°C/W 210.9°C/W Copper Area http://onsemi.com 3 0.175 mW YJ1−F3 10% Duty Cycle Figures 7 and 8 represent Cauer and Foster Ladders respectively. This technical note assumes the reader has a general understanding of these networks. Please refer to the documentation cited under references for detailed descriptions of thermal RC networks. In this section, the Junction−to−Foot AND8381/D following matrix equation illustrates the aforementioned relationships for a junction−to−ambient thermal response; A relationship for the thermal resistance of each device is established by using either of the following relationships, R qJ1A + Y J1*F3 ) Y F3*A (eq. 2) R qJ1A + Y J1*F6 ) Y F6*A (eq. 3) NJ Nj ƪ TJ1 TJ2 Substituting appropriate values, from Table 2, into the above equations yields RqJ1A = RqJ2A = 528.4°C/W for the FR−4 at 100 mm2 and RqJ1A = RqJ2A = 452.6°C/W for FR−4 at 500 mm2 min pad size. In both cases the thermal resistances of each device are directly proportional to each other due to symmetrical die sizes. ƫNJ Nj R qJ1A Y Q1Q2 + Y Q2Q1 R qJ2A P D1 P D2 ) TA (eq. 4) Using data from Table 3, this matrix allows various junction temperatures and, in turn, the package R(u)EFF to be calculated at assumed ambient temperatures. R(u)EFF is defined as, R (u)EFF + ƪT MAX * T A ƫ ń P TOTAL (eq. 5) Where R(u)EFF is a function of either direct current or a transient response and TMAX is the maximum junction temperature between TJ1 and TJ2. Table 3 outlines the junction−to−ambient thermal analysis of this package, using J1 as the initial reference. Notice that RqJ1A = RqJ2A and YQ1Q2 = YQ2Q1 due to symmetrical die sizes. Furthermore, Quick reference steady state matrices are located in the Appendix. Junction−to−Ambient The thermal response of this package is parameterized by thermal interactions between adjacent MOSFETS. Switching one device OFF, such as Q1, alters the junction temperature and thermal resistance of each FET. Heat from Q2 will transfer to Q1 causing Q1 to exhibit an added thermal resistance equivalent to a factor of YQ1Q2. The Table 3. JUNCTION−TO−AMBIENT THERMAL RESPONSE 10% Duty Cycle Steady State Copper area PD1 = PD2 TAMB Rq−JA R(t)q−JA YQ1Q2 = YQ2Q1 Pulsed time = 5 sec 100 mm2 (1 oz) 500 mm2 (1 oz) 100 mm2 (1 oz) 175 mW 210 mW 175 mW 25.0°C 25.0°C 25.0°C 528.4°C/W 452.6°C/W 198.5°C/W 146.7°C/W 152.2°C 151.0°C TJ1 TJ2 528.4°C/W 366.9°C/W* 67.3°C/W* 152.2°C TJ (t) 101.0°C* R(DC)EFF 363.0°C/W R(t)EFF 300.0°C/W 363.0°C/W 217.0°C/W *Refer to Appendix−A for Theta(t) matrix equations. Junction−to−Board A matrix equation yielding junction temperatures for assumed board temperatures is defined by equation 6, NJ Nj TJ1 TJ2 + ƪ ǒRqJ1A * Y B*AǓ ǒY Q1Q2 * Y B*AǓ ǒY Q2Q1 * Y B*AǓ ǒRqJA1 * Y B*AǓ ƫNJ Nj P D1 P D2 ) T BOARD (eq. 6) Where YB−A is the thermal reference from board−to−ambient. Values for RqJA and YQ1Q2 are defined in Table 3. Table 4 outlines the junction−to−board thermal analysis of this package surface mounted on an FR4 board. Furthermore, Quick reference steady state matrices are located in the Appendix. http://onsemi.com 4 AND8381/D Table 4. JUNCTION−TO−BOARD THERMAL RESPONSE 10% Duty Cycle Steady State Cu area 100 PD1 = PD2 mm2 [1 oz] Pulsed time = 5 sec 500 mm2 100 mm2 [1 oz] [1 oz] 175 mW 210 mW 175 mW TAMB 25.0°C 25.0°C 25.0°C Y(t)B−A 199.1°C 143.7°C TJ1 = TJ2 TJ1(t) = TJ2(t) TBOARD (DC) TBOARD (t) R(DC)EFF−BOARD R(t)EFF−BOARD 152.0°C 151.0°C 95.0°C 85.0°C 199.0°C/W 144.0°C/W 67.4°C* 152.0°C* 101.0°C 95.0°C 49.0°C 199.0°C/W 67.0°C/W *Refer to Appendix−A for Theta(t) matrix equations. SUMMARY Table 5. MAXIMUM RATINGS Cu Area RqJ1A Max Power 100 mm2 [1 oz] 528.4°C/W 0.237 W 452.6°C/W 0.276 W 500 580 [1 oz] TA 25°C qJA Curve with PCB cu thk 1.0 oz 530 mm2 Power Curve PCB cu thk 2.0 oz RqJA (°C/W) 480 0.31 0.3 0.29 0.28 430 0.27 qJA Curve with PCB cu thk 2.0 oz 380 0.26 0.25 0.24 330 280 0.32 0 Power Curve PCB cu thk 1.0 oz 100 200 300 400 500 600 COPPER HEAT SPREADER AREA (mm2) 0.23 0.22 700 Figure 9. Self−Heating Thermal Characteristics as a Function of Copper Area on the PCB http://onsemi.com 5 MAXIMUM POWER (W) Figure 9 illustrates a steady state plot of the change in thermal resistance and max power dissipation that occurs with a change in the amount of copper spread across a given area. Figure 10 illustrates the packages change in junction−to−ambient thermal resistance with respect to pulse time. Evaluating these plots by inspection yields the following maximum values; AND8381/D 1000 @50% Duty Cycle 100 20% 10% 5% 2% R(t)EFF (C/W) 10 1% Single Pulse 1 0.1 0.01 Psi LA(t) 0.001 0.000001 0.00001 0.0001 0.001 0.01 0.1 Pulse Time (sec) 1 10 100 1000 Figure 10. Thermal Response References 1. R.P. Stout, D.T. Billings, “How to Extend a Thermal−RC−Network Model (Derived From Experimental Data) to Respond to an Arbitrarily Fast Input,” ON Semiconductor, 2006. 2. R.P. Stout, “Thermal RC Ladder Networks; Packaging Technology Development ,” ON Semiconductor, 2006. 3. R.P. Stout, “General Thermal Transient RC Networks,” ON Semiconductor, 2006. http://onsemi.com 6 AND8381/D APPENDIX Steady State Junction−to−Ambient Quick Reference Matrix (1 oz. Cu), 10% DC. Steady State Junction−to−Board Quick Reference Matrix (1 oz. Cu), 10% DC. FR−4 at 100 mm2 NJ Nj ƪ TJ1 TJ2 ƫNJ 528.4 198.5 + 198.5 528.4 NJ Nj ƪ Nj TJ1 TJ2 0.175 0.175 ) T A FR−4 at 500 mm2 NJ Nj ƪ TJ1 TJ2 + 452.6 146.7 146.7 452.6 ƫNJ 329.3 −0.6 + −0.6 329.3 NJ Nj ƪ Nj TJ1 TJ2 0.21 0.21 ) TA ƪ m RȀ qJ1A + S Y(t ) n+1 n qJ1A NJ Njƪ TJ1 TJ2 ƫ ƪ1 * expǒ−tpulseńtnǓƫ (eq. 8) ƫNJ Nj RȀ qJ1A YȀ Q1Q2 YȀ Q2Q1 RȀ qJ1A P D1 P D2 ) T A (eq. 9) Junction−to−Board Theta(t) Matrix Equations m YȀ B*A + NJ Nj TJ1 TJ2 + S n+1 ƪ Y(t n) B*A ƪ1 * expǒ−tpulseńtnǓƫ (eq. 10) ƫNJ ǒRȀ qJ1A * YȀ B*AǓ ǒYȀQ1Q2 * YȀB*AǓ ǒYȀQ2Q1 * YȀ B*AǓ ǒRȀqJ1A * YȀB*AǓ Nj P D1 P D2 ) T BOARD http://onsemi.com 7 (eq. 11) ƫNJ Nj 0.175 0.175 ) TBOARD FR−4 at 500 mm2 308.9 3.0 + 3.0 308.9 Junction−to−Ambient Theta(t) Matrix Equations m YȀ QXQY + 1 * expǒ−t pulseńt nǓ (eq. 7) Y(t n) J*A n+1 S FR−4 at 100 mm2 ƫNJ Nj 0.21 0.21 ) T BOARD AND8381/D PACKAGE DIMENSIONS SOT−963 CASE 527AD−01 ISSUE D D 6 5 A B A L 4 HE E 1 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. C 3 e 6X DIM A b C D E e L HE C b 0.08 C A B MILLIMETERS MIN NOM MAX 0.34 0.37 0.40 0.10 0.15 0.20 0.07 0.12 0.17 0.95 1.00 1.05 0.75 0.80 0.85 0.35 BSC 0.05 0.10 0.15 0.95 1.00 1.05 MIN INCHES NOM MAX 0.004 0.003 0.037 0.03 0.006 0.008 0.005 0.007 0.039 0.041 0.032 0.034 0.014 BSC 0.002 0.004 0.006 0.037 0.039 0.041 SOLDERING FOOTPRINT* 0.35 0.014 0.35 0.014 0.90 0.0354 0.20 0.008 0.20 0.008 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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