SONY CXA1391Q

CXA1391Q/R
Processing IC for Complementary Color Mosaic CCD Camera
Description
The CXA1391Q/R is a bipolar IC developed for
signal processing in complementary color mosaic
CCD cameras.
CXA1391Q
64 pin QFP (Plastic)
Features
• Low power consumption (170mW)
• Number of delay lines used for signal processing
can be selected according to the system
requirements
• The LPF peripheral to 1H delay line is built in
Absolute Maximum Ratings
• Supply voltage
Vcc
• Storage temperature Tstg
• Allowable power dissipation
PD
Structure
Bipolar silicon monolithic IC
DLC1 IN
C1 GAIN
DLCO OUT
R MTX
CLP C MPX1
CLP C MPX2
B MTX
ID
B GAIN
B CONT
R CONT
R GAIN
CLP C B
CLP C G
CLF C R
C LEVEL
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CLP
(CLP4)
CLP C YO 51
Y0
LPF
Y0
Y1
LPF
CLP
(CLP2)
30 WB B
29 WB G
28 WB R
R-r
G-r
B-r
2H
APCN
V-APCN
LPF ADJ 1 59
LPF ADJ 2 60
LPF ADJ 3 61
23 CS GAIN
V-APCN
LPF
YH0
V CC 62
CLP
(CLP4)
GC
YH1
22 R – Y HUE
21 B – Y HUE
20 R – Y OUT
19 B – Y OUT
18 B – Y GAIN
YH0
DLYH OUT
YH OUT 1
YH OUT 2
TP
9
10
11
12
13
14
15
16
CS IN
CLP C DLYH
8
CLP C CS
7
VAP SLICE
6
CLP C VAP
5
VAP GAIN
4
VAP OUT
3
CLP2
2
CLP4
1
DLYH IN
17 R – Y GAIN
CLP C YH
r
DLYH GAIN
CLP
(CLP2)
GC
Y-r CONT 63
YH IN 64
25 YL OUT
24 CS OUT
R-Y
MTX
R-Y B-Y
Hue & GC
–
CS VAP MAX
LPF
CS-Y
CS
CLP
(CLP4)
3H
APCN
YH1
26 GND 1
B-Y
–
–
GND 2 58
KNEE
Y2 GAIN 57
GC
ABS
CS-Y
LPF
G ch SLICE
SLICE
CLP
CLP
(CLP4) Y2
CLP V-APCN
(CLP4)
GC
Y0
DLY2 IN 56
KNEE
LPF
Y2
Y1
CLP
(CLP4) Y1
KNEE
GC
27 C-r CONT
r
Y1 GAIN 54
R-r
SLICE
DLY1 OUT 53
DLY1 IN 55
31 WB DC
YL MTX
DLY0 OUT 52
CLP
(CLP4)
GC
32 C SLICE
LPF
B-r
Y0
C0 CLP -CB
B
LPF
(CLP2) CR
G
&
Y MATRIX R WB AMP
C1 MPX
LPF
G-r
S1 IN 50
V
°C
WB CONTROL
LPF
R-WB
G-WB
B-WB
C0
S2 IN 49
7
–55 to +150
690
mW
(LQFP: Ta = 25°C, without P.C.B)
Recommended Operating Conditions
• Supply voltage
Vcc
4.75 to 5.25
V
• Ambient temperature Topr
–20 to +75
°C
Applications
Complementary color mosaic CCD cameras
Block Diagram and Pin Configuration
(Top View)
CXA1391R
64 pin LQFP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E89Z18-ST
CXA1391Q/R
Pin Description
PIn
No.
Symbol
Pin voltage
Equivalent circuit
Description
1
2.4k
1
CLP C YH
2.4k
800
1k
3 to 3.5V
Capacitor connecting pin
for YH clamp
(Clamp at CLP2)
147
180µA
80µA
1k
DL YH signal input pin
(Input from 1H delay line)
147
2
DL YH IN
2
3.65V
Sig: Typ. 200mV
(Positive polarity)
5k
80µA
3
2.6k
3
CLP C
DL YH
1k
2.6k
1k
147
Capacitor connecting pin
for DL YH clamp
(Clamp at CLP4)
2.6 to 3.8V
180µA
40µA
200
4
DL YH
OUT
DL YH signal output pin
(To 1H delay line)
2.7 to 3.1V
4
400µA
Note) Pin voltage for input and output pins indicate black level.
–2–
Sig: Typ. 400mV
Max. 600mV
(Negative polarity)
CXA1391Q/R
PIn
No.
Symbol
Pin voltage
Equivalent circuit
Description
100
5
YH OUT1
YH1 signal output pin
1.9 to 2.3V
Sig: Typ. 1V
Max. 1.5V
(Positive polarity)
5
160µA
100
6
YH OUT2
YH2 signal output pin
1.9 to 2.3V
Sig: Typ. 1V
Max. 1.5V
(Positive polarity)
6
400µA
2.6 to 3.0V
(YH)
7
TP
TP OUT (adjusting pin)
1H mode: Outputs YH1–YH0
0H mode: Outputs Gch
C-slice OUT
(Mode selection is executed
through Pin 8)
500
2.5 to 2.9V
(G)
7
80µA
0V
(0H Mode)
8
DL YH GAIN
1.8 to 5V
(1H Mode)
54
Y1 GAIN
0V:
Common
control by
Pin 57
1.8 to 5V
Independent
control
1k
30k
30k
40µA
–3–
100k
147
8 54
100k
DL YH signal gain control
pin
(For 1H delay line gain
compensation of YH)
TP (Pin 7) mode selection
0H Mode: 0V
1H Mode: 1.8 to 5V
DLY1 signal gain control pin
(1H delay line gain
compensation)
0V: DLY1 signal gain
control is executed in
common with DLY2
signal gain control.
1.8 to 5V: DLY1 signal gain
control is executed
independently from
DLY2 signal gain
control.
CXA1391Q/R
PIn
No.
Symbol
Pin voltage
Equivalent circuit
5V
9
1k
CLP4
Description
CLP4 pulse input pin
(BLK clamp)
(CMOS level input,
VTH = 2.5V)
30k
0
9
5V
10
CLP2 pulse input pin
(OPB clamp)
(CMOS level input,
VTH = 2.5V)
10
CLP2
40µA
0
431
V-APCN signal output pin∗
11
VAP OUT
2.6 to 3.0V
11
Sig: Max. 1.2Vp-p
280µA
1k
147
12
VAP GAIN
1.8 to 5V
(Control)
12
25k
V-APCN signal output level
adjustment pin
25k
40µA
2.6k
2.6k
1k
13
CLP C VAP
Capacitor connecting pin
for VAP clamp
(Clamp at CLP4)
3.4 to 3.8V
147
147
180µA
12µA
13
∗ V-APCN: Vertical Aperture Compensation
–4–
CXA1391Q/R
PIn
No.
Symbol
Pin voltage
Equivalent circuit
Description
1k
147
14
VAP SLICE
14
1.8 to 5V
(Control)
30k
V-APCN signal
dark slice volume
adjustment pin
30k
40µA
2.6k
2.6k
1k
15
CLP C CS
Capacitor connecting pin
for CS clamp
(Clamp at CLP4)
3.5 to 3.7V
147
147
180µA
20µA
15
2.6k
2.6k
1k
147
16
CS IN
C-Couple
input
2.9 to 3.3V
AGC CS signal input pin
16
147
Sig: Max. 1V
180µA
–5–
20µA
CXA1391Q/R
R–Y GAIN
0V:
R–G output
1.8 to 5V:
R–Y output
R–Y signal output level
adjustment pin
Pin 20 Mode select
0V: R–G output
1.8 to 5V: R–Y output
18
B–Y GAIN
0V:
B–G output
1.8 to 5V:
B–Y output
B–Y signal output level
adjustment pin
Pin 19 Mode select
0V: B–G output
1.8 to 5V: B–Y output
23
CS GAIN
1.8 to 5V
(Control)
19
B–Y OUT
20
R–Y OUT
2.75 to 3.15V
(Hue OFF)
2.35 to 2.75V
(Hue ON)
46
DLC0 OUT
1.8 to 2.2V
52
DLY0 OUT
1.4 to 1.8V
53
DLY1 OUT
2.8 to 3.2V
21
B–Y Hue
17
V-APCN CS signal
gain control pin
0V:
B–Y hue control pin
R–Y hue control pin
–6–
CXA1391Q/R
PIn
No.
Symbol
Pin voltage
Equivalent circuit
Description
431
CS signal output pin
24
CS OUT
1.5 to 1.8V
24
Sig: Max. 1V
200µA
431
25
YL OUT
YL signal output pin
1.9 to 2.3V
25
80µA
26
GND
GND1
1k
27
C-γ CONT
100k
Chroma (R.G.B)
γ curve adjustment pin
0V: Typ.
γ curve
30k
30k
147
40µA
27
–7–
CXA1391Q/R
PIn
No.
28
Symbol
WB R
Pin voltage
Equivalent circuit
Description
R signal output pin
WB Mode:
Sig: Typ. 400mV
γ Mode:
Sig: Typ. 500mV
1.4 to 2V
431
G signal output pin
WB Mode:
Sig: Typ. 400mV
γ Mode:
Sig: Typ. 500mV
28
29
WB G
1.4 to 2V
29
30
200µA
30
WB B
B signal output pin
WB Mode:
Sig: Typ. 400mV
γ Mode:
Sig: Typ. 500mV
1.4 to 2V
431
31
WB DC
1k
300
1.4 to 2V
200µA
100k
31
100k
32
C SLICE
When connected to Vcc:
Pins 28, 29 and 30 turn to
γ mode.
1k
32
0V:
Slice OFF
When used as output pin,
it is an Auto WB DC output
pin.
Pin 28, 29 and 30 turn
to WB mode.
18k
18k
Chroma (R.G.B) signals
dark slice level adjustment
pin
67µA
33
C LEVEL
1.8 to 5V
(Control)
Chroma (R.G.B) gain
control pin
(Chroma modulation factor
control for all 3 channels)
1k
33
47
30k
47
C1 GAIN
30k
1.8 to 5V
(Control)
40µA
–8–
DL C1 signal gain control
pin
(1H delay line gain
compensation)
CXA1391Q/R
PIn
No.
34
Symbol
CLP C R
Pin voltage
Equivalent circuit
Description
Capacitor connecting pin
for R WB amplifier clamp
(Clamp at CLP2)
3.0 to 3.6V
2.2k
2.2k
1k
1k
35
CLP C G
Capacitor connecting pin
for G WB amplifier clamp
(Clamp at CLP2)
147
3.0 to 3.6V
34 35 36
125µA
36
CLP C B
3.0 to 3.6V
37
R GAIN
1.8 to 5V
(Control)
40µA
Capacitor connecting pin
for B WB amplifier clamp
(Clamp at CLP2)
Rch WB amplifier gain
control pin
(Pre-WB)
1k
147
37
40
15k
40
B GAIN
1.8 to 5V
(Control)
38
R CONT
2.5 to 4.6V
15k
80µA
1k
Bch WB amplifier gain
control pin
(Pre-WB)
Rch WB amplifier gain
control pin
147
38
39
39
B CONT
2.5 to 4.6V
10µA
–9–
Bch WB amplifier gain
control pin
CXA1391Q/R
PIn
No.
Symbol
Pin voltage
Equivalent circuit
Description
1k
ID pulse
(color discrimination pulse)
input pin
(CMOS level VIH = 2.5V)
30k
147
41
ID
5V
41
ID = L C0 → CR
C1 → CB
0
40µA
1k
ID = H C0 → CB
C1 → CR
100k
1.8 to 5V
(Control)
42
B MTX
0V
(Preset)
15k
15k
80µA
43
CLP C
MPX2
2.7 to 3.1V
147
42
1k
147
43
44
147
6k
44
CLP C
MPX1
100k
B signal operations MTX
coefficient adjustment pin
(Coefficient 0.22)
Refer to Note 2.
6k
2.7 to 3.1V
40µA
– 10 –
Capacitor connecting pin
for MPX clamp
(Clamp at CLP2)
CXA1391Q/R
PIn
No.
Symbol
Pin voltage
Equivalent circuit
1k
Description
100k
1.8 to 5V
(Control)
45
R MTX
30k
0V
(Preset)
300k
40µA
48
55
DLC1 IN
C-Couple
input
3.1 to 3.5V
DLY1 IN
C-Couple
input
3.6 to 4.0V
DLY2 IN
C-Couple
input
3.6 to 4.0V
2.6k
147
100k
45
2.6k
DL C1 signal input pin
Sig: Typ. 150mVp-p
(Negative polarity)
1k
1k
R signal operations MTX
coefficient adjustment pin
(Coefficient 0.617)
Refer to Note 2.
DL Y1 signal input pin
Sig: Typ. 150mVp-p
(Negative polarity)
147
48 55 56
56
11µA
150µA
DL Y2 signal input pin
Sig: Typ. 150mVp-p
(Negative polarity)
S2 signal input pin
147
49
S2 IN
1.9V
147
49
50
7.5k
40µA
Sig: Typ. 500mV
Max. 1500mV
40µA
S1 signal input pin
1.9V
– 11 –
40µA
40µA
40µA
Sig: Typ. 500mV
Max. 1500mV
40µA
S1 IN
40µA
50
CXA1391Q/R
PIn
No.
Symbol
Pin voltage
Equivalent circuit
Description
1k
2.6k
147
51
CLP C Y0
1k
Capacitor connecting pin
for Y0 clamp
(Clamp at CLP4)
3.3 to 3.7V
51
40µA
150µA
1k
1.8 to 5V
(3H Mode)
57
DL Y2 signal gain control
pin
(1H delay line gain
compensation)
V-APCON mode selection
0V: 2H Mode
1.8 to 5V: 3H Mode
147
57
Y2 GAIN
15k
0V
(2H Mode)
80µA
58
59
GND2
GND
LPF Adj. 1
Connecting pin of the
external resistor that
determines the
characteristics of the LPF
for 1H DL.
(External resistor in the
range of 15 to 27kΩ)
1.8 to 2.2V
5k
20k
300
60
LPF Adj. 2
1.8 to 2.2V
10µA
59 60
– 12 –
Connecting pin of the
external resistor that
determines the
characteristics of the
chroma LPF
(LPF for R, G, B, CS).
(External resistor in the
range of 15 to 62kΩ)
CXA1391Q/R
PIn
No.
Symbol
Pin voltage
Equivalent circuit
Description
1k
300
61
LPF Adj. 3
300
1.8 to 2.2V
10µA
61
120k
62
Connecting pin of the
external resistor that
determines the
characteristics of the LPF
for V-APCN.
(External resistor in the
range of 15 to 62kΩ)
When connected to Vcc,
the LPF for V-APCN turns
OFF.
Vcc
Power supply 5V (Typ.)
1k
100k
0V
(Typ. γ curve)
63
YH γ curve adjustment
Y-γ CONT
1.8 to 5V
(Control)
30k
30k
40µA
147
63
10k
YH signal input
64
YH IN
0.95V
Sig: Typ. 220mV
Max. 660mV
64
– 13 –
CXA1391Q/R
Electrical Characteristics
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
25
34.5
43
mA
Current consumption
ID
S2–S1 Amp Gain
SSG
Input: S1 IN = –62.5mV, S2 IN = 62.5mV
Calculations: DLC0 OUT/S1 IN
–3
–1.95
–1
dB
DLC1
gain control
Max.
Input: DLC1IN = 100mV
Conditions: C1Gain = 5V
DLC1H
C-level = 5V
Calculations: (WB-R/DLC1IN) –CG Note2)
6
7
9
dB
Min.
DLC1L
Conditions: C1Gain = 0V
(Others same as DLC1H)
–2
–0.85
0
dB
SAG
Input: S1 IN = 500mV
Calculations: DLY0OUT/S1 IN
–15
–14
–13
dB
Gch Y
GY
Input: S1 IN = S2 IN = 300mV
Conditions: C-level = 5V
Calculations: WB-G (ID = H, L average)
80
100
120
mV
CR/Y
GCR
Input: S1 IN = S2 IN = 62.5mV
Conditions: C-level = 5V
Calculations: WB-G/GY (ID = L)
0.9
1
1.1
—
–CB/Y
GCB
ID = H (Others same as GCR)
–1.1
–1
–0.9
—
Rch CR
RCR
Input: S1 IN = –62.5mV, S2 IN = 62.5mV
Conditions: C-level = 5V
Calculations: WB-R (ID = L)
70
85
100
mV
Y
(Preset)
RYP
Input: S1 IN = S2 IN = 500mV
Conditions: C-level = 5V
Calculations: WB-R/RCR (ID = H)
0.15
0.168 0.186
—
Y (Max.)
RYH
RMTX = 5V (Others same as RYP)
0.22
0.25
0.27
—
Y (Min.)
RYL
RMTX = 1.8V (Others same as RYP)
0.11
0.125
0.14
—
Bch–CB
BCB
Input: S1 IN = 62.5mV, S2 IN = –62.5mV
Conditions: C-level = 5V
Calculations: WB-B (ID = H)
80
100
120
mV
Y
(Preset)
BYP
Input: S1 IN = S2 IN = 500mV
Conditions: C-level = 5V
Calculations: WB-B/BCB (ID = H)
0.2
0.22
0.24
—
Y (Max.)
BYH
BMTX = 5V (Others same as BYP)
0.31
0.34
0.37
—
Y (Min.)
BYL
BMTX =1.8V (Others same as BYP)
0.13
0.15
0.17
—
S1+S2 Amp
Chroma matrix
(Gch)
Note 3)
Chroma matrix
(Rch)
Note 3)
Chroma matrix
(Bch)
Note 3)
– 14 –
CXA1391Q/R
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
7.5
8.2
8.5
dB
RCONT Max.
RCH
Input: DLC1IN = –200mV
Conditions: C-level = 5V
RCONT = 4.6V (ID = H)
Calculations: WB-R/WB-RTyp. Note 4)
WB-R Typ. is the tested output of WB-R
when RCONT is set to 4V (Other inputs,
conditions same as RCH)
RCONT Min.
RCL
Test: RCONT = 2.5V
(Others same as RCH)
–8.4
–7.9
–7.4
dB
BCONT Max.
BCH
Input: DLC1IN = 150mV
Conditions: C-level = 5V
BCONT = 4.6V (ID = L)
Calculations: WB-B/WB-BTyp. Note 4)
WB-B Typ. is the tested output of WB-B
when BCONT is set to 4V (Other inputs,
conditions same as BCH)
7.5
8.2
8.5
dB
BCONT Min.
BCL
Test: BCONT = 2.5V
(Others same as BCH)
–8.4
–7.9
–7.4
dB
RGH
Input: DLC1IN = –200mV
Conditions: RCONT = 2.5V RGAIN = 5V
C-level = 5V (ID = H)
Calculations: WB-R/WB-RMin.
WB-R Min. is the tested WB-R, when
tested under the same conditions as RCL.
8.6
9.2
—
dB
BGH
Input: DLC1IN = 150mV
Conditions: BCONT = 2.5V BGAIN = 5V
C-level = 5V (ID = L)
Calculations: WB-B/WB-BMin.
WB-B Min. is the tested WB-B, when
tested under the same conditions as BCL.
11.4
12.2
—
dB
WB
GAIN
RGAIN Max.
BGAIN Max.
– 15 –
CXA1391Q/R
Item
Bch
color
difference
matrix
Note 5)
Symbol
Conditions
Min.
Typ.
Max.
Unit
0.4
0.44
0.48
—
–0.24 –0.21 –0.17
—
R–G OUT/
WB-B
BMBY
Input: S1IN = 200mV S2IN = 160mV
DLC1IN = 220mV
Conditions: C-γ CONT = WB DC =
C-Slice = C-level = 5V
RCONT = 2.5V
BCONT = 4.6V (ID = L)
Calculations: B–Y OUT/WB-B
R–Y OUT/
WB-B
BMRY
Conditions: R–Y GAIN = 1.8V
Calculations: R–Y OUT/WB-B
(Others same as BMBY)
BMG
Conditions: BCONT = 4V
1. B–Y OUT is tested when B–Y
gain = 0V and taken as A. (Other
conditions are the same as BMBY)
2. B–Y OUT is tested when B–Y
gain = 5V and taken as B. (Other
conditions are the same as BMBY)
Calculations: B/A
3.0
3.3
—
—
B–Y Hue Max.
BMHH
Conditions: B–Y HUE = 1.8V
(Others same as BMBY)
Calculations: R–Y OUT/B–Y Typ.
0.58
B–Y Typ. is the value of the tested B–Y
OUT when B–Y hue=0V (Other conditions
are the same as BMBY). Note 6)
0.68
—
—
B–Y Hue Min.
BMHL
B–Y HUE = 5V
(Others same as BMHH)
–0.67 –0.58
—
GMR
Input: S1IN = 830mV S2IN = 660mV
DLC1IN = –230mV
Conditions: WB-DC = C-level = 5V
RCONT = BCONT = 2.5V
1. R–Y OUT is tested when R–Y
gain = 0V and taken as A.
2. R–Y OUT is tested when R–Y
gain = 1.8V and taken as B.
Calculations: B/A
0.81
0.85
0.89
—
GMB
Input: (The same as GMR)
Conditions:
1. B–Y OUT is tested when B–Y
gain = 0V and taken as A.
2. B–Y OUT is tested when R–Y
gain = 1.8V and taken as B.
(Others same as GMR)
Calculations: B/A
0.63
0.66
0.7
B–Y GAIN
Max.
R–Y/R–G
Gch
color
difference
matrix
Note 5)
B–Y/B–G
– 16 –
—
—
CXA1391Q/R
Item
Symbol
Min.
Typ.
Max.
Unit
0
5
15
mV
Typ.–Min.
CSLL
Input: DLY1IN = –400mV
Conditions: C-level = 5V
Y1GAIN = 1.8V
C-Slice = 1.8V (ID = H)
Calculations: C-Slice Typ. -TP
C-Slice Typ. is the TP output of
C-Slice = 0V.
Typ.–Max.
CSLH
Conditions: C-Slice =5V
(Others same as CSLL)
95
120
145
mV
C-γ CONT=0V
γTyp.
Gch-WB=400mV
Input: DLY1IN = –200mV
S1IN = S2IN = 500mV
Conditions: Y1GAIN = 1.8V
C-level is valied and
adjusted to obtain 400mV at
WB-G.
After that C-level is fixed
during test.
WB-DC is set to OPEN during C-level
adjusted and set to 5V during test.
Calculations: WB-G is tested.
450
500
550
mV
C-γ CONT=0V
γL8
Gch-WB=800mV
Input: DLY1IN = –400mV
S1IN = S2IN = 1000mV
Conditions: Same as γ Typ.
Calculations: WB-G/γ Typ.
1.13
1.2
1.25
—
C-γ CONT=0V
γL1
Gch-WB=100mV
Input: DLY1IN = –50mV
S1IN = S2IN = 125mV
(Others same as γL8)
0.36
0.4
0.44
—
C-γ CONT=1.8V
γM4
Gch-WB=400mV
Input: DLY1IN = –200mV
S1IN = S2IN = 500mV
Conditions: Cγ CONT = 1.8V
Calculations: WB-G/γ Typ.
0.9
1
1.1
—
C-γ CONT=1.8V
γM8
Gch-WB=800mV
Input: DLY1IN = –400mV
S1IN = S2IN = 1000mV
(Others same as γM4)
1.13
1.2
1.25
—
C-γ CONT=1.8V
γM1
Gch-WB=100mV
Input: DLY1IN = –50mV
S1IN = S2IN = 125mV
(Others same as γM4)
0.45
0.5
0.55
—
C-γ CONT=5V
γH4
Gch-WB=400mV
Input: DLY1IN = –200mV
S1IN = S2IN = 500mV
Conditions: Cγ CONT = 1.8V
Calculations: WB-G/γ Typ.
0.9
1
1.1
—
C-γ CONT=5V
γH8
Gch-WB=800mV
Input: DLY1IN = –400mV
S1IN = S2IN = 1000mV
(Others same as γH4)
1.13
1.2
1.25
—
C-γ CONT=5V
γH1
Gch-WB=100mV
Input: DLY1IN = –50mV
S1IN = S2IN = 125mV
(Others same as γH4)
0.26
0.3
0.35
—
C-Slice
Gch γ
curve
Conditions
– 17 –
CXA1391Q/R
Item
Symbol
Yγ1.0 (Typ.)
YγT
Yγ2.0/Yγ1.0
Min.
Typ.
Max.
Unit
Input: YHIN = 220mV
Calculations: DLYHOUT
–440
–400
–360
mV
Yγ2.0
Input: YHIN = 440mV
Calculations: DLYHOUT/YγT
1.23
1.37
1.51
—
Yγ0.5/Yγ1.0
Yγ0.5
Input: YHIN = 110mV
Calculations: DLYHOUT/YγT
0.59
0.66
0.73
—
Yγ0.5 (Max.)/
Yγ1.0
YγH
Input: YHIN = 110mV
Conditions: Yγ CONT = 1.8V
Calculations: DLYHOUT/YγT
0.64
0.71
0.78
—
Yγ0.5 (Min.)/
Yγ1.0
YγL
Input: YHIN = 110mV
Conditions: Yγ CONT = 5V
Calculations: DLYHOUT/YγT
0.54
0.6
0.66
—
TP (YH)
TPY
Input: YHIN = 220mV
Conditions: DLYHGAIN = 1.8V
Calculations: TP/DLYHOUT
–5
–4
–3
dB
TP (DLYH)
TPDY
Input: DLYHIN = YγT × 0.7
Conditions: Same as TPY
Calculations: TP/–DLYHOUT
–5
–4
–3
dB
TPG
Input: S1IN = S2IN = 500mV
DLY1IN = 200mV
Conditions: Y1GAIN = 1.8V
Calculations: TP/WB-G
–2
0
2
dB
YLG
Input: YHIN = 220mV
DLYHIN = – [YγT × –3.5dB]
Conditions: DLYHGAIN = 1.8V
Calculations: TP is tested to check that
the signal level is below
0mV in relation to black
level. Note 8)
—
—
3.5
dB
YHG
Input: YHIN = 220mV
DLYHIN = – [YγT × –12dB]
Conditions: DLYHGAIN = 5V
Calculations: TPTP is tested to check that
the signal level is over
0mV in relation to black
level. Note 8)
12
—
—
dB
Chroma level Max./Min.
GCL
Input: DLC1IN = 200mV
Conditions:
1. WB-G is tested when C-level = 5V
and taken as GC-level Min.
2. WB-G is tested when C-level = 1.8V
and taken as GC-level Max.
(Both 1 and 2 test at ID-H.)
Calculations: GC-level Max. /
GC-level Min.
1.55
1.65
1.75
—
WB DC
WDDC Test: WB-DC
1.4
1.6
2
V
Yγ
TP
TP (GWBS)
Min. Gain
YH AMP
Max. Gain
Conditions
– 18 –
Note 7)
CXA1391Q/R
Item
Conditions
Min.
Typ.
Max.
Unit
YLR
Input: S1IN = 150mV S2IN = 450mV
Conditions: C-γ CONT = WB
DC = C-Slice =
C-level = 5V
RCONT = 4.6V BCONT = 2.5V
BGAIN = 1.8V (ID = L)
Calculations: YLOUT/WB-R
0.27
0.3
0.34
—
YLB
Input: S1IN = 200mV S2IN = 160mV
DLC1IN = 220mV
Conditions: C-γ CONT = WB
DC = C-Slice =
C-level = 5V RCONT = 2.5V
BCONT = 4.6V (ID = L)
Calculations: YLOUT/WB-B
0.08
0.1
0.12
—
YLG
Input: S1IN = 830mV S2IN = 660mV
DLC1IN = –230mV
Conditions: WB-DC = C-level = 5V
RCONT = BCONT = 2.5V
Calculations: YLOUT/WB-G
0.54
0.6
0.66
—
YHOUT1 (OH mode)
YH1Z
Input: YHIN = 220mV
Calculations: YHOUT1 is tested.
900
1000
1100
mV
YHOUT1 1H/0H
YH1O
Input: DLYHIN = – (YγT × –4dB)
Conditions: DLYHGAIN = 1.8V
Calculations: YHOUT1/YH1Z Note 8)
–1
0
1
dB
YHOUT2 (0H) /YHOUT1
YH2Z
Input: YHIN = 220mV
Calculations: YHOUT2/YH1Z
–1
0
1
dB
YH2O
Input: YHIN = 220mV
Conditions: DLYHGAIN = 1.8V
Calculations: YHOUT2/YHOUT2Typ.
YHOUT2Typ. is YHOUT2 output tested at
YH2Z.
–6.5
–6
–5.5
dB
VAPT
Input: S1IN = S2IN = 125mV
Conditions: VAP GAIN = 1.8V
VAP Slice = 1.8V
Y2 GAIN = 1.8V
Calculations: VAP OUT is tested.
–250
–200
–150
mV
VS
Input: S1IN = S2IN = 1000mV
Conditions: Y2 GAIN = 1.8V
1. VAP OUT is tested when VAP
Slice=1.8V and taken as SMin.
2. VAP OUT is tested when VAP
Slice=5V and taken as SMax.
Calculations: SMax.–SMin. Note 10)
256
320
384
mV
YLOUT/
RγOUT
Symbol
YL
Note 5)
YLOUT/
BγOUT
YLOUT/
GγOUT
YHOUT2 (1H) /YHOUT1
VAP Typ.
Note 9)
VAP Slice
Note 9)
– 19 –
CXA1391Q/R
Item
Min.
Symbol
Conditions
Min.
Typ.
Max.
Unit
DY1L
Input: S1IN = S2IN = 500mV
DLY1IN = –200mV
Conditions: VAP GAIN = VAP
Slice = Y1GAIN = 1.8V
Calculations: VAP-OUT is tested to check
that the signal level is over
0mV in relation to black
level.
—
—
0
dB
DY1H
Input: S1IN = S2IN = 500mV
DLY1IN = –110mV
Conditions: VAP GAIN = VAP Slice =
1.8V
Y1GAIN = 5V
Calculations: VAP-OUT is tested to check
that the signal level is below
0mV in relation to black
level.
5
—
—
dB
—
—
0
dB
5
—
—
90
120
150
mV
—
0
0.05
—
—
—
490
mV
DLY1
gain
Note 11)
Max.
Min.
DY2L
DLY2
gain
Note 11)
Input: S1IN = S2IN = –167mV
DLY2IN = –66.7mV
Conditions: VAP GAIN = VAP
Slice = Y1GAIN = Y2GAIN = 1.8V
Calculations: VAP-OUT is tested to check
that the signal level is over
0mV in relation to black
level.
Input: S1IN = S2IN = –167mV
DLY2IN = –37.5mV
Conditions: Y2GAIN = 5V
(Others same as DY2L)
Calculations: VAP-OUT is tested to check
that the signal level is below
0mV in relation to black
level.
Max.
DY2H
VCS Typ.
VCST
VCS Min.
VCSL
VCS Max.
VCSH
Conditions: CS GAIN = 1.8V
(Others same as VCSL)
4.4
VCS Typ.
CST
Input: CS-IN = 500mV
440
CS
Note 12)
Input: S1IN = S2IN = 167mV
Conditions: Y1GAIN = Y2GAIN = 1.8V
CS GAIN = 5V
Calculations: CS OUT is tested.
Conditions: CS GAIN = 0V
(Others same as VCST)
Calculations: CS OUT/VCST
– 20 –
465
dB
CXA1391Q/R
Note 1) For pins without specific instructions regarding input, feed the DC value shown on the Test Circuit.
Calculations are mentioned utilizing the pin name or the electrical characteristics symbols. Otherwise,
for exceptional notations explanatory notes, are given with every case.
Note 2) In this item, the gain of DLC1 amplifier exclusively is calculated. CG is the gain of the system from
DLC1 IN to WB-R from which DLC1 GC amplifier gain has been excluded.
—CG calculating method—
In the actual calculation, the system on C0 side is utilized.
Input: S1IN = –62.5mV S2IN = 62.5mV
Condition: Same as DLC1H
Calculations: CG = 20log (WB-R/DLC0OUT)
Note 3) Chroma matrix operations
R = 2 [CR + αY]
G = Y – (CR + CB)
B = 2 [CB + ß (Y – C)]
α: Control with RMTX (Preset 0.167)
ß: Control with BMTX (Preset 0.22)
Note 4) With the typical gain taken when R CONT is at 4V, compare with the gain during Max. and Min. The
same for B CONT.
Note 5) Adjustment and testing is performed so that signals are output only for each of R, G, B channels
respectively.
Note 6) Comparison with B–Y OUT when R–Y HUE = 0V (HUE OFF).
The same for B–Y HUE.
Note 7) The compensation of difference in gain of YH0 andYH1 is as follows.
1) At DLYH GAIN = 1.8V, DLYH amplifier gain is 3dB.
2) Test DLYH OUT (tested at YrT) when YH IN = 220mV signal is input.
3) The difference in gain between YH0 and YH1 is compensated by inputting the signal as –3dB to
DLYH IN.
Note 8) The amplifier input is varied and the gain confirmed.
Note 9) VAP (Vertical Aperture Compensation)
Note 10) Dark slice variable volume. (Output level difference between the value slice volume at Max. and slice
volume at Min.)
Note 11) Utilizing V-APCN 2H mode, DLY1 amplifier exclusive gain is obtained through operations. However,
as the amplifier gain cannot be tested directly, only the upper and lower limits of the gain control are
checked according to the following method.
(a) Lower limit check
S1 IN = S2 IN = 500mV (At that time KNEE circuit input turns to 200mV)
DLY1 IN = –200mV (For others refer to the conditions chart)
In this condition, if we have VAP OUT ≥ 0, this indicates that DLY1 amplifier is below 0dB.
(b) Upper limit check
S1 IN = S2 IN = 500mV
DLY1 IN = –110mV (in (a) the –5dB of –200mV)
In this condition, if we have VAP OUT ≤ 0, this indicates that DLY1 amplifier is above 5dB.
Note 12) CS (Chroma Suppress)
– 21 –
CXA1391Q/R
Timing Chart for Testing
Input waveform
Differs with each test
30µ
30µ
30µ
30µ
DLYH IN
CS IN
DLC1 IN
S1
5V
tD
0V
5V
2µ
2µ
CLP2
0V
5µ
5µ
5V
2µ
CLP4
2µ
0V
15µ
15µ
Output waveform
Output signal
DLYH OUT
YH OUT1
YH OUT2
TP
VAP_OUT
B – Y OUT
R – Y OUT
CS OUT
YL OUT
WB_R
WB_G
WB_B
DLC0 OUT
DLY0 OUT
DLY1 OUT
– 22 –
S2
DLY1 IN
DLY2 IN
YH IN
10
62k
62k
27k
0.1
64
YH IN
63
Y-r CONT
62
V CC
61
LPF ADJ 3
60
LPF ADJ 2
59
LPF ADJ 1
58
GND 2
57
0.1
Y2 GAIN
56
0.1
DLY2 IN
55
DLY1 IN
54
Y1 GAIN
53
DLY1 OUT
52
DLY0 OUT
51
CLP C YO
50
S1 IN
49
S2 IN
Note 1) µF is unit of capacitor
Note 2)
indicates testing pin. (AC, DC test)
Note 3) Input pin DC value indicates input signal black level.
Note 4)
indicate relay, side, normal close.
DC 0.95V
0V
5V
5V
62k
0V
0V
DC 1.9V
DC 1.9V
1
C0
47
Y0
CLP
(CLP2)
GC
GC
LPF
48
0.1
DLCO OUT
LPF
2
r
3
YH0
0.1
4
LPF
–
3H
APCN
–
LPF
CLP
(CLP4) Y2
YH1
44
CLP
(CLP4)
LPF
45
CLP
(CLP4) Y1
Y0
GC
46
0.1
V
5
CLP
(CLP4)
42
0V
41
ID
40
0V
38
4V
WB CONTROL
39
4V
37
6
GC
LPF
7
YH1
YH0
2H
APCN
–
Y0
Y1
8
ABS
0V
9
CLP4
V-APCN
CS-Y
11
CLP2
10
GC
0V
12
36
0.1V 0.1V 0.1V
LPF
LPF
0V
CS
CS VAP MAX
C0 CLP -CB
B
LPF
(CLP2) CR
G
MATRIX
WB AMP
&
Y
C1 MPX
R
LPF
43
0.1
V
0.1
13
CLP C G
34
CLP
(CLP2)
35
0V
14
15
33
0.1
0V
16
0.1
YL MTX
0V
CLP C MPX2
Y2
Y1
KNEE
V-APCN
YH OUT 2
DLC1 IN
CLP C YH
B MTX
Y0
KNEE
TP
C1 GAIN
DLYH IN
ID
CLP V-APCN
(CLP4)
DLYH GAIN
CLP
(CLP4)
DC
3.65VCLP C DLYH
B GAIN
CLP4
CLP C MPX1
YH OUT 1
B CONT
CLP2
0V
VAP OUT
KNEE
R CONT
G ch SLICE
SLICE
CLP
GC
0.1
CLP C VAP
R GAIN
VAP GAIN
CLP C B
CS-Y CLP
(CLP4)
R MTX
DLYH OUT
R-r
CLF C R
R-WB
G-WB
B-WB
SLICE
r
R-r
G-r
B-r
B-Y
R-Y
MTX
R-Y B-Y
Hue & GC
VAP SLICE
– 23 –
CLP C CS
C LEVEL
B-r
G-r
CS IN
Test Circuit (Typ. setting)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
R-Y GAIN
B-Y GAIN
B-Y OUT
R-Y OUT
B-Y HUE
R-Y HUE
CS GAIN
CS OUT
YL OUT
GND 1
C-r CONT
WB R
WB G
WB B
WB DC
C SLICE
V
V
0V
0V
0V
0V
0V
0V
5V
0V
CXA1391Q/R
CXA1391Q/R
Standard Control Characteristics (Vcc = 5V, Ta = 25°C)
C1 GAIN control characteristics
R-MTX coefficient
3
0.3
GAIN converted into unit
GAIN
2
0.2
Preset
1
2
3
4
0.1
5
0
2
3
C1 GAIN voltage (V)
4
5
R-MTX voltage (V)
B-MTX coefficient
R GAIN control characteristics
7
0.4
6
0.3
GAIN
5
Preset
4
0.2
3
0.1 0
2
3
4
2
5
0
B-MTX voltage (V)
2
3
4
5
R GAIN voltage (V)
B GAIN control characteristics
R/B CONT control characteristics
10
3
8
1/GAIN
GAIN
2
6
1
4
2
2
3
4
2
5
3
4
R/B CONT voltage (V)
B GAIN voltage (V)
– 24 –
5
CXA1391Q/R
C-SLICE control characteristics
C-SLICE control characteristics
150
1.5
BLACK DC difference between sliced
signal and during sliced OFF
(mV)
GAIN
100
1
50
0.5
0
2
3
4
2
5
3
4
5
C-LEVEL voltage (V)
C-SLICE power supply (V)
R–Y/B–Y GAIN control characteristics
R–Y/B–Y HUE control characteristics
3
40°
30°
20°
2
GAIN
10°
0°
–10°
1
–20°
–30°
2
3
4
2
5
3
4
5
R–Y/B–Y GAIN voltage (V)
R–Y/B–Y HUE voltage (V)
Y1/Y2 GAIN control characteristics
CS GAIN control characteristics
3
400
CS output during
S1 = S2 = 125mV input
(3H_Mode)
300
(mV)
GAIN
2
200
1
100
2
3
4
5
Y1/Y2 GAIN voltage (V)
2
3
4
CS GAIN voltage (V)
– 25 –
5
CXA1391Q/R
DLYH GAIN control characteristics
VAP control characteristics
400
15
VAP_OUT output
during S1 = S2 = 250mV input
(3H_Mode)
300
GAIN (dB)
VAP OUT (mV)
10
5
200
100
0
0
2
3
4
DLYH GAIN voltage (V)
5
VAP SLICE control characteristics
(mV)
300
200
100
VAP GAIN = 0V
Diminution of VAP OUT
output level
2
3
4
VAP SLICE voltage (V)
5
– 26 –
2
3
4
VAP GAIN voltage (V)
5
CXA1391Q/R
Standard Design Data
Chroma γ curve (standardize)
1.2
γ output (standardize)
1.0
0.8
0.6
1
2
0.4
3
Standardize at typical input (400mV)
1: C – γ CONT=1.6V (Max.)
2: C – γ CONT=0V (Typ.)
1: C – γ CONT=5V (Min.)
0.2
0.2
0.4
0.6
0.8
1.0
1.2
1.4
γ input (standardize)
1.6
1.8
2.0
2.2
YH γ curve (standardize) (mV)
1.4
γ output (standardize)
1.2
1.0
0.8
0.6
1 2
0.4
3
Standardize at typical input (220mV)
1: Y – γ CONT=1.6V (Max.)
2: Y – γ CONT=0V (Typ.)
1: Y – γ CONT=5V (Min.)
0.2
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
γ input (standardize)
1.8
2.0
2.2
V-APCN Knee (standardize) (mV)
Knee output (standardize)
1.0
0.8
0.6
0.4
0.2
Standardize at typical input (S1 = S2 = 500mV)
0.2
0.4
0.6
0.8
1.0
1.2
Knee input (standardize)
– 27 –
1.4
1.6
1.8
2.0
CXA1391Q/R
Pre-Filter Adjust characteristics
DL Y0 out
S1, S2 → DL C0 out
<Cut Off> (fc: –3dB)
250
2.5
fc (MHz)
3.0
200
2.0
1.5
150
100
10k
1.0
15k
20k
25k
30k
10k
REXT [LPF ADJ1 (59PIN) ] (Ω)
15k
20k
25k
30k
REXT [LPF ADJ1 (59PIN) ] (Ω)
Chroma Adjust characteristics
<Group Delay>
S1, S2 →
R–Y out
B–Y out
800
τD (nsec)
600
400
200
10k
20k
30k
40k
50k
60k
70k
80k
60k
70k
80k
REXT [LPF ADJ2 (60PIN) ] (Ω)
<Cut Off> (fc: –3dB)
1.5
fc (MHz)
τD (nsec)
<Group Delay>
300
1.0
0.5
10k
20k
30k
40k
50k
REXT [LPF ADJ2 (60PIN) ] (Ω)
– 28 –
CXA1391Q/R
CS-VAP Adjust characteristics (S1, S2 → CS OUT)
<Group Delay>
800
τD (nsec)
600
400
10k
20k
30k
40k
50k
60k
70k
80k
60k
70k
80k
REXT [LPF ADJ2 (60 PIN) ] (Ω)
<Cut Off> (fc: –3dB)
fc (MHz)
1.5
1.0
0.5
10k
20k
30k
40k
50k
REXT [LPF ADJ2 (60 PIN) ] (Ω)
– 29 –
CXA1391Q/R
CS-Y LPF Adjust characteristics (CS IN → CS OUT)
<Group Delay>
600
τD (nsec)
400
200
10k
20k
30k
40k
50k
60k
70k
REXT [LPF ADJ2 (60 PIN) ] (Ω)
<Cut Off> (fc: –3dB)
2.0
fc (MHz)
1.5
1.0
0.5
10k
20k
30k
40k
50k
60k
REXT [LPF ADJ2 (60 PIN) ] (Ω)
VAP LPF Adjust characteristics
– 30 –
70k
80k
80k
CXA1391Q/R
VAP LPF Adjust characteristics (S1, S2 → VAP OUT)
<Group Delay>
600
τD (nsec)
400
200
10k
20k
30k
40k
50k
60k
70k
80k
REXT [LPF ADJ3 (61 PIN) ] (Ω)
<Cut Off> (fc: –3dB)
1.5
fc (MHz)
1.0
0.5
10k
20k
30k
40k
50k
REXT [LPF ADJ3 (61 PIN) ] (Ω)
– 31 –
60k
70k
80k
5V
GND 19
42 XSP1
2
1
3
XSHP
XSHD
CLP4
XSP2
XSP1
XSH1 XSH2
48 XSH2
TG
CLP1
8
9
BFG
CLP2
ID PBLK
7
6
5
LPF DL
4
10
11
HD.VD CL
12
CLP1 13
PBLK 14
WND 15
47 F1-CLP
VG-OUT 16
46 F2-CLP
IRIS-OUT 17
45 F3-CLP
IRIS-CLP 18
43 GND
44 FSHI
CS-AGCSL
5V
SG
BLK BF SYNC LALT
WND
CXA1391 Q/R
4fSC
64
LPF
IHDL
2
3
YH-IN
1
CONT
63 YGAM-
4
8
YR YG YB
CONTROLLER
FOR TITLER
CR CG CB
DL
7
6
5
9
10
11
12
LPF
14
13
15
16
17
18
19
13
14
10
11
12
R-Y 20
OUT
B-Y HUE 21
R-Y HUE 22
VCS-GAIN 23
61 LPF-ADJ3
62 V CC
YL-OUT 25
CS-OUT 24
GND 26
LPF-ADJ1
DLYH-GAIN
60 LPF-ADJ2
59
58 GND
CGAM-CONT 27
57 Y2-GAIN
DET-CLP 20
WB-R 28
41 XSP2
WB-G 29
56 DLY2-IN
IRIS-GC 22
IRIS-LEVEL 21
55 DLY1-IN
C- 32
SLICE
WB-DC 31
33
34
36 35
WB-B 30
39 V CC 1
CXA1390 Q/R
38 37
39
40
41
43 42
44
54 Y1-GAIN
5V
DETECTOR
DET- 24
OUT
V CC 2 23
40 XSP3
38 DATA-IN
YHCLP
DLYH-IN
37 PG-IN
OUT
53 DLY1-OUT
52 DLY0-
45
46
47
48
49
50
B-CLP
CS-IN
51
YOCLP
S1-IN
DLYH-OUT
G-CLP
R-Y GAIN
25
26
27
28
S2-IN
DLYH-CLP
29
DLC1-IN
YH-OUT1
CLP4
XSH1
C1-GAIN
YH-OUT2
XSHD
GY-OUT
R-MIX
DLCO-OUT
TP
XSHP
DC-OUT
MPX1-CLP
CLP4
31 30
CLP2
AGC-SEL
F2-OUT
MPX2-CLP
VAP-OUT
AGC-MAX
F3-OUT
ID
B-MTX
VAP-GAIN
AGC-CONT
CS-CLP
B-GAIN
VAP-CLP
OPIN-N
CS-CCD-SL
B-CONT
VAP-SLICE
OP-OUT
F1-OUT
OPIN-P
CS-CCD-GC
AGC-OUT
CS-OUT
AGC-CLP
DETLEVEL
CS-AGC-GC
R-CONT
R-GAIN
CS-CLP
R-CLP
B-Y GAIN
32
9
15
16
8
7
6
5
CXA1393AN/AM
17 18
19
4
3
2
1
CLP
48 B-Y
20 21
22 23
24
LPF
2
1
47 B-Y IN
46 B-LEVEL
45 CLP2
44 CLP4
43 AGND
42 YL-YH IN
41 YL-YH CLP
40 YH-IN
39 YH-CLP
38 NOISE-SLICE
37 YTBLK
5V
3
4
7
6
5
CXA1392 Q/R
5V
8
9
WC 24
VIDEO-OUT 21
SETUP- 23
CLP
V-OUT 22
25
26
10
11
12
MODE 13
CS-AGC 14
CS-Y 15
C-OUT 16
AV CC 17
C-IN 18
DGND 19
CHROMA-OUT 20
27
28
29
31 30
32
33
34
35
36
R-Y IN
33
R-Y CLP
34
4FSC
C
LEVEL
B-Y OUT
DL
DV CC
35
CLP4
LALT
36
W/B
CONTROLLER
DR-OUT
DY-OUT
NC
IHDL
DB-IN
CT-BLK DB-OUT
DR-IN
YT-BLK
SHPLEVEL
DLE
BFG
IHDL
YR-IN
GND
DY-CLP
DLD
SHP-CLP1
Y-LEVEL
NC
IHDL
YB-IN
CG-IN
SHP-CLP2
BF
CCD
YT-GC
CB-IN
DY-IN
SHP-OUT
CT-GC
CR-IN
YG-IN
FADER-MODE
HYSCONT
TH-CONT
COMP-IN
COMPOUT
– 32 –
V CC
SETUP
FADER-SIG
FSC-OUT
SYNC
SYNC-LEVEL
CBLK
CTBLK
CXA Series System Diagram
BPF
5V
C
Vid
Y
CXA1391Q/R
CXA1391Q/R
Package Outline
Unit: mm
CXA1391Q
64PIN QFP(PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
51
0.15
64
20
1
16.3
32
+ 0.4
14.0 – 0.1
52
17.9 ± 0.4
33
+ 0.2
0.1 – 0.05
0.8 ± 0.2
19
+ 0.35
2.75 – 0.15
+ 0.15
0.4 – 0.1
1.0
± 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP–64P–L01
LEAD TREATMENT
EIAJ CODE
∗ QFP064–P–1420
LEAD MATERIAL
SOLDER/PALLADIUM
PLATING
COPPER /42 ALLOY
PACKAGE WEIGHT
1.5g
JEDEC CODE
CXA1391R
64PIN LQFP (PLASTIC)
12.0 ± 0.2
∗
10.0 ± 0.1
48
33
32
64
17
(0.22)
0.5 ± 0.2
(11.0)
49
A
1
0.5 ± 0.08
+ 0.08
0.18 – 0.03
16
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0° to 10°
0.5 ± 0.2
0.1 ± 0.1
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
LQFP-64P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP064-P-1010-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.3g
JEDEC CODE
– 33 –