Si4732CY New Product Vishay Siliconix N-Channel Synchronous MOSFETs With Break-Before-Make FEATURES D D D D D D D D D D 0- to 30-V Operation Under-Voltage Lockout Shoot Through Resistant Fast Switching Times SO-16 Package Driver Impedance—3 30-V MOSFETs High Side: 0.028 VDD = 4.5 V Low Side: 0.008 VDD = 4.5 V Switching Frequency: 250 kHz to 1 MHz DESCRIPTION The Si4732CY n-channel synchronous MOSFET with break-before-make (BBM) is a high speed driver designed to operate in high frequency dc-dc switch-mode power supplies. It’s purpose is to simplify the use of n-channel MOSFETs in high frequency buck regulators. This device is designed to be used with any single output PWM IC or ASIC to produce a highly efficient, low cost, synchronous rectifier converter. The LITTLE FOOT Plust Drivers Si4732DY is packaged in Vishay-Siliconix’s high-performance SO-16 package. FUNCTIONAL BLOCK DIAGRAM BOOT VDD D1 Q1 Level Shift S1 Undervoltage Lockout D2 VDD CLK SYNC EN Q2 S2 + - VREF GND Order Number: Document Number: 71926 S-03778—Rev. C, 21-Apr-03 Si4732CY (without tape and reel) Si4732CY-T1 (with tape and reel) www.vishay.com 1 Si4732CY New Product Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED) Parameter Symbol Steady State Logic Supply VDD 7 Logic Inputs VIN -0.7 to VDD + 0.3 Drain Voltage VD1 30 VBOOT VS1 + 7 Bootstrap Voltage TA = 25rC Continuous Drain Current (TJ = 150rC)a TA = 70rC TA = 25rC TA = 70rC Maximum Power Dissipationa 4.25 A 11 ID2 8.85 PD MOSFETs V 5.3 ID1 1.2 Driver Operating Junction and Storage Temperature Range Unit W -65 to 125 Tj, Tstg _C -65 to 150 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Steady State Drain Voltage VD1 0 to 30 Logic Supply VDD 4.5 to 5.5 Input Logic High Voltage VIH 0.6 x VDD to VDD Input Logic Low Voltage Bootstrap Capacitor Ambient Temperature Unit V VIL -0.3 to 0.3 x VDD CBOOT 100 n to 1 F TA -40 to 85 _C THERMAL RESISTANCE RATINGS Parameter High-Side Junction-to-Ambienta Low-Side Junction-to-Ambienta High-Side Junction-to-Foot (Drain)b Low-Side Junction-to-Foot (Drain)b St d State Steady St t Symbol Typical Maximum RthJA1 85 105 RthJA2 68 85 RthJF1 26 33 RthJF2 16 20 Unit _C/W Notes a. Surface mounted on 1” x1” FR4 board, 0.062” thick, 2-oz copper double sided. b. Junction-to-foot thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in conjunction with the thermal impedance of the PC board pads to ambient (RthJA = RthJF + RthPCB-A). It can also be used to estimate chip temperature if power dissipation and the lead temperature of a heat carrying (drain) lead is known. www.vishay.com 2 Document Number: 71926 S-03778—Rev. C, 21-Apr-03 Si4732CY New Product Vishay Siliconix SPECIFICATIONS Test Conditions Unless Specified Parameter Symbol TA = 25_C 4.5 V < VDD <5.5 V, 4.5 V < VD1 <30 V Limits Min Typa Max Unit 5.5 V Power Supplies Logic Voltage Logic Current (Static) Logic Current (Dynamic) VDD 4.5 IDD(EN) VDD = 4.5 V, VCLK, SYNC = 4.5 V 280 500 IDD(DIS) VDD = 4.5 V, VCLK, SYNC = 0 V 220 500 IDD1(DYN) VDD = 5 V, fclk = 250 kHz 20 IDD2(DYN) VDD = 5 V, fclk = 1 MHz 70 A mA Logic Input Logic Input Voltage—High (VCLK, SYNC) VHIGH Logic Input Voltage—Low (VCLK, SYNC) VLOW 2.7 2.3 -0.3 2.25 VDD = 4.5 45V V 0.8 Protection Break-Before-Make Reference VBBM Under-Voltage Lockout VUVLO Under-Voltage Lockout Hysteresis VH VDD = 5.5 V 2.4 3.75 VDD = 4.5 45V 4 4.25 V 0.4 MOSFETs Drain-Source Voltage Drain Source On-State Drain-Source On State Resistancea Diode Forward Voltagea VDS rDS(on)1 rDS(on)2 ID = 250 A VDD = 4.5 V, ID = 10 A TA = 25_C VSD1 VSD2 IS = 2 A, A VGS = 0 V 30 V Q1 23 28 Q2 5.5 8 Q1 0.7 1.1 Q2 0.7 1.1 m V Dynamicb Driver CLK to S1/D2 Off Delay td(off) 34 60 Driver CLK to S1/D2 Fall Time tf 2.8 10 Driver CLK to S1/D2 On Delay td(on) Driver CLK to S1/D2 Rise Time tr Source-Drain Reverse Recovery Time—Q2 trr fs = 1 MHz, ID = 10 A VIN = 12 V, VOUT = 1.6 V IF 2.7 A, di/dt = 100 A/s 81 150 18.4 40 50 80 ns Notes a. Pulse test: pulse width v300 ms, duty cycle v2%. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Document Number: 71926 S-03778—Rev. C, 21-Apr-03 www.vishay.com 3 Si4732CY New Product Vishay Siliconix TIMING DIAGRAMS CLK 50% 50% CLK tf tr S1/D2 90% 90% 50% 50% 10% S1/D2 td(off) 10% td(on) SWITCHING TEST SET−UP 20 V C VDD CBOOT 5V D1 C CBOOT G1 SYNC EN S1 MOSFET Drive Circuitry with Break-Before-Make vout + CL G2 GND L D2 CLK Signal Input S1/D2 RL S2 GND GND www.vishay.com 4 Document Number: 71926 S-03778—Rev. C, 21-Apr-03 Si4732CY New Product Vishay Siliconix PIN CONFIGURATION TRUTH TABLE Sync EN CLK Q1 Q2 H H ON OFF SO-16 H L OFF ON D1 1 16 S1 L H ON OFF D1 2 15 S1 L L OFF OFF GND 3 14 CBOOT CLK 4 13 VDD SYNC EN 5 12 D2 S2 6 11 D2 S2 7 10 D2 S2 8 9 D2 PIN DESCRIPTION Pin Top View Symbol Description 1, 2 D1 3 GND High-Side MOSFET Drain Signal Ground 4 CLK Input Logic Signal 5 SYNC EN 6, 7, 8 S2 Low-Side MOSFET Source 9, 10, 11, 12 D2 Low-Side MOSFET Drain 13 VDD 14 CBOOT 15, 16 S1 Synchronous Enable Logic Supply; Decoupling to GND (with a Dap is strongly recommended) Bootstrap Capacitor for Upper MOSFET High-Side MOSFET Source APPLICATION CIRCUIT 0 V to 30 V CBOOT VDD 5V D1 Power Up Sequence: Q1 1 Ensure VDD is within spec before allowing. SYNC EN 2 CLK to be set high. Power Down Sequence: DC-DC Controller 1 Ensure CLK is low before turning. S1 MOSFET Drive Circuitry with Break-Before-Make CBOOT L VOUT D2 CLK 2 Turn VDD off. GND + CL Q2 S2 GND GND Document Number: 71926 S-03778—Rev. C, 21-Apr-03 www.vishay.com 5 Si4732CY New Product Vishay Siliconix DEVICE OPERATION The Vishay Siliconix MOSFET plus driver product is optimized for dc-dc conversion in all aspects—driver design through MOSFET optimization. The integrated packaged allows the PCB designer to ignore the MOSFET driving current loops and focus on one board layout aspect—output current loop. It also allows for simplicity when adding additional phases to a system. The MOSFET driver is designed to eliminate any shoot-through currents in the output MOSFET stage by integrating a break-before-make circuit topology. When the low-side MOSFET is to be turned on, there is an internal reference voltage, VBBM, that the S1 node needs to be below before the low-side MOSFET is turned on. When the high-side MOSFET is to be turned on, there is an optimized delay time (based on the MOSFET pair used) that will ensure that the low-side is turned off, and minimize the body diode conduction. In addition, the low impedance MOSFET drivers are optimized with the MOSFET gate impedance to help ensure an “off” state gate voltage during any shoot-through conditions when the high-side MOSFET is turned on. The MOSFETs are designed to meet a specific set of conditions to provide the best performance possible. These requirements are as follows. 1. The size of the MOSFET is selected to provide a good compromise between power dissipation and size. 2. The high-side MOSFET is designed to minimize the rDS(on)-Qg figure-of-merit and to have a low Rg for short switching times. 3. The low-side MOSFET is designed to have the optimum rDS(on), low Rg for short switching times, and low Qgd/Qgs ratio to eliminate shoot-through conditions. Switch Timing The Si4732CY has a built-in delay time that is optimized for the MOSFET pair. When the CLK signal goes low, the high-side driver will turn off, and the output will start to ramp down, tf. After a total delay, td(off) , the low-side driver turns on to provide the synchronous rectification. When the CLK goes high, the low-side driver turns off; as the body diode starts to conduct, the high-side MOSFET turns on after a total delay, td(on). The output then ramps up, tr. TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Representative Safe Operating Curve Typical Performance The following guidelines are meant to allow the designer the quickest and simplest method to working with the Vishay Siliconix MOSFET plus driver products. 2. The following chart shows experimental results based on a specific set of operating conditions. 1. The Si4732CY has a limited maximum output current capability, depending on the frequency, duty cycle and ambient temperature. The following graph shows the limitation Power Dissipation vs. Frequency IOUT vs. Operating Frequency 6 12 5 VIN = 20 V VOUT = 1.6 V VDD = 5 V 4 IOUT = 12 A Power Dissipation (W) 9 IOUT (A) TA = 25_C 6 TA = 80_C 3 3 IOUT = 8 A 2 1 VIN = 20 V VOUT = 1.6 V 0 0 0 200 400 600 800 Operating Frequency (kHz) www.vishay.com 6 1000 1200 0 250 500 750 1000 1250 Operating Frequency (kHz) Document Number: 71926 S-03778—Rev. C, 21-Apr-03 Si4732CY New Product Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Power Dissipation vs. IOUT When all of these factors are put together, a set of efficiency curves are developed as shown. This experimental result is based on a spreading copper area on the board of one and a half square inches. 4.5 VIN = 20 V VOUT = 1.6 V VDD = 5 V 4.0 Efficiency Comparison 3.0 92 2.5 90 700 kHz 2.0 88 1.5 300 kHz 1.0 0.5 0.0 0 3 6 9 12 IOUT (A) Efficiency (%) Power Dissipation (W) 3.5 86 300 kHz 84 500 kHz 82 700 kHz 80 VIN = 20 V Inductor of 0.82 H, 5050EZ 78 3. The dissipation of the heat generated by the MOSFET plus driver product is highly dependent on the board thermal impedance and the RthJF of the SO-16 package. 1000 kHz 76 4 6 8 10 12 14 IO (A) BOARD DESIGN GUIDELINES The performance characteristics shown above was done using a board that follows a suggested layout of the device and surrounding components. The basic design rules are as follows. 2. Place the output inductor close to the S1 and D2 pads. Using a large copper area around these pads help improve the thermal performance. Adding thermal vias to help dissipate the heat also improves performance. 1. Minimize the distance of the VDD capacitor to the VDD pins and ground. 3. Use a large copper area for the D1 and S2 pads. Again, using thermal vias in this area will help the thermal performance. Document Number: 71926 S-03778—Rev. C, 21-Apr-03 www.vishay.com 7 Si4732CY Vishay Siliconix New Product BOARD LAYOUT www.vishay.com 8 Top Layer Overlay Top Layer Internal Plane 1 Internal Plane 2 Bottom Layer Bottom Layer Overlay Document Number: 71926 S-03778—Rev. C, 21-Apr-03 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1