Si4724 Datasheet

Product is End of Life 12/2014
Si4724
Vishay Siliconix
N-Channel Synchronous MOSFETs With Break-Before-Make
DESCRIPTION
FEATURES
The Si4724CY N-Channel synchronous MOSFET with
break-before-make (BBM) is a high speed driver designed to
operate in high frequency DC/DC switchmode power
supplies. It’s purpose is to simplify the use of N-Channel
MOSFETs in high frequency buck regulators. This device is
designed to be used with any single output PWM IC or ASIC
to produce a highly efficient low cost synchronous rectifier
converter. A synchronous enable pin (disable = low,
enable = high) controls the synchronous function for light
load conditions.
The Si4724CY is packaged in Vishay Siliconix’s high
performance LITTLE FOOT® SO-16 package.
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0 V to 30 V operation
Driver impedance-3
Undervoltage lockout
Fast switching times
30 V MOSFETs
High side: 0.0375 at VDD = 4.5 V
Low side: 0.029 at VDD = 4.5 V
Switching frequency: 250 kHz to 1 MHz
Integrated schottky
Available
FUNCTIONAL BLOCK DIAGRAM
VDD
BOOT
D1
Q1
Level Shift
S1
Undervoltage
Lockout
D2
VDD
IN
SYNC EN
Q2
S2
+
-
VREF
GND
Document Number: 71863
S11-1185-Rev. F, 13-Jun-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4724
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Steady State
Unit
Logic Supply
VDD
7
Logic Inputs
VIN
- 0.7 to VDD + 0.3
Drain Voltage
VD1
30
V
Bootstrap Voltage
VBOOT
VS1 + 7
Synchronous pin Voltage
VSYNC
- 0.7 to VDD + 0.3
TA = 25 °C
TA = 70 °C
Continuous Drain Current
TA = 25 °C
TA = 70 °C
a
5.1
ID1
4.09
5.2
PD
Maximum Power Dissipation
Operating Junction and Storage Temperature Range
Driver
MOSFETs
A
6.5
ID2
1.2
W
- 65 to 125
TJ, Tstg
°C
- 65 to 150
Notes:
a. Surface mounted on 1" x 1" FR4 board, full copper two sides.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Steady State
Unit
Drain Voltage
VD1
0 to 30
Logic Supply
VDD
4.5 to 5.5
Input Logic High Voltage
VIH
0.7 x VDD to VDD
VIL
- 0.3 to 0.3 x VDD
Input Logic Low Voltage
Bootstrap Capacitor
Ambient Temperature
V
CBOOT
0.1 to 1
µ
TA
- 40 to 85
°C
THERMAL RESISTANCE RATINGS
Parameter
Highside
Junction-to-Ambienta
Lowside Junction-to-Ambienta
Highside Junction-to-Foot (Drain)
b
Lowside Junction-to-Foot (Drain)b
Steady State
Symbol
Typical
Maximum
RthJA1
85
105
RthJA2
68
85
RthJF1
28
35
RthJF2
19
24
Unit
°C/W
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. Junction-to-foot thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in
conjunction with the thermal impedance of the PC board pads to ambient (RthJA = RthJF + RthPCB-A). It can also be used to estimate chip temperature if power dissipation and the lead temperature of a heat carrying (drain) lead is known.
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Document Number: 71863
S11-1185-Rev. F, 13-Jun-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4724
Vishay Siliconix
SPECIFICATIONS
Parameter
Symbol
Test Conditions Unless Specified
TA = 25 °C
4.5 V < VDD < 5.5 V, 4.5 V < VD1 < 30 V
Limits
Min.
Typ.
Max.
Unit
Power Supplies
VDD
Logic Voltage
4.5
5.5
IDD(EN)
VDD = 4.5 V, VIN = 4.5 V
280
500
IDD(DIS)
VDD = 4.5 V, VIN = 0 V
220
500
High
VIH
Low
VIL
VDD = 4.5
- 40 °C ≤ TA ≤ 85 °C
Break-Before-Make Reference
VBBM
VDD = 5.5
Undervoltage Lockout
VUVLO
Logic Current
V
µA
Logic Input
Logic Input Voltage (VIN)
3.15
2.3
- 0.3
2.25
0.8
V
Protection
Undervoltage Lockout Hysteresis
VH
2.4
3.75
SYNC = 4.5
4
4.25
V
0.4
MOSFET Drivers
Driver Impedance
RDR1
RDR2
VDD = 4.5 V
Driver 1
3
Driver 2
2
V
MOSFETs
Drain-Source Voltage
Drain Source On State Resistancea
Diode Forward Voltagea
VDS
RDS(on)1
RDS(on)2
VSD1
VSD2
ID = 250 µA
30
VDD = 4.5 V, ID = 5 A
TA = 25 °C
IS = 2 A, VGS = 0
V
Q1
30
37.5
Q2
24
29
Q1
0.7
1.1
Q2
0.7
1.1
mΩ
V
Dynamicb (Unless Specified-Fs = 250 kHz, VIN = 12 V. VDD = 5 V, I = 5 A, Refer to Switching Test Setup)
Turn Off Delay
Δt
Source-Drain Reverse Recovery
Time-Q2
td(off)1
VIN to G1
28
56
td(off)2
VIN to G2
17
40
G1 to G2
16
32
G2 to G1
38
80
50
80
Δt1-2
See Timing Diagram
Δt2-1
tfrr
IF 2.7 A, di/dt = 100 A/µs
ns
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
SCHOTTKY SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter
Forward Voltage Drop
Maximum Reverse Leakage Current
Junction Capacitance
Document Number: 71863
S11-1185-Rev. F, 13-Jun-11
Symbol
VF
Irm
CT
Test Conditions
Typ
Max
IF = 1 A
Min
0.47
0.50
IF = 1 A, TJ = 125 °C
0.36
0.42
Vr = 30 V
0.004
0.100
Vr = 30 V, TJ = 100 °C
0.7
10
Vr = - 30 V, TJ = 125 °C
3
20
Vr = 10 V
50
Unit
V
mA
pF
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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4724
Vishay Siliconix
APPLICATION CIRCUIT
0 V to 30 V
Si4724
VDD
5V
CBOOT
D1
CBOOT
Q1
SYNC EN
MOSFET
Drive Circuitry
with
Break-BeforeMake
S1
VOUT
D2
+
DC-DC
Controller
IN
Q2
S2
GND
GND
GND
Power Up Sequence:
Ensure VDD is within spec before allowing IN or SYNC EN to be set high.
Power Down Sequence:
Ensure IN and SYNC EN are low before turning VDD off.
Figure 1.
PIN CONFIGURATION
TRUTH TABLE
SO-16
Sync EN
CLK
Q1
Q2
H
H
ON
OFF
H
L
OFF
ON
L
H
ON
OFF
L
L
OFF
OFF
D1
1
16
S1
D1
2
15
S1
GND
3
14
CBOOT
IN
4
13
VDD
SYNC EN
5
12
D2
Pin
Number
Symbol
S2
6
11
D2
1, 2
D1
S2
7
10
D2
3
GND
S2
8
9
D2
4
IN
PIN DESCRIPTION
5
Top View
Ordering Information: Si4724CY-T1
Si4724CY-T1-E3 (Lead (Pb)-free)
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Description
Highside MOSFET Drain
Ground
Input Logic Signal
SYNC EN Synchronous Enable
6, 7, 8
S2
Lowside MOSFET Source
9, 10, 11, 12
D2
Lowside MOSFET Drain
13
VDD
14
CBOOT
15, 16
S1
Logic Supply, decoupling to GND with
a cap is strongly recommended.
Bootstrap Capacitor for Upper
MOSFET
Highside MOSFET Source
Document Number: 71863
S11-1185-Rev. F, 13-Jun-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4724
Vishay Siliconix
TIMING DIAGRAM
IN
IN
G2
G1
G1
G2
td(off)
Δt2-1
td(off)
Δt1- 2
output
(S1/D2, not to scale)
output
(S1/D2, not to scale)
Figure 2. Δt1-2
Figure 3. Δt2-1
SWITCHING TEST SET-UP
12 V
C
CBOOT
VDD
5V
D1
C
G1
CBOOT
SYNC EN
MOSFET
Drive Circuitry
with
Break-BeforeMake
S1
G2
L
D2
S1/D2
+
CL
IN
RL
Signal Input
S2
GND
GND
GND
Figure 4.
Document Number: 71863
S11-1185-Rev. F, 13-Jun-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4724
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C unless noted)
800
80
600
60
C oss (pF)
r DS(on) - On-Resistance (MΩ)
700
ID = 5 A
40
500
400
300
200
20
100
0
0
0
2
4
6
8
10
0
6
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage (Q1)
18
24
30
Output Capacitance vs. Drain Voltage (Q1 and Q2)
1.6
16
ID = 5 A
VGS = 4.5 V
1.4
VIN = 12 V
VDD = 5 V
DC = 25 %
BOOT = 0.1 µF
ILOAD = 1 A
14
12
1.2
10
I CC (mA)
rDS(on) - On-Resistance
(Normalized)
12
VDS - Drain-to-Source Voltage (V)
1.0
0.8
8
6
4
0.6
2
0.4
- 50
0
- 25
0
25
50
75
100
125
150
0
200
400
600
800
1000
Frequency (kHz)
TA - Ambient Temperature (°C)
On-Resistance vs. Ambient Temperature
ICC vs. Frequency
350
10
300
200
I S - Source Current (A)
(A)
250
I DDQ
IDDQ at IN = H
IDDQ at IN = L
TJ = 150 °C
TJ = 25 °C
150
100
- 50
- 25
0
25
50
75
100
125
TJ - Junction Temperature (°C)
Input Current vs. Junction Temperature
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150
1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
Document Number: 71863
S11-1185-Rev. F, 13-Jun-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4724
Vishay Siliconix
50
50
40
40
30
30
Power (W)
Power (W)
TYPICAL CHARACTERISTICS (25 °C unless noted)
20
20
10
10
0
0.01
0.1
1
10
Pulse (S)
100
0
0.01
1000
1
10
Time (sec)
100
1000
Single Pulse Power, Junction-to-Ambient (Q1)
50
50
40
40
30
30
Power (W)
Power (W)
Single Pulse Power, Junction-to-Foot (Q1)
0.1
20
20
10
10
0
0.01
0.1
1
10
100
0
0.01
1000
Pulse (S)
0.1
1
10
Time (sec)
100
1000
Single Pulse Power, Junction-to-Foot (Q2)
Single Pulse Power, Junction-to-Ambient (Q2)
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = R thJA = 85 °C/W
0.02
3. T JM - TA = PDMZthJA(t)
Single Pulse
0.01
10-4
10-3
4. Surface Mounted
10-2
10-1
1
10
100
600
Square Wave Pulse Duration (sec)
Normalized Thermal Transient Impedance, Junction-to-Ambient (Q1)
Document Number: 71863
S11-1185-Rev. F, 13-Jun-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si4724
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C unless noted)
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
1
Square Wave Pulse Duration (sec)
10
100
1000
Normalized Thermal Transient Impedance, Junction-to-Foot (Q1)
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = R thJA = 68 °C/W
0.02
3. T JM - TA = PDMZthJA(t)
Single Pulse
0.01
10-4
10-3
4. Surface Mounted
10-2
10-1
1
Square Wave Pulse Duration (sec)
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient (Q2)
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
1
Square Wave Pulse Duration (sec)
10
100
1000
Normalized Thermal Transient Impedance, Junction-to-Foot (Q2)
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?71863.
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Document Number: 71863
S11-1185-Rev. F, 13-Jun-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
SOIC (NARROW):
16ĆLEAD
JEDEC Part Number: MS-012
MILLIMETERS
16
15
14
13
12
11
10
Dim
A
A1
B
C
D
E
e
H
L
Ĭ
9
E
1
2
3
4
5
6
7
8
INCHES
Min
Max
Min
Max
1.35
1.75
0.053
0.069
0.10
0.20
0.004
0.008
0.38
0.51
0.015
0.020
0.18
0.23
0.007
0.009
9.80
10.00
0.385
0.393
3.80
4.00
0.149
0.157
1.27 BSC
0.050 BSC
5.80
6.20
0.228
0.244
0.50
0.93
0.020
0.037
0_
8_
0_
8_
ECN: S-03946—Rev. F, 09-Jul-01
DWG: 5300
H
D
C
All Leads
e
Document Number: 71194
02-Jul-01
B
A1
L
Ĭ
0.101 mm
0.004 IN
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Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-16
RECOMMENDED MINIMUM PADS FOR SO-16
0.372
(9.449)
0.152
0.022
0.050
0.028
(0.559)
(1.270)
(0.711)
(3.861)
0.246
(6.248)
0.047
(1.194)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72608
Revision: 21-Jan-08
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Revision: 02-Oct-12
1
Document Number: 91000