Si4728CY Vishay Siliconix N-Channel Synchronous MOSFETs with Break-Before-Make FEATURES D D D D D D D D 4.5- to 30-V Operation Driver Impedance—3 W Undervoltage Lockout Fast Switching Times (30 ns typ.) 30-V MOSFETs High Side: 0.018 W @ VDD = 4.5 V Low Side: 0.0105 W @ VDD = 4.5 V Switching Frequency: 250 kHz to 1 MHz DESCRIPTION The Si4728CY n-channel synchronous MOSFET with break-before-make (BBM) is a high speed driver designed to operate in high frequency dc-dc switchmode power supplies. It’s purpose is to simplify the use of n-channel MOSFETs in high frequency buck regulators. This device is design to be used with any single output PWM IC or ASIC to produce a highly efficient low cost synchronous rectifier converter. A synchronous enable pin (disable = low, enable = high) controls the synchronous function for light load conditions. The Si4728CY is packaged in Vishay Siliconix’s high performance LITTLE FOOTR SO-16 package. FUNCTIONAL BLOCK DIAGRAM 4.5 V to 30 V Si4728 VDD 5V CBOOT D1 CBOOT Q1 SYNC EN DC-DC Controller MOSFET Drive Circuitry with Break-BeforeMake S1 VOUT D2 + IN GND Q2 S2 GND GND Document Number: 71286 S-03075—Rev. C, 03-Feb-03 www.vishay.com 1 Si4728CY Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED) Parameter Symbol Steady State Logic Supply VDD 7 Logic Inputs VIN - 0.7 to VDD + 0.3 Drain-Source Voltage VDS - 1.0 to 30 Bootstrap Voltage VBOOT 7 Synchronous Pin Voltage VSYNC - 0.7 to VDD +0.3 Maximum Power Dissipationa PD MOSFETs V 4 Driver Operating Junction and Storage Temperature Range Unit W - 65 to 125 Tj, Tstg _ _C - 65 to 150 Notes a. Surface mounted on 1” x1” FR4 board, full copper two sides. b. Pulse test: pulse width v300 mS, duty cycle v2%. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Steady State Drain Voltage VD1 4.5 to 30 Logic Supply VDD 4.5 to 5.5 Input Logic High Voltage VIH 0.7 VIL - 0.3 to 0.3 Input Logic Low Voltage Bootstrap Capacitor Ambient Temperature Unit V VDD to VDD VDD CBOOT 100 n to 1 m F TA - 40 to 85 _C THERMAL RESISTANCE RATINGS Symbol Typical Maximum Highside Junction-to-Ambienta Parameter RthJA1 85 105 Lowside Junction-to-Ambienta RthJA2 68 85 RthJF1 24 30 RthJF2 16 20 Highside Junction-to-Foot (Drain)b Lowside Junction-to-Foot (Drain)b Steady State Unit _ _C/W Notes a. Surface Mounted on 1” x 1” FR4 Board. b. Junction-to-foot thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in conjunction with the thermal impedance of the PC board pads to ambient (RthJA = RthJF + RthPCB-A). It can also be used to estimate chip temperature if power dissipation and the lead temperature of a heat carrying (drain) lead is known. www.vishay.com 2 Document Number: 71286 S-03075—Rev. C, 03-Feb-03 Si4728CY Vishay Siliconix SPECIFICATIONS Limits Test Conditions Unless Specified Parameter Symbol TJ = 25_C 4.5 V < VDD < 5.5 V, 4.5 V < VD1 < 30 V Min Typ Max Unit 5.5 V Power Supplies Logic Voltage VDD Logic Current 4.5 IDD(EN) VDD = 4.5 V, VIN = 4.5 V 280 500 IDD(DIS) VDD = 4.5 V, VIN = 0 V 220 500 m mA Logic Input Logic Input Voltage (VIN) High VIH Low VIL VDD = 4.5 V 3.15 2.3 - 0.3 2.25 0.8 V Protection Break-Before-Make Reference VBBM VDD = 5.5 V Undervoltage Lockout VUVLO SYNC = 4.5 V Undervoltage Lockout Hysteresis 2.4 3.75 VH 4 4.25 V 0.4 MOSFET Drivers Driver Impedance RDR1 RDR2 VDD = 4.5 V Driver 1 3.6 Driver 2 2 W MOSFETs Drain-Source Voltage Drain-Source On-State Resistancea Diode Forward Voltagea VDS rDS(on)1 rDS(on)2 VSD1 VSD2 ID = 250 mA 30 VDD = 4.5 V, ID = 10 A TJ = 25_C IS = 2 A, VGS = 0 V V Q1 13 18 Q2 8 10.5 Q1 0.7 1.1 Q2 0.7 1.1 mW W V Dynamicb (Unless Specified—Fs = 250 kHz, dc = 10%. VDD = 5 V, I = 10 A, Refer to Switching Test Setup) Rise Time Fall Time Turn-Off Delay D Dt trdr1 trdr2 tfdr1 tfdr2 10% - 90% 90% - 10% td(off)1 td(off)2 Dt1-2 See Timing Diagram Dt2-1 Driver 1 31 60 Driver 2 23 40 Driver 1 9 20 Driver 2 15 40 VIN to G1 50 100 VIN to G2 27 60 G1 to G2 19 40 G2 to G1 38 80 Rise Time tr 10% - 90% S1/D2 29 60 Fall Time tf 90% - 10% S1/D2 10 20 50 80 Source-Drain Reverse Recovery Time—Q2 tfr2 IF 2.7 A, di/dt = 100 A/ms ns Notes a. Pulse test: pulse width v300 ms; duty cycle v 2%. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Document Number: 71286 S-03075—Rev. C, 03-Feb-03 www.vishay.com 3 Si4728CY Vishay Siliconix DETAILED BLOCK DIAGRAM VDD CBOOT VDC VOUTH Q1 Level Shift VS S1 Undervoltage Lockout D2 VDD VOUTL IN SYNC EN + - Q2 VBBM GND FIGURE 1. PIN CONFIGURATION TRUTH TABLE SO-16 D1 1 16 S1 Sync EN VIN D1 2 15 S1 H H GND 3 14 CBOOT IN 4 13 VDD SYNC EN 5 12 D2 S2 6 11 D2 S2 7 10 D2 S2 8 9 D2 Q1 Q2 H ON OFF L OFF ON L H ON OFF L L OFF OFF PIN DESCRIPTION Top View Order Number: Si4728CY www.vishay.com 4 Pin Number Symbol Description 1, 2 D1 3 GND Highside MOSFET Drain 4 IN 5 SYNC EN 6, 7, 8 S2 Lowside MOSFET Source 9, 10, 11, 12 D2 Lowside MOSFET Drain 13 VDD 14 CBOOT 15, 16 S1 Ground Input Logic Signal Synchronous Enable Logic Supply Bootstrap Capacitor For Upper MOSFET Highside MOSFET Source Document Number: 71286 S-03075—Rev. C, 03-Feb-03 Si4728CY Vishay Siliconix TIMING DIAGRAM VIN VIN G1 G2 G2 G1 td(off) dt1- 2 dt2-1 td(off) output (S1/D2, not to scale) output (S1/D2, not to scale) FIGURE 2. Dt1-2 FIGURE 3. Dt2-1 SWITCHING TEST SETUP 20 V C CBOOT VDD 5V D1 C G1 CBOOT SYNC EN MOSFET Drive Circuitry with Break-BeforeMake S1 G2 L D2 S1/D2 + CL IN RL Signal Input S2 GND GND GND FIGURE 4. Document Number: 71286 S-03075—Rev. C, 03-Feb-03 www.vishay.com 5 Si4728CY Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) On-Resistance vs. Gate-to-Source Voltage (Q1) On-Resistance vs. Gate-to-Source Voltage (Q2) 80 r DS(on) - On-Resistance (M W ) r DS(on) - On-Resistance (M W ) 100 80 ID = 10 A 60 40 20 0 60 ID = 10 A 40 20 0 0 2 4 6 8 0 10 2 VGS - Gate-to-Source Voltage (V) 4 6 8 10 VGS - Gate-to-Source Voltage (V) Output Capacitance vs. Drain Voltage (Q1) Output Capacitance vs. Drain Voltage (Q2) 2000 3000 1600 C oss (pF) C oss (pF) 2400 1200 1800 800 1200 400 600 0 0 0 6 12 18 24 0 30 6 VDS - Drain-to-Source Voltage (V) On-Resistance vs. Junction Temperature 30 Input VIH vs. Junction Temperature Q2 VGS = 4.5 V ID = 10 A VDD = 4.5 V 2.30 Q1 2.25 1.2 Input V IH (V) r DS(on) - On-Resistance (W) (Normalized) 24 2.35 1.0 2.20 2.15 0.8 2.10 0.6 0.4 - 50 2.05 - 25 0 25 50 75 100 TJ - Junction Temperature (_C) www.vishay.com 6 18 VDS - Drain-to-Source Voltage (V) 1.6 1.4 12 125 150 2.00 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (_C) Document Number: 71286 S-03075—Rev. C, 03-Feb-03 Si4728CY Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Input Current vs. Junction Temperature Source-Drain Diode Forward Voltage 350 10 I S - Source Current (A) IDDQ @ IN = H 250 I DDQ ( mA) 300 200 IDDQ @ IN = L TJ = 150_C TJ = 25_C 150 100 - 50 - 25 0 25 50 75 100 125 1 0.2 150 TJ - Junction Temperature (_C) 0.4 0.6 0.7 0.8 Single Pulse Power, Junction-to-Ambient (Q1) 50 40 40 30 30 Power (W) 50 20 10 20 10 0 0.01 0.1 1 10 100 0 0.01 1000 0.1 Time (sec) 10 100 1000 Single Pulse Power, Junction-to-Ambient (Q2) 50 40 40 30 30 Power (W) 50 20 10 0 0.01 1 Time (sec) Single Pulse Power, Junction-to-Foot (Q2) Power (W) 0.5 VSD - Source-to-Drain Voltage (V) Single Pulse Power, Junction-to-Foot (Q1) Power (W) 0.3 20 10 0.1 1 10 Time (sec) Document Number: 71286 S-03075—Rev. C, 03-Feb-03 100 1000 0 0.01 0.1 1 10 100 1000 Time (sec) www.vishay.com 7 Si4728CY Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Normalized Thermal Transient Impedance, Junction-to-Ambient (Q1) 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = 0.02 t1 t2 2. Per Unit Base = RthJA = 85_C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 Square Wave Pulse Duration (sec) 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Foot (Q1) 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 10 Square Wave Pulse Duration (sec) Normalized Thermal Transient Impedance, Junction-to-Ambient (Q2) 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = RthJA = 68_C/W 0.02 3. TJM - TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 10 -4 www.vishay.com 8 10 -3 10 -2 10 -1 1 Square Wave Pulse Duration (sec) 10 100 600 Document Number: 71286 S-03075—Rev. C, 03-Feb-03 Si4728CY Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Normalized Thermal Transient Impedance, Junction-to-Foot (Q2) 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 Document Number: 71286 S-03075—Rev. C, 03-Feb-03 10 -3 10 -2 10 -1 1 10 www.vishay.com 9