PDF Data Sheet Rev. E

Single and Dual-Supply, Rail-to-Rail,
Low Cost Instrumentation Amplifier
AD623
Data Sheet
FEATURES
GENERAL DESCRIPTION
Easy to use
Rail-to-rail output swing
Input voltage range extends 150 mV below ground
(single supply)
Low power, 550 μA maximum supply current
Gain set with one external resistor
Gain range: 1 to 1000
High accuracy dc performance
0.10% gain accuracy (G = 1)
0.35% gain accuracy (G > 1)
Noise: 35 nV/√Hz RTI noise at 1 kHz
Excellent dynamic specifications
800 kHz bandwidth (G = 1)
20 μs settling time to 0.01% (G = 10)
The AD623 is an integrated, single- or dual-supply instrumentation
amplifier that delivers rail-to-rail output swing using supply
voltages from 3 V to 12 V. The AD623 offers superior user
flexibility by allowing single gain set resistor programming and by
conforming to the 8-lead industry standard pinout configuration.
With no external resistor, the AD623 is configured for unity
gain (G = 1), and with an external resistor, the AD623 can be
programmed for gains of up to 1000.
The superior accuracy of the AD623 is the result of increasing
ac common-mode rejection ratio (CMRR) coincident with
increasing gain; line noise harmonics are rejected due to
constant CMRR up to 200 Hz. The AD623 has a wide input
common-mode range and amplifies signals with commonmode voltages as low as 150 mV below ground. The AD623
maintains superior performance with dual and single polarity
power supplies.
APPLICATIONS
Low power medical instrumentation
Transducer interfaces
Thermocouple amplifiers
Industrial process controls
Difference amplifiers
Low power data acquisition
Table 1. Low Power Upgrades for the AD623
Part No.
AD8235
AD8236
AD8237
AD8226
AD8227
AD8420
AD8422
AD8426
Total VS (V dc)
5.5
5.5
5.5
36
36
36
36
36
Typical IQ (μA)
30
33
33
350
325
85
300
325 (per channel)
FUNCTIONAL BLOCK DIAGRAM
A1
–
VDIFF
2 +
VCM
–
RG
VDIFF
2 +
+IN
3
–RG
50kΩ
1
8
50kΩ
50kΩ
50kΩ
A3
6
OUTPUT
+RG
A2
4
–VS
50kΩ
50kΩ
5
REF
00778-054
–IN
+VS
7
2
Figure 1.
Rev. E
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AD623
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications Information .............................................................. 18 Applications ....................................................................................... 1 Basic Connection ....................................................................... 18 General Description ......................................................................... 1 Gain Selection ............................................................................. 18 Functional Block Diagram .............................................................. 1 Reference Terminal .................................................................... 18 Revision History ............................................................................... 2 Input and Output Offset Voltage Error ................................... 19 Specifications..................................................................................... 3 Single Supply ................................................................................. 3 Dual Supplies ................................................................................ 5 Specifications Common to Dual and Single Supplies ............. 7 Input Protection ......................................................................... 19 RF Interference ........................................................................... 19 Grounding ................................................................................... 20 Input Differential and Common-Mode Range vs.
Supply and Gain ......................................................................... 22 Absolute Maximum Ratings............................................................ 8 Additional Information ............................................................. 23 ESD Caution .................................................................................. 8 Evaluation Board ............................................................................ 24 Pin Configuration and Function Descriptions ............................. 9 General Description ................................................................... 24 Typical Performance Characteristics ........................................... 10 Outline Dimensions ....................................................................... 25 Theory of Operation ...................................................................... 17
Ordering Guide .......................................................................... 26
REVISION HISTORY
6/2016—Rev. D to Rev. E
Changes to Features Section, General Description Section,
and Figure 1 ....................................................................................... 1
Deleted Connection Diagram Section ........................................... 1
Added Functional Block Diagram Section and Table 1;
Renumbered Sequentially................................................................ 1
Changes to Single Supply Section................................................... 3
Changes to Table 3 ............................................................................ 6
Changed Both Dual and Single Supplies Section to
Specifications Common to Dual and Single Supplies Section ... 7
Changes to Table 5 ............................................................................ 8
Added Pin Configuration and Function Descriptions Section,
Figure 2, and Table 6; Renumbered Sequentially ......................... 9
Changes to Figure 5 Caption, Figure 6 Caption, and
Figure 8 Caption ............................................................................. 10
Changes to Figure 17 Caption through Figure 20 Caption ....... 11
Changes to Figure 21 Caption through Figure 26 Caption ....... 12
Changes to Figure 27 Caption and Figure 28 Caption .............. 13
Changes to Theory of Operation Section .................................... 17
Changes to Basic Connection Section ......................................... 18
Changes to Input and Output Offset Voltage Error Section, and
Input Protection Section ................................................................ 19
Added Additional Information Section....................................... 23
Added Evaluation Board Section and Figure 56 ........................ 24
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 26
7/2008—Rev. C to Rev. D
Updated Format .................................................................. Universal
Changes to Features Section and General Description Section ..1
Changes to Table 3.............................................................................6
Changes to Figure 40...................................................................... 14
Changes to Theory of Operation Section.................................... 15
Changes to Figure 42 and Figure 43............................................. 16
Changes to Table 7.......................................................................... 19
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 23
9/1999—Rev. B to Rev. C
Rev. E | Page 2 of 26
Data Sheet
AD623
SPECIFICATIONS
SINGLE SUPPLY
Typical at 25°C, single supply, +VS = 5 V, −VS = 0 V, and RL = 10 kΩ, unless otherwise noted.
Table 2.
Parameter
GAIN
Gain Range
Gain Error1
G=1
G = 10
G = 100
G = 1000
Nonlinearity
G = 1 to 1000
Gain vs. Temperature
G=1
G > 11
VOLTAGE OFFSET
Input Offset, VOSI
Over Temperature
Average Temperature
Coefficient (Tempco)
Output Offset, VOSO
Over Temperature
Average Tempco
Offset Referred to the
Input vs. Supply (PSR)
G=1
G = 10
G = 100
G = 1000
INPUT CURRENT
Input Bias Current
Over Temperature
Average Tempco
Input Offset Current
Over Temperature
Average Tempco
INPUT
Input Impedance
Differential
Common-Mode
Input Voltage Range2
Test Conditions/
Comments
G = 1 + (100 k/RG)
Min
AD623A
Typ Max
1
1000
Min
AD623ARM
Typ Max
1
1000
Min
AD623B
Typ Max
1
Unit
1000
G1 VOUT =
0.05 V to 3.5 V
G > 1 VOUT =
0.05 V to 4.5 V
0.03
0.10
0.10
0.10
0.10
0.35
0.35
0.35
0.03
0.10
0.10
0.10
0.10
0.35
0.35
0.35
0.03
0.10
0.10
0.10
0.05
0.35
0.35
0.35
%
%
%
%
G1 VOUT =
0.05 V to 3.5 V
G > 1 VOUT =
0.05 V to 4.5 V
50
50
50
ppm
5
50
10
5
50
10
5
50
10
ppm/°C
ppm/°C
25
200
350
2
200
500
650
2
25
100
160
1
μV
μV
μV/°C
1000
1500
10
500
2000
2600
10
200
500
1100
10
μV
μV
μV/°C
Total RTI error =
VOSI + VOSO/G
0.1
200
2.5
80
100
120
120
100
120
140
140
17
25
0.25
VS = 3 V to 12 V
(−VS) −
0.15
0.1
2.5
80
100
120
120
25
27.5
100
120
140
140
17
25
0.25
2
2.5
0.1
2.5
80
100
120
120
25
27.5
100
120
140
140
17
25
0.25
2
2.5
5
5
5
2||2
2||2
2||2
2||2
2||2
2||2
(+VS) −
1.5
Rev. E | Page 3 of 26
(−VS) −
0.15
(+VS) −
1.5
(−VS) −
0.15
dB
dB
dB
dB
25
27.5
2
2.5
(+VS) −
1.5
nA
nA
pA/°C
nA
nA
pA/°C
GΩ||pF
GΩ||pF
V
AD623
Parameter
Common-Mode Rejection
at 60 Hz with 1 kΩ
Source Imbalance
G=1
G = 10
G = 100
G = 1000
OUTPUT
Output Swing
DYNAMIC RESPONSE
Small Signal −3 dB BW
G=1
G = 10
G = 100
G = 1000
Slew Rate
Settling Time to 0.01%
G=1
G = 10
1
2
Data Sheet
Test Conditions/
Comments
Min
VCM = 0 V to 3 V
VCM = 0 V to 3 V
VCM = 0 V to 3 V
VCM = 0 V to 3 V
70
90
105
105
RL = 10 kΩ
0.01
RL = 100 kΩ
0.01
VS = 5 V
Step size: 3.5 V
Step size: 4 V,
VCM = 1.8 V
AD623A
Typ Max
80
100
110
110
Min
70
90
105
105
(+VS) −
0.5
(+VS) −
0.15
AD623ARM
Typ Max
80
100
110
110
0.01
77
94
105
105
(+VS) −
0.5
(+VS) −
0.15
0.01
Min
AD623B
Typ Max
86
100
110
110
0.01
dB
dB
dB
dB
(+VS) −
0.5
(+VS) −
0.15
0.01
Unit
V
V
800
100
10
2
0.3
800
100
10
2
0.3
800
100
10
2
0.3
kHz
kHz
kHz
kHz
V/μs
30
20
30
20
30
20
μs
μs
Does not include effects of external resistor, RG.
One input grounded. G = 1.
Rev. E | Page 4 of 26
Data Sheet
AD623
DUAL SUPPLIES
Typical at 25°C dual supply, VS = ±5 V, and RL = 10 kΩ, unless otherwise noted.
Table 3.
Parameter
GAIN
Gain Range
Gain Error1
G=1
G = 10
G = 100
G = 1000
Nonlinearity
G = 1 to 1000
Gain vs. Temperature
G=1
G > 11
VOLTAGE OFFSET
Input Offset, VOSI
Over Temperature
Average Tempco
Output Offset, VOSO
Over Temperature
Average Tempco
Offset Referred to the
Input vs. Supply (PSR)
G=1
G = 10
G = 100
G = 1000
INPUT CURRENT
Input Bias Current
Over Temperature
Average Tempco
Input Offset Current
Over Temperature
Average Tempco
INPUT
Input Impedance
Differential
Common-Mode
Input Voltage Range2
Test Conditions/
Comments
G = 1 + (100 k/RG)
Min
AD623A
Typ Max
1
1000
Min
AD623ARM
Typ Max
1
1000
Min
AD623B
Typ Max
1
Unit
1000
G1 VOUT =
−4.8 V to +3.5 V
G > 1 VOUT =
0.05 V to 4.5 V
0.03
0.10
0.10
0.10
0.10
0.35
0.35
0.35
0.03
0.10
0.10
0.10
0.10
0.35
0.35
0.35
0.03
0.10
0.10
0.10
0.05
0.35
0.35
0.35
%
%
%
%
G1 VOUT =
−4.8 V to +3.5 V
G > 1 VOUT =
−4.8 V to +4.5 V
50
50
50
ppm
5
50
10
5
50
10
5
50
10
ppm/°C
ppm/°C
25
200
350
2
1000
1500
10
200
500
650
2
2000
2600
10
25
100
160
1
500
1100
10
μV
μV
μV/°C
μV
μV
μV/°C
Total RTI error =
VOSI + VOSO/G
0.1
200
2.5
80
100
120
120
100
120
140
140
17
25
0.25
VS =
+2.5 V to ±6 V
(−VS) –
0.15
0.1
500
2.5
80
100
120
120
25
27.5
100
120
140
140
17
25
0.25
2
2.5
0.1
200
2.5
80
100
120
120
25
27.5
100
120
140
140
17
25
0.25
2
2.5
5
5
5
2||2
2||2
2||2
2||2
2||2
2||2
(+VS) –
1.5
Rev. E | Page 5 of 26
(−VS) –
0.15
(+VS) –
1.5
(−VS) –
0.15
dB
dB
dB
dB
25
27.5
2
2.5
(+VS) –
1.5
nA
nA
pA/°C
nA
nA
pA/°C
GΩ||pF
GΩ||pF
V
AD623
Parameter
Common-Mode Rejection
at 60 Hz with 1 kΩ
Source Imbalance
G=1
G = 10
G = 100
G = 1000
OUTPUT
Output Swing
DYNAMIC RESPONSE
Small Signal −3 dB
Bandwidth
G=1
G = 10
G = 100
G = 1000
Slew Rate
Settling Time to 0.01%
G=1
G = 10
1
2
Data Sheet
Test Conditions/
Comments
Min
AD623A
Typ Max
Min
AD623ARM
Typ Max
Min
AD623B
Typ Max
Unit
VCM =
+3.5 V to −5.15 V
VCM =
+3.5 V to −5.15 V
VCM =
+3.5 V to −5.15 V
VCM =
+3.5 V to −5.15 V
70
80
70
80
77
86
dB
90
100
90
100
94
100
dB
105
110
105
110
105
110
dB
105
110
105
110
105
110
dB
RL = 10 kΩ,
VS = ±5 V
RL = 100 kΩ
(−VS) +
0.2
(−VS) +
0.05
(+VS) −
0.5
(+VS) −
0.15
(−VS) +
0.2
(−VS) +
0.05
(+VS) −
0.5
(+VS) −
0.15
(−VS) +
0.2
(−VS) +
0.05
(+VS) −
0.5
(+VS) −
0.15
V
V
800
100
10
2
0.3
800
100
10
2
0.3
800
100
10
2
0.3
kHz
kHz
kHz
kHz
V/μs
30
20
30
20
30
20
μs
μs
VS = ±5 V, 5 V step
Does not include effects of external resistor, RG.
One input grounded. G = 1.
Rev. E | Page 6 of 26
Data Sheet
AD623
SPECIFICATIONS COMMON TO DUAL AND SINGLE SUPPLIES
Table 4.
Parameter
NOISE
Voltage Noise, 1 kHz
Test Conditions/
Comments
Min
AD623A
Typ
Max
Min
AD623ARM
Typ
Max
Min
AD623B
Typ
Max
Unit
Total RTI noise =
eni 2  2eno / G 2
Input, Voltage Noise, eni
Output, Voltage Noise, eno
RTI, 0.1 Hz to 10 Hz
G=1
G = 1000
Current Noise
0.1 Hz to 10 Hz
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
TEMPERATURE RANGE
For Specified Performance
f = 1 kHz
VIN+, VREF = 0 V
35
50
35
50
35
50
nV/√Hz
nV/√Hz
3.0
1.5
100
1.5
3.0
1.5
100
1.5
3.0
1.5
100
1.5
μV p-p
μV p-p
fA/√Hz
pA p-p
100 ±
20%
50
100 ±
20%
50
100 ±
20%
50
kΩ
−VS
60
+VS
−VS
1±
0.0002
Dual supply
Single supply
Dual supply
Single supply
±2.5
2.7
375
305
−40
60
+VS
−VS
1±
0.0002
±6
12
550
480
625
±2.5
2.7
+85
−40
Rev. E | Page 7 of 26
375
305
60
+VS
μA
V
V
±6
12
550
480
625
V
V
μA
μA
μA
+85
°C
1±
0.0002
±6
12
550
480
625
±2.5
2.7
+85
−40
375
305
AD623
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Supply Voltage
Internal Power Dissipation1
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
1
Rating
12 V
650 mW
±6 V
Indefinite
−65°C to +125°C
−40°C to +85°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Specification is for device in free air:
8-Lead PDIP Package: θJA = 95°C/W
8-Lead SOIC Package: θJA = 155°C/W
8-Lead MSOP Package: θJA = 200°C/W
Rev. E | Page 8 of 26
Data Sheet
AD623
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD623
–RG 1
+RG
7
+VS
+IN 3
6
OUTPUT
–VS 4
5
REF
–IN
TOP VIEW
(Not to Scale)
00778-001
8
2
Figure 2. AD623 Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
−RG
−IN
+IN
−VS
REF
OUTPUT
+VS
+RG
Description
Inverting Terminal of External Gain-Setting Resistor, RG.
Inverting In-Amp Input.
Noninverting In-Amp Input.
Negative Supply Terminal.
In-Amp Output Reference Input. The voltage input establishes the common-mode voltage of the output.
In-Amp Output.
Positive Supply Terminal.
Noninverting Terminal of External Gain Setting Resistor, RG.
Rev. E | Page 9 of 26
AD623
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
At 25°C, VS = ±5 V, and RL = 10 kΩ, unless otherwise noted.
300
22
280
260
20
240
18
220
16
200
14
UNITS
160
140
12
10
120
100
8
80
6
60
4
40
2
20
0
20
40
60
80
100 120 140
INPUT OFFSET VOLTAGE (µV)
0
00778-003
0
–100 –80 –60 –40 –20
–600 –500 –400 –300 –200 –100
0
00778-006
UNITS
180
100 200 300 400 500
OUTPUT OFFSET VOLTAGE (µV)
Figure 3. Typical Distribution of Input Offset Voltage,
N-8 and R-8 Package Options
Figure 6. Typical Distribution of Output Offset Voltage,
+VS = 5 V, −VS = 0 V, VREF = −0.125 V, N-8 and R-8 Package Options
480
210
420
180
360
150
120
UNITS
240
90
180
60
120
30
60
0
200
400
600
800
OUTPUT OFFSET VOLTAGE (µV)
0
–0.245 –0.240 –0.235 –0.230 –0.225 –0.220 –0.215 –0.210
INPUT OFFSET CURRENT (nA)
Figure 4. Typical Distribution of Output Offset Voltage,
N-8 and R-8 Package Options
Figure 7. Typical Distribution for Input Offset Current,
N-8 and R-8 Package Options
22
20
20
18
18
16
16
14
14
12
12
UNITS
UNITS
00778-007
–800 –600 –400 –200
00778-004
0
10
10
8
8
6
4
4
2
2
0
–80
–60
–40
–20
0
20
40
INPUT OFFSET VOLTAGE (µV)
60
80
100
00778-005
6
Figure 5. Typical Distribution of Input Offset Voltage,
+VS = 5 V, −VS = 0 V, VREF = −0.125 V, N-8 and R-8 Package Options
0
–0.025 –0.020 –0.015 –0.010 –0.005
0
0.005
INPUT OFFSET CURRENT (nA)
0.010
00778-008
UNITS
300
Figure 8. Typical Distribution for Input Offset Current,
+VS = 5 V, −VS = 0 V, VREF = −0.125 V, N-8 and R-8 Package Options
Rev. E | Page 10 of 26
Data Sheet
AD623
1600
30
1400
25
1200
20
IBIAS (nA)
UNITS
1000
800
600
15
10
400
75
80
85
90
95
0
–60
00778-009
0
100 105 110 115 120 125 130
CMRR (dB)
–40
–20
40
60
80
100
120
140
Figure 12. IBIAS vs. Temperature
1k
G=1
G= 10
G= 100
G= 1000
10
1
10
100
1k
10k
100k
FREQUENCY (Hz)
100
10
1
21
19.5
20
19.0
19
18.5
IBIAS (nA)
20.0
18
18.0
17.5
16
17.0
15
16.5
14
CMV (V)
2
4
00778-011
17
0
1k
Figure 13. Current Noise Spectral Density vs. Frequency
22
–2
100
FREQUENCY (Hz)
Figure 10. Voltage Noise Spectral Density vs. Frequency
–4
10
16.0
–4
–3
–2
–1
0
CMV (V)
Figure 14. IBIAS vs. CMV, VS = ±2.5 V
Figure 11. IBIAS vs. CMV
Rev. E | Page 11 of 26
1
2
00778-014
100
00778-013
CURRENT NOISE SPECTRAL DENSITY (fA/ Hz)
1k
00778-010
VOLTAGE NOISE SPECTRAL DENSITY (nV/ Hz RTI)
20
TEMPERATURE (°C)
Figure 9. Typical Distribution for CMRR (G = 1)
IBIAS (nA)
0
00778-012
5
200
AD623
CH1
Data Sheet
10mV
A
1s
100mV
120
VERT
110
100
G = ×1000
CMR (dB)
90
80
G = ×100
70
60
G = ×10
00778-015
50
G = ×1
40
1
10
100
1k
10k
00778-018
30
100k
FREQUENCY (Hz)
Figure 18. CMR vs. Frequency for Various Gain Settings (G)
Figure 15. 0.1 Hz to 10 Hz Current Noise (0.71 pA/DIV)
1µV/DIV
70
1s
G = 1000
60
50
G = 100
GAIN (dB)
40
30
G = 10
20
10
G=1
0
00778-016
–10
–30
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 16. 0.1 Hz to 10 Hz RTI Voltage Noise (1 DIV = 1 μV p-p)
Figure 19. Gain vs. Frequency (+VS = 5 V, −VS = 0 V), VREF = 2.5 V,
for Various Gain Settings (G)
120
5
110
4
3
100
COMMON-MODE INPUT (V)
G = ×1000
90
G = ×100
80
70
G = ×10
60
50
VS = ±2.5V
1
0
–1
–2
–3
–4
G = ×1
40
2
30
1
10
100
1k
FREQUENCY (Hz)
10k
100k
00778-017
–5
Figure 17. Common-Mode Rejection (CMR) vs. Frequency, +VS = 5 V, − VS = 0
V, VREF = 2.5 V, for Various Gain Settings (G)
Rev. E | Page 12 of 26
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
MAXIMUM OUTPUT VOLTAGE (V)
Figure 20. Maximum Output Voltage vs. Common-Mode Input,
G = 1, RL = 100 kΩ for Two Supply Voltages
00778-020
CMR (dB)
00778-019
–20
Data Sheet
AD623
5
140
4
120
VS = ±2.5V
2
POSITIVE PSSR (dB)
COMMON-MODE INPUT (V)
3
1
0
–1
–2
–3
G = 1000
100
G = 100
80
60
G = 10
40
G=1
–4
20
–4
–3
–2
–1
0
1
2
3
4
5
MAXIMUM OUTPUT VOLTAGE (V)
0
00778-021
–6
–5
1
1k
10k
100k
Figure 24. Positive PSRR vs. Frequency
5
140
120
POSITIVE PSSR (dB)
4
3
2
1
G = 1000
100
G = 100
80
60
G = 10
40
G=1
0
0
1
2
3
4
5
MAXIMUM OUTPUT VOLTAGE (V)
0
00778-022
–1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
00778-025
20
Figure 25. Positive PSRR vs. Frequency, +VS = 5V, −VS = 0 V,
for Various Gain Settings (G)
Figure 22. Maximum Output Voltage vs. Common-Mode Input,
G = 1, +VS = 5 V, −VS = 0 V, RL = 100 kΩ
140
5
G = 1000
120
4
NEGATIVE PSRR (dB)
G = 100
3
2
1
0
100
80
G = 10
60
G=1
40
20
0
1
2
3
4
5
MAXIMUM OUTPUT VOLTAGE (V)
Figure 23. Maximum Output Voltage vs. Common-Mode Input,
G ≥ 10, +VS = 5 V, −VS = 0 V, RL = 100 kΩ
00778-023
0
–1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 26. Negative PSRR vs. Frequency for Various Gain Settings (G)
Rev. E | Page 13 of 26
00778-026
COMMON-MODE INPUT (V)
100
FREQUENCY (Hz)
Figure 21. Maximum Output Voltage vs. Common-Mode Input,
G ≥ 10, RL = 100 Ω, for Two Supply Voltages
COMMON-MODE INPUT (V)
10
00778-024
–5
AD623
Data Sheet
10
500µV
1V
10µs
OUTPUT VOLTAGE (V p-p)
8
6
4
VS = ±5V
VS = ±2.5V
00778-030
2
0
40
20
60
80
00778-027
0
100
FREQUENCY (kHz)
Figure 27. Large Signal Response, G ≤ 10 for Two Supply Voltages
Figure 30. Large Signal Pulse Response and Settling Time,
G = −10 (0.250 mV = 0.01%), CL = 100 pF
10mV
2V
50µs
100
00778-031
10
1
1
10
100
1k
GAIN (V/V)
00778-028
SETTLING TIME (µs)
1k
Figure 28. Settling Time to 0.01% vs. Gain, for a 5 V Step at Output,
CL = 100 pF
1V
20µs
20mV
2V
500µs
00778-032
00778-029
500µV
Figure 31. Large Signal Pulse Response and Settling Time,
G = 100, CL = 100 pF
Figure 29. Large Signal Pulse Response and Settling Time,
G = −1 (0.250 mV = 0.01%), CL = 100 pF
Figure 32. Large Signal Pulse Response and Settling Time,
G = −1000 (5 mV = 0.01%), CL = 100 pF
Rev. E | Page 14 of 26
Data Sheet
20mV
500µs
00778-036
2µs
00778-033
Figure 33. Small Signal Pulse Response, G = 1, RL = 10 kΩ, CL = 100 pF
5µs
200µV
00778-034
20mV
Figure 36. Small Signal Pulse Response, G = 1000, RL = 10 kΩ, CL = 100 pF
1V
Figure 34. Small Signal Pulse Response, G = 10, RL = 10 kΩ, CL = 100 pF
20µV
1V
00778-038
50µs
Figure 37. Gain Nonlinearity, G = −1 (50 ppm/DIV)
00778-035
20mV
00778-037
20mV
AD623
Figure 35. Small Signal Pulse Response, G = 100, RL = 10 kΩ, CL = 100 pF
Rev. E | Page 15 of 26
Figure 38. Gain Nonlinearity, G = −10 (6 ppm/DIV)
AD623
Data Sheet
V+
1V
(V+) –0.5
(V+) –1.5
(V+) –2.5
(V–) +0.5
V–
0
0.5
1.0
1.5
OUTPUT CURRENT (mA)
Figure 40. Output Voltage Swing vs. Output Current
Figure 39. Gain Nonlinearity, G = −100, 15 ppm/DIV
Rev. E | Page 16 of 26
2.0
00778-040
00778-039
OUTPUT VOLTAGE SWING (V)
50µV
Data Sheet
AD623
THEORY OF OPERATION
The AD623 is an instrumentation amplifier based on a modified
classic 3-op-amp approach, to assure single- or dual-supply
operation even at common-mode voltages at the negative supply
rail. Low voltage offsets, input and output, as well as absolute
gain accuracy, and one external resistor to set the gain, make
the AD623 one of the most versatile instrumentation amplifiers
in its class.
The output voltage at Pin 6 is measured with respect to the
potential at Pin 5. The impedance of the reference pin is 100 kΩ;
therefore, in applications requiring voltage conversion, a small
resistor between Pin 5 and Pin 6 is all that is needed.
+VS
7
The input signal is applied to PNP transistors acting as voltage
buffers and providing a common-mode signal to the input
amplifiers (see Figure 41). An absolute value 50 kΩ resistor in
each amplifier feedback assures gain programmability.
–IN
–RG
2
1
4
–VS
50kΩ
50kΩ
50kΩ
6
RG
The differential output is
+RG
 100 kΩ 
VC
VO  1 
RG 

50kΩ
8
50kΩ
50kΩ
+VS
5
OTUPUT
REF
7
+IN
3
4
–VS
Because the amplifiers can swing to either supply rail, as well as
have their common-mode range extended to below the negative
supply rail, the range over which the AD623 can operate is further
enhanced (see Figure 20 and Figure 21).
00778-041
The differential voltage is then converted to a single-ended
voltage using the output amplifier, which also rejects any
common-mode signal at the output of the input amplifiers.
Figure 41. Simplified Schematic
Because of the voltage feedback topology of the internal op
amps, the bandwidth of the in-amp decreases with increasing
gain. At unity gain, the output amplifier limits the bandwidth.
Rev. E | Page 17 of 26
AD623
Data Sheet
APPLICATIONS INFORMATION
BASIC CONNECTION
Figure 42 and Figure 43 show the basic connection circuits for
the AD623. The +VS and −VS terminals are connected to the
power supply. The supply can be either bipolar (VS = ±2.5 V to
±6 V) or single supply (−VS = 0 V, +VS = 3.0 V to 12 V).
Capacitively decouple power supplies close to the power pins of
the device. For best results, use surface-mount 0.1 μF ceramic
chip capacitors and 10 μF electrolytic tantalum capacitors.
+VS
0.1µF
10µF
+2.5V TO +6V
VIN
RG
OUTPUT
RG REF
RG
VOUT
The input voltage, which can be either single-ended (tie either
−IN or +IN to ground) or differential, is amplified by the
programmed gain. The output signal appears as the voltage
difference between the OUTPUT pin and the externally applied
voltage on the REF input. For a ground referenced output, REF
must be grounded.
GAIN SELECTION
The gain of the AD623 is programmed by the RG resistor, or
more precisely, by whatever impedance appears between Pin 1
and Pin 8. The AD623 offers accurate gains using 0.1% to 1%
tolerance resistors. Table 7 shows the required values of RG for
the various gains. Note that for G = 1, the RG terminals are
unconnected (RG = ∞). For any arbitrary gain, RG can be
calculated by
REF (INPUT)
–VS
–2.5V TO –6V
Figure 42. Dual-Supply Basic Connection
+VS
0.1µF
10µF
+3V TO +12V
VIN
RG
RG = 100 kΩ/(G − 1)
10µF
00778-042
0.1µF
RG
OUTPUT
RG REF
VOUT
REFERENCE TERMINAL
The reference terminal potential defines the zero output voltage
and is especially useful when the load does not share a precise
ground with the rest of the system. It provides a direct means of
injecting a precise offset to the output. The reference terminal is
also useful when bipolar signals are being amplified because it
can be used to provide a virtual ground voltage. The voltage on
the reference terminal can be varied from −VS to +VS.
00778-055
REF (INPUT)
Figure 43. Single-Supply Basic Connection
Table 7. Required Values of Gain Resistors
Desired Gain
2
5
10
20
33
40
50
65
100
200
500
1000
1% Standard Table Value of RG
100 kΩ
24.9 kΩ
11 kΩ
5.23 kΩ
3.09 kΩ
2.55 kΩ
2.05 kΩ
1.58 kΩ
1.02 kΩ
499 Ω
200 Ω
100 Ω
Calculated Gain Using 1% Resistors
2
5.02
10.09
20.12
33.36
40.21
49.78
64.29
99.04
201.4
501
1001
Rev. E | Page 18 of 26
Data Sheet
AD623
INPUT AND OUTPUT OFFSET VOLTAGE ERROR
RF INTERFERENCE
The offset voltage (VOS ) of the AD623 is attributed to two
sources: those originating in the two input stages where the inamp gain is established, and those originating in the subtractor
output stage. The output error is divided by the programmed
gain when referred to the input. In practice, the input errors
dominate at high gain settings, whereas the output error
prevails when the gain is set at or near unity.
All instrumentation amplifiers can rectify high frequency outof-band signals. Once rectified, these signals appear as dc offset
errors at the output. The circuit in Figure 45 provides good RFI
suppression without reducing performance within the pass band of
the in-amp. Resistor R1 and Capacitor C1 (and likewise, R2 and
C2) form a low-pass RC filter that has a −3 dB bandwidth equal
to f = 1/(2 π R1C1). Using the component values shown, this
filter has a −3 dB bandwidth of approximately 40 kHz. The R1
and R2 resistors were selected to be large enough to isolate the
input of the circuit from the capacitors, but not large enough to
significantly increase the noise of the circuit. To preserve commonmode rejection in the pass band of the amplifier, the C1 and C2
capacitors must be 5% or better units, or low cost 20% units can
be tested and binned to provide closely matched devices.
Total Error Referred to Input (RTI)
= Input Error + (Output Error/G)
Total Error Referred to Output (RTO)
= (Input Error × G) + Output Error
The RTI offset errors and noise voltages for different gains are
listed in Table 8.
+VS
0.33µF
INPUT PROTECTION
Internal supply-referenced clamping diodes allow the input,
reference, output, and gain terminals of the AD623 to safely
withstand overvoltages of 0.3 V above or below the supplies.
This overvoltage protection is true at all gain settings and when
cycling power on and off. Overvoltage protection is particularly
important because the signal source and amplifier may be
powered separately.
If the overvoltage is expected to exceed this value, the current
through these diodes must be limited to about 10 mA using
external current limiting resistors (see Figure 44). The size of
this resistor is defined by the supply voltage and the required
overvoltage protection.
+VS
VOVER
RLIM
AD623
OUTPUT
RG
VOVER –VS + 0.7V
RLIM =
10mA
RLIM
–VS
Figure 44. Input Protection
00778-043
I = 10mA MAX
VOVER
–IN
+IN
R1
4.02kΩ
1%
0.01µF
C1
1000pF
5%
R2
C3
4.02kΩ 0.047µF
1%
C2
1000pF
5%
RG
AD623
VOUT
REFERENCE
0.33µF
0.01µF
+VS
NOTES:
1. LOCATE C1 TO C3 AS CLOSE TO THE INPUT PINS AS POSSIBLE.
00778-044
The VOS error for any given gain is calculated as follows:
Figure 45. Circuit to Attenuate RF Interference
Capacitor C3 is needed to maintain common-mode rejection at
low frequencies. R1/R2 and C1/C2 form a bridge circuit whose
output appears across the input pins of the in-amp. Any mismatch
between C1 and C2 unbalances the bridge and reduces the
common-mode rejection. C3 ensures that any RF signals are
common mode (the same on both in-amp inputs) and are not
applied differentially. This second low-pass network, R1 + R2 and
C3, has a −3 dB frequency equal to 1/(2π(R1 + R2)(C3)). Using
a C3 value of 0.047 μF, the −3 dB signal bandwidth of this circuit
is approximately 400 Hz. The typical dc offset shift over frequency
is less than 1.5 μV, and the RF signal rejection of the circuit is
better than 71 dB. The 3 dB signal bandwidth of this circuit can
be increased to 900 Hz by reducing R1 and R2 to 2.2 kΩ. The
performance is similar to using 4 kΩ resistors, except that the
circuitry preceding the in-amp must drive a lower impedance load.
Table 8. RTI Error Sources
Gain
1
2
5
10
20
50
100
1000
Maximum Total Input Offset Error (μV)
AD623A
AD623B
1200
600
700
350
400
200
300
150
250
125
220
110
210
105
200
100
Maximum Total Input Offset Drift (μV/°C)
AD623A
AD623B
12
11
7
6
4
3
3
2
2.5
1.5
2.2
1.2
2.1
1.1
2
1
Rev. E | Page 19 of 26
Total Input Referred Noise (nV/√Hz)
AD623A
AD623B
62
62
45
45
38
38
35
35
35
35
35
35
35
35
35
35
AD623
Data Sheet
The circuit in Figure 45 must be built using a printed circuit
board (PCB) with a ground plane on both sides. All component
leads must be as short as possible. The R1 and R2 resistors can
be common 1% metal film units; however, the C1 and C2
capacitors must be ±5% tolerance devices to avoid degrading
the common-mode rejection of the circuit. Either the
traditional 5% silver mica units or Panasonic ±2% PPS film
capacitors are recommended.
GROUNDING
Because the AD623 output voltage is developed with respect
to the potential on the reference terminal, many grounding
problems can be solved by simply tying the REF pin to the
appropriate local ground. The REF pin must, however, be tied
to a low impedance point for optimal CMR.
The use of ground planes is recommended to minimize the
impedance of ground returns (and hence the size of dc errors).
To isolate low level analog signals from a noisy digital environment,
many data acquisition components have separate analog and digital
ground returns (see Figure 47). All ground pins from mixed signal
components, such as analog-to-digital converters (ADCs), must
be returned through the high quality analog ground plane.
Maximum isolation between analog and digital is achieved by
connecting the ground planes back at the supplies. The digital
return currents from the ADC that flow in the analog ground
plane, in general, have a negligible effect on noise performance.
In many applications, shielded cables are used to minimize noise;
for best CMR over frequency, the shield must be properly driven.
Figure 46 shows an active guard driver that is configured to
improve ac common-mode rejection by bootstrapping the
capacitances of input cable shields, thus minimizing the
capacitance mismatch between the inputs.
+VS
–IN
AD8031
AD623
8
3
If there is only a single power supply available, it must be shared
by both digital and analog circuitry. Figure 48 shows how to
minimize interference between the digital and analog circuitry.
As in the previous case, use separate analog and digital ground
planes (reasonably thick traces can be used as an alternative to a
digital ground plane). These ground planes must be connected at
the ground pin of the power supply. Run separate traces from the
power supply to the supply pins of the digital and analog circuits.
Ideally, each device has its own power supply trace, but these can
be shared by a number of devices, as long as a single trace is not
used to route current to both digital and analog circuitry.
OUTPUT
6
5
REF
4
–VS
Figure 46. Common-Mode Shield Driver
ANALOG POWER SUPPLY
+5V
–5V
1
AD623
3
+5V
0.1µF
7
2
GND
6
VDD
4 VIN1
4
6
3
5
0.1µF
14
AGND DGND
12
ADC
AD7892-2
VIN2
AGND
VDD
MICROPROCESSOR
00778-046
0.1µF 0.1µF
DIGITAL POWER SUPPLY
GND
Figure 47. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies
POWER SUPPLY
+5V
GND
0.1µF
0.1µF
2
7
1
AD623
3
0.1µF
5
4
6
VDD
4 VIN1
6
14
AGND DGND
ADC
AD7892-2
12
AGND
Figure 48. Optimal Ground Practice in a Single-Supply Environment
Rev. E | Page 20 of 26
VDD
MICROPROCESSOR
00778-047
+IN
RG
2
7
1
00778-045
100Ω
2
RG
2
Data Sheet
AD623
Ground Returns for Input Bias Currents
Output Buffering
Input bias currents are those dc currents that must flow to bias
the input transistors of an amplifier. These are usually transistor
base currents. When amplifying floating input sources, such as
transformers or ac-coupled sources, there must be a direct dc
path into each input so that the bias current can flow. Figure 49,
Figure 50, and Figure 51 show how a bias current path can be
provided for the cases of transformer coupling, thermocouple,
and capacitive ac coupling. In dc-coupled resistive bridge
applications, providing this path is generally not necessary
because the bias current simply flows from the bridge supply
through the bridge into the amplifier. However, if the impedances
that the two inputs see are large and differ by a large amount
(>10 kΩ), the offset current of the input stage causes dc errors
proportional with the input offset voltage of the amplifier.
The AD623 is designed to drive loads of 10 kΩ or greater. If the
load is less than this value, the output of the AD623 must be
buffered with a precision single-supply op amp, such as the
OP113. This op amp can swing from 0 V to 4 V on its output
while driving a load as small as 600 Ω. Table 9 summarizes the
performance of some buffer op amps.
5V
0.1µF
VIN
RG
AD623
OP113
7
AD623
5
8
+IN
3
Op Amp
OP113
OP191
OUTPUT
6
REF
4
LOAD
–VS
TO POWER
SUPPLY
GROUND
00778-048
RG
Figure 49. Ground Returns for Bias Currents with Transformer-Coupled Inputs
+VS
Interfacing bipolar signals to single-supply ADCs presents a
challenge. The bipolar signal must be mapped into the input
range of the ADC. Figure 53 shows how this translation can be
achieved.
2
5V
7
1
5V
AD623
RG
3
5V
0.1µF
0.1µF
OTUPUT
6
5
8
+IN
Description
Single-supply, high output current
Rail-to-rail input and output, low supply current
Single-Supply Data Acquisition System
REF
4
±10mV
LOAD
–VS
TO POWER
SUPPLY
GROUND
00778-049
–IN
00778-051
Figure 52. Output Buffering
Table 9. Buffering Options
2
1
VOUT
REFERENCE
+VS
–IN
5V
0.1µF
RG
1.02kΩ
AD623
AD7776
AIN
REFERENCE
REFOUT
REFIN
00778-052
Figure 50. Ground Returns for Bias Currents with Thermocouple Inputs
+VS
7
1
AD623
RG
100kΩ
100kΩ
3
OUTPUT
6
5
8
+IN
Figure 53. A Single-Supply Data Acquisition System
2
4
–VS
REF
LOAD
TO POWER
SUPPLY
GROUND
Figure 51. Ground Returns for Bias Currents with AC-Coupled Inputs
00778-050
–IN
The bridge circuit is excited by a 5 V supply. The full-scale output
voltage from the bridge (±10 mV) therefore has a common-mode
level of 2.5 V. The AD623 removes the common-mode component
and amplifies the input signal by a factor of 100 (RGAIN = 1.02 kΩ),
which results in an output signal of ±1 V. To prevent this signal
from running into the ground rail of the AD623, the voltage on
the REF pin must be raised to at least 1 V. In this example, the 2 V
reference voltage from the AD7776 ADC biases the output voltage
of the AD623 to 2 V ± 1 V, which corresponds to the input range
of the ADC.
Rev. E | Page 21 of 26
AD623
Data Sheet
Amplifying Signals with Low Common-Mode Voltage
equations, the maximum and minimum input common-mode
voltages are given by the following equations:
Because the common-mode input range of the AD623 extends
0.1 V below ground, it is possible to measure small differential
signals which have low or no common-mode component.
Figure 54 shows a thermocouple application where one side of
the J-type thermocouple is grounded.
VCMMAX = V+ − 0.7 V − VDIFF × Gain/2
VCMMIN = V− − 0.590 V + VDIFF × Gain/2
These equations can be rearranged to give the maximum possible
differential voltage (positive or negative) for a particular commonmode voltage, gain, and power supply. Because the signals on
A1 and A2 can clip on either rail, the maximum differential
voltage is the lesser of the two equations.
5V
0.1µF
RG
1.02kΩ
J-TYPE
THERMOCOUPLE
AD623
OUTPUT
|VDIFFMAX| = 2 (V+ − 0.7 V − VCM)/Gain
REF
|VDIFFMAX| = 2 (VCM − V− +0.590 V)/Gain
00778-053
2V
Figure 54. Amplifying Bipolar Signals with Low Common-Mode Voltage
Over a temperature range of −200°C to +200°C, the J-type thermocouple delivers a voltage ranging from −7.890 mV to +10.777 mV.
A programmed gain on the AD623 of 100 (RG = 1.02 kΩ) and a
voltage on the REF pin of 2 V result in the output voltage ranging
from 1.110 V to 3.077 V relative to ground.
However, the range on the differential input voltage range is
also constrained by the output swing. Therefore, the range of
VDIFF may need to be lower according the following equation:
Input Range ≤ Available Output Swing/Gain
INPUT DIFFERENTIAL AND COMMON-MODE
RANGE vs. SUPPLY AND GAIN
For a bipolar input voltage with a common-mode voltage that is
roughly half way between the rails, VDIFFMAX is half the value that
the previous equations yield because the REF pin is at midsupply.
Note that the available output swing is given for different supply
conditions in the Specifications section.
Figure 55 shows a simplified block diagram of the AD623. The
voltages at the outputs of Amplifier A1 and Amplifier A2 are
given by
The equations can be rearranged to give the maximum gain for
a fixed set of input conditions. The maximum gain is the lesser
of the two equations.
GainMAX = 2 (V+ − 0.7 V − VCM)/VDIFF
VA2 = VCM + VDIFF/2 + 0.6 V + VDIFF × RF/RG
= VCM + 0.6 V + VDIFF × Gain/2
GainMAX = 2 (VCM − V− +0.590 V)/VDIFF
VA1 = VCM − VDIFF/2 + 0.6 V + VDIFF × RF/RG
= VCM + 0.6 V − VDIFF × Gain/2
Again, it is recommended that the resulting gain times the input
range is less than the available output swing. If this is not the case,
the maximum gain is given by
+VS
7
GainMAX = Available Output Swing/Input Range
VDIFF
2
2
4
–VS
–
1
RF
50kΩ
50kΩ
50kΩ
+
GAIN
RG
VCM
A3
8
RF
50kΩ
50kΩ
50kΩ
+VS
–
6
OUTPUT
5
REF
7
VDIFF
2 +
+IN
Also for bipolar inputs (that is, input range = 2 VDIFF), the
maximum gain is half the value yielded by the previous equations
because the REF pin must be at midsupply.
A1
A2
3
4
–VS
00778-055
–IN
Figure 55. Simplified Block Diagram
The voltages on these internal nodes are critical in determining
whether the output voltage is clipped. The VA1 and VA2 voltages
can swing from approximately 10 mV above the negative supply
(V− or ground) to within approximately 100 mV of the positive
rail before clipping occurs. Based on this and from the previous
The maximum gain and resulting output swing for different input
conditions is given in Table 10. Output voltages are referenced to
the voltage on the REF pin.
For the purposes of computation, it is necessary to break down the
input voltage into its differential and common-mode components.
Therefore, when one of the inputs is grounded or at a fixed
voltage, the common-mode voltage changes as the differential
voltage changes. Take the case of the thermocouple amplifier in
Figure 54. The inverting input on the AD623 is grounded;
therefore, when the input voltage is −10 mV, the voltage on the
noninverting input is −10 mV. For the purpose of the signal
swing calculations, this input voltage must be composed of a
common-mode voltage of −5 mV (that is, (+IN + −IN)/2) and
a differential input voltage of −10 mV (that is, +IN − −IN).
Rev. E | Page 22 of 26
Data Sheet
AD623
Table 10. Maximum Attainable Gain and Resulting Output Swing for Different Input Conditions
VCM
0V
0V
0V
0V
0V
2.5 V
2.5 V
2.5 V
1.5 V
1.5 V
0V
0V
VDIFF
±10 mV
±100 mV
±10 mV
±100 mV
±1 V
±10 mV
±100 mV
±1 V
±10 mV
±100 mV
±10 mV
±100 mV
REF Pin
2.5 V
2.5 V
0V
0V
0V
2.5 V
2.5 V
2.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Supply Voltages
+5 V
+5 V
±5 V
±5 V
±5 V
+5 V
+5 V
+5 V
+3 V
+3 V
+3 V
+3 V
Maximum Gain
118
11.8
490
49
4.9
242
24.2
2.42
142
14.2
118
11.8
Closest 1%
Gain Resistor
866 Ω
9.31 kΩ
205 Ω
2.1 kΩ
26.1 kΩ
422 Ω
4.32 kΩ
71.5 kΩ
715 Ω
7.68 kΩ
866 Ω
9.31 kΩ
Resulting Gain
116
11.7
488
48.61
4.83
238
24.1
2.4
141
14
116
11.74
Output Swing
±1.2 V
±1.1 V
±4.8 V
±4.8 V
±4.8 V
±2.3 V
±2.4 V
±2.4 V
±1.4 V
±1.4 V
±1.1 V
±1.1 V
ADDITIONAL INFORMATION
For additional information on in-amps, refer to the following:
For an updated design of the AD623, see the AD8223.
MT-061. Instrumentation Amplifier (In-Amp) Basics.
Analog Devices, Inc.
For a selection guide to all Analog Devices instrumentation
amplifiers, see the Instrumentation Amplifiers page on the
Analog Devices website at www.analog.com.
MT-070. In-Amp Input RFI Protection. Analog Devices, Inc.
Counts, Lew and Charles Kitchen. A Designer's Guide to Instrumentation Amplifiers. 3rd edition. Analog Devices, Inc., 2006.
Rev. E | Page 23 of 26
AD623
Data Sheet
EVALUATION BOARD
The EVAL-INAMP-62RZ can be used to evaluate the AD620,
AD621, AD622, AD623, AD627, AD8223, and AD8225
instrumentation amplifiers. In addition to the basic in-amp
connection, circuit options enable the user to adjust the offset
voltage, apply an output reference, or provide shield drivers
with user supplied components. The board is shipped with an
assortment of instrumentation amplifier ICs in the legacy SOIC
pinout, such as the AD620, AD621, AD622, AD623, AD8223,
and AD8225. The board also has an alternative footprint for a
through-hole, 8-lead PDIP.
Figure 56 shows a photograph of the evaluation boards for all
Analog Devices instrumentation amplifiers. For additional
information, see the EVAL-INAMP user guide (UG-261).
Rev. E | Page 24 of 26
00778-056
GENERAL DESCRIPTION
Figure 56. Evaluation Boards for Analog Devices In-Amps
Data Sheet
AD623
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
5
1
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
070606-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 57. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 58. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
Rev. E | Page 25 of 26
012407-A
4.00 (0.1574)
3.80 (0.1497)
AD623
Data Sheet
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.55
0.40
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
Figure 59. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD623ANZ
AD623AR
AD623AR-REEL7
AD623ARZ
AD623ARZ-R7
AD623ARZ-RL
AD623ARMZ
AD623ARMZ-REEL
AD623ARMZ-REEL7
AD623BNZ
AD623BRZ
AD623BRZ-R7
AD623BRZ-RL
EVAL-INAMP-62RZ
1
Temperature
Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel
8-Lead SOIC, 13" Tape and Reel
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP], 13" Tape and Reel
8-Lead Mini Small Outline Package [MSOP], 7" Tape and Reel
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel
Evaluation Board
Z = RoHS Compliant Part.
©1997–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00778-0-6/16(E)
Rev. E | Page 26 of 26
Package
Option
N-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
N-8
R-8
R-8
R-8
Branding
J0A
J0A
J0A