STM32L476xx Ultra-low-power ARM® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 1MB Flash, 128 KB SRAM, USB OTG FS, LCD, analog, audio Datasheet - production data Features • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/105/125 °C temperature range – 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 30 nA Shutdown mode (5 wakeup pins) – 120 nA Standby mode (5 wakeup pins) – 420 nA Standby mode with RTC – 1.1 µA Stop 2 mode, 1.4 µA Stop 2 with RTC – 100 µA/MHz run mode – Batch acquisition mode (BAM) – 4 µs wakeup from Stop mode – Brown out reset (BOR) in all modes except shutdown – Interconnect matrix • Core: ARM® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Clock Sources – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator for RTC (LSE) – Internal 16 MHz factory-trimmed RC (±1%) – Internal low-power 32 kHz RC (±5%) – Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy) – 3 PLLs for system clock, USB, audio, ADC • RTC with HW calendar, alarms and calibration • LCD 8 × 40 or 4 × 44 with step-up converter • Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors • 16x timers: 2x 16-bit advanced motor-control, 2x 32-bit and 5x 16-bit general purpose, 2x 16bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer • Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V September 2015 This is information on a product in full production. LQFP144 (20 × 20) LQFP100 (14 x 14) LQFP64 (10 x 10) UFBGA132 (7 × 7) WLCSP72 WLCSP81 • Memories – Up to 1 MB Flash, 2 banks read-whilewrite, proprietary code readout protection – Up to 128 KB of SRAM including 32 KB with hardware parity check – External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories – Quad SPI memory interface • 4x digital filters for sigma delta modulator • Rich analog peripherals (independent supply) – 3× 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps – 2x 12-bit DAC, low-power sample and hold – 2x operational amplifiers with built-in PGA – 2x ultra-low-power comparators • 18x communication interfaces – USB OTG 2.0 full-speed, LPM and BCD – 2x SAIs (serial audio interface) – 3x I2C FM+(1 Mbit/s), SMBus/PMBus – 6x USARTs (ISO 7816, LIN, IrDA, modem) – 3x SPIs (4x SPIs with the Quad SPI) – CAN (2.0B Active) and SDMMC interface – SWPMI single wire protocol master I/F • 14-channel DMA controller • True random number generator • CRC calculation unit, 96-bit unique ID • Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ Table 1. Device summary Reference STM32L476xx DocID025976 Rev 3 Part number STM32L476RG, STM32L476JG, STM32L476MG, STM32L476ME, STM32L476VG, STM32L476QG, STM32L476ZG, STM32L476RE, STM32L476JE, STM32L476VE, STM32L476QE, STM32L476ZE, STM32L476RC, STM32L476VC 1/229 www.st.com Contents STM32L476xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 ARM® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 16 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 19 3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.15 3.16 2/229 3.9.1 3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 36 3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 36 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DocID025976 Rev 3 STM32L476xx Contents 3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.21 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.22 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 41 3.23 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.24.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.24.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.24.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 44 3.24.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.24.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.24.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.25 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 46 3.26 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.27 Universal synchronous/asynchronous receiver transmitter (USART) . . . 48 3.28 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 48 3.29 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.30 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.31 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 50 3.32 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.33 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 51 3.34 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 51 3.35 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 52 3.36 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.37 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.37.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.37.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DocID025976 Rev 3 3/229 5 Contents 6 STM32L476xx Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.1 4/229 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 97 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 97 6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.6 Wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.3.16 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.3.17 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 148 6.3.18 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 161 6.3.19 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 165 6.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.3.21 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 6.3.24 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6.3.25 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 DocID025976 Rev 3 STM32L476xx 7 Contents 6.3.26 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.3.27 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 176 6.3.28 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 7.1 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 7.2 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 7.3 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 7.4 WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 7.5 WLCSP72 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 7.6 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 7.7.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 224 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 DocID025976 Rev 3 5/229 5 List of tables STM32L476xx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. 6/229 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32L476xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 13 Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 17 STM32L476 modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STM32L476xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 STM32L476xxSTM32L476xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Alternate function AF0 to AF7 (for AF8 to AF15 see Table 16) . . . . . . . . . . . . . . . . . . . . . 72 Alternate function AF8 to AF15 (for AF0 to AF7 see Table 15) . . . . . . . . . . . . . . . . . . . . . 79 STM32L476xx memory map and peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 98 Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 102 Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 105 Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . 107 Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . 108 Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Current consumption in Stop 1 mode with main regulator . . . . . . . . . . . . . . . . . . . . . . . . 111 Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 DocID025976 Rev 3 STM32L476xx Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. List of tables High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 184 eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 185 USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 190 Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 190 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 191 Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 192 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 193 DocID025976 Rev 3 7/229 8 List of tables Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. 8/229 STM32L476xx Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 193 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 195 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 200 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 204 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 210 LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 WLCSP81- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 WLCSP81 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 216 WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 WLCSP72 recommended PCB design rules (0.4 mm pitch BGA) . . . . . . . . . . . . . . . . . . 219 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 STM32L476xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 DocID025976 Rev 3 STM32L476xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. STM32L476xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STM32L476Zx LQFP144 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 STM32L476Qx UFBGA132 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 STM32L476Vx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 STM32L476Mx WLCSP81 ballout(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STM32L476Jx WLCSP72 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STM32L476Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 STM32L476 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 189 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 191 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 192 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 194 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 200 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 203 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 204 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 205 DocID025976 Rev 3 9/229 10 List of figures STM32L476xx Figure 49. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Figure 50. LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Figure 51. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Figure 52. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package recommended footprint210 Figure 53. UFBGA132 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Figure 54. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 212 Figure 55. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Figure 56. LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Figure 57. WLCSP81 - 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 58. WLCSP81- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Figure 59. WLCSP81 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Figure 60. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Figure 61. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package recommended footprint219 Figure 62. WLCSP72 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Figure 63. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 221 Figure 64. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Figure 65. LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Figure 66. LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 10/229 DocID025976 Rev 3 STM32L476xx 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L476xx microcontrollers. This document should be read in conjunction with the STM32L4x6 reference manual (RM0351). The reference manual is available from the STMicroelectronics website www.st.com. For information on the ARM® Cortex®-M4 core, please refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.com website. DocID025976 Rev 3 11/229 54 Description 2 STM32L476xx Description The STM32L476xx devices are the ultra-low-power microcontrollers based on the highperformance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32L476xx devices embed high-speed memories (Flash memory up to 1 Mbyte, up to 128 Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. The STM32L476xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall. The devices offer up to three fast 12-bit ADCs (5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four digital filters for external sigma delta modulators (DFSDM). In addition, up to 24 capacitive sensing channels are available. The devices also embed an integrated LCD driver 8x40 or 4x44, with internal step-up converter. They also feature standard and advanced communication interfaces. • Three I2Cs • Three SPIs • Three USARTs, two UARTs and one Low-Power UART. • Two SAIs (Serial Audio Interfaces) • One SDMMC • One CAN • One USB OTG full-speed • One SWPMI (Single Wire Protocol Master Interface) The STM32L476xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C (+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of lowpower applications. Some independent power supplies are supported: analog independent supply input for ADC, DAC, OPAMPs and comparators, 3.3 V dedicated supply input for USB and up to 14 I/Os can be supplied independently down to 1.08V. A VBAT input allows to backup the RTC and backup registers. The STM32L476xx family offers six packages from 64-pin to 144-pin packages. 12/229 DocID025976 Rev 3 STM32L476xx Description Table 2. STM32L476xx family device features and peripheral counts Peripheral Flash memory STM32L476 STM32L476 Zx Qx 512KB 1MB 512KB 1MB STM32L476 Vx 256KB 512KB STM32L476 STM32L476 Mx Jx 1MB SRAM Yes Yes(1) Yes No Quad SPI 512KB 1MB 256KB 512KB 1MB No No Yes Advanced control 2 (16-bit) General purpose 5 (16-bit) 2 (32-bit) Basic 2 (16-bit) Low -power 2 (16-bit) SysTick timer 1 Watchdog timers (independent, window) 2 SPI 3 2 Comm. interfaces 1MB 128KB External memory controller for static memories Timers 512KB STM32L476 Rx I C 3 USART UART LPUART 3 2 1 SAI 2 CAN 1 USB OTG FS Yes SDMMC Yes SWPMI Yes Digital filters for sigma-delta modulators Yes (4 filters) Number of channels 8 RTC Yes Tamper pins LCD COM x SEG 3 Yes 8x40 or 4x44 Yes 8x40 or 4x44 Yes 8x40 or 4x44 Random generator 2 2 2 Yes 8x30 or 4x32 Yes 8x28 or 4x32 Yes 8x28 or 4x32 Yes GPIOs Wakeup pins Nb of I/Os down to 1.08 V 114 5 14 109 5 14 82 5 0 65 4 6 57 4 6 51 4 0 Capacitive sensing Number of channels 24 24 21 12 12 12 12-bit ADCs Number of channels 3 24 3 19 3 16 3 16 3 16 3 16 12-bit DAC channels Internal voltage reference buffer 2 Yes No Analog comparator 2 Operational amplifiers 2 DocID025976 Rev 3 13/229 54 Description STM32L476xx Table 2. STM32L476xx family device features and peripheral counts (continued) Peripheral STM32L476 STM32L476 Zx Qx STM32L476 Vx Max. CPU frequency STM32L476 Rx 80 MHz Operating voltage 1.71 to 3.6 V Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C Operating temperature Packages STM32L476 STM32L476 Mx Jx LQFP144 UFBGA132 LQFP100 WLCSP81 WLCSP72 LQFP64 1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. 14/229 DocID025976 Rev 3 STM32L476xx Description Figure 1. STM32L476xx block diagram -7&.6:&/. -7$*6: 038 (70 19,& -7'26:'-7'2 &/.1(>@1/1%/>@ $>@'>@12(1:( 1:$,71&(,17DV$) )OH[LEOHVWDWLFPHPRU\FRQWUROOHU)60& 65$0365$0125)ODVK 1$1')ODVK 1-7567-7', 75$&(&/. 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DocID025976 Rev 3 15/229 54 Functional overview STM32L476xx 3 Functional overview 3.1 ARM® Cortex®-M4 core with FPU The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM® Cortex®-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation. With its embedded ARM core, the STM32L476xx family is compatible with all ARM tools and software. Figure 1 shows the general block diagram of the STM32L476xx family devices. 3.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex®-M4 processors. It balances the inherent performance advantage of the ARM® Cortex®-M4 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor near 100 DMIPS performance at 80MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 16/229 DocID025976 Rev 3 STM32L476xx 3.4 Functional overview Embedded Flash memory STM32L476xx devices feature up to 1 Mbyte of embedded Flash memory available for storing programs and data. The Flash memory is divided into two banks allowing readwhile-write operations. This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. The dual bank boot is also supported. Each bank contains 256 pages of 2 Kbyte. Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: memory readout protection: the Flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected – Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible. Table 3. Access status versus readout protection level and execution modes Area Debug, boot from RAM or boot from system memory (loader) User execution Protection level Read Write Erase Read Write Erase Main memory 1 Yes Yes Yes No No No 2 Yes Yes Yes N/A N/A N/A System memory 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A Option bytes 1 Yes Yes Yes Yes Yes Yes 2 Yes No No N/A N/A N/A No No N/A(1) Backup registers SRAM2 N/A (1) 1 Yes Yes 2 Yes Yes N/A N/A N/A N/A 1 Yes Yes Yes(1) No No No(1) 2 Yes Yes Yes N/A N/A N/A 1. Erased when RDP change from Level 1 to Level 0. • Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity. • Proprietary code readout protection (PCROP): a part of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. One area per bank can be selected, with 64-bit granularity. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. DocID025976 Rev 3 17/229 54 Functional overview STM32L476xx The whole non-volatile memory embeds the error correction code (ECC) feature supporting: 3.5 • single error detection and correction • double error detection. • The address of the ECC fail can be read in the ECC register Embedded SRAM STM32L476xx devices feature up to 128 Kbyte of embedded SRAM. This SRAM is split into two blocks: • 96 Kbyte mapped at address 0x2000 0000 (SRAM1) • 32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2). This block is accessed through the ICode/DCode buses for maximum performance. These 32 Kbyte SRAM can also be retained in Standby mode. The SRAM2 can be write-protected with 1 Kbyte granularity. The memory can be accessed in read/write at CPU clock speed with 0 wait states. 3.6 Firewall The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas. Each illegal access generates a reset which kills immediately the detected intrusion. The Firewall main features are the following: • • Three segments can be protected and defined thanks to the Firewall registers: – Code segment (located in Flash or SRAM1 if defined as executable protected area) – Non-volatile data segment (located in Flash) – Volatile data segment (located in SRAM1) The start address and the length of each segments are configurable: – code segment: up to 1024 Kbyte with granularity of 256 bytes – Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes – Volatile data segment: up to 96 Kbyte with a granularity of 64 bytes • Specific mechanism implemented to open the Firewall to get access to the protected areas (call gate entry sequence) • Volatile data segment can be shared or not with the non-protected code • Volatile data segment can be executed or not depending on the Firewall configuration The Flash readout protection must be set to level 2 in order to reach the expected level of protection. 18/229 DocID025976 Rev 3 STM32L476xx 3.7 Functional overview Boot modes At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, CAN and USB OTG FS in Device mode through DFU (device firmware upgrade). 3.8 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.9 Power supply management 3.9.1 Power supply schemes • VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins. • VDDA = 1.62 V (ADCs/COMPs) / 1.8 (DACs/OPAMPs) to 3.6 V: external analog power supply for ADCs, DACs, OPAMPs, Comparators and Voltage reference buffer. The VDDA voltage level is independent from the VDD voltage. • VDDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers. The VDDUSB voltage level is independent from the VDD voltage. • VDDIO2 = 1.08 to 3.6 V: external power supply for 14 I/Os (PG[15:2]). The VDDIO2 voltage level is independent from the VDD voltage. • VLCD = 2.5 to 3.6 V: the LCD controller can be powered either externally through VLCD pin, or internally from an internal voltage generated by the embedded step-up converter. • VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Note: When the functions supplied by VDDA, VDDUSB or VDDIO2 are not used, these supplies should preferably be shorted to VDD. Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V tolerant (refer to Table 18: Voltage characteristics). Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1 or VDDIO2, with VDDIO1 = VDD. VDDIO2 supply voltage level is independent from VDDIO1. DocID025976 Rev 3 19/229 54 Functional overview STM32L476xx Figure 2. Power supply overview 9''$GRPDLQ [$'FRQYHUWHUV [FRPSDUDWRUV ['$FRQYHUWHUV [RSHUDWLRQDODPSOLILHUV 9''$ 966$ 9ROWDJHUHIHUHQFHEXIIHU 9/&' /&' 9''86% 966 86%WUDQVFHLYHUV 9'',2GRPDLQ 9'',2 9'',2 966 ,2ULQJ 3*>@ 9''GRPDLQ 9'',2 ,2ULQJ 9&25(GRPDLQ 5HVHWEORFN 7HPSVHQVRU [3//+6,06, 6WDQGE\FLUFXLWU\ :DNHXSORJLF ,:'* 966 9'' 9ROWDJHUHJXODWRU /RZYROWDJHGHWHFWRU &RUH 9&25( 65$0 65$0 'LJLWDO SHULSKHUDOV )ODVKPHPRU\ %DFNXSGRPDLQ /6(FU\VWDO.RVF %.3UHJLVWHUV 5&&%'&5UHJLVWHU 57& 9%$7 069 3.9.2 Power supply supervisor The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down. The device remains in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. In addition, the devices embeds a Peripheral Voltage Monitor which compares the independent supply voltages VDDA, VDDUSB, VDDIO2 with a fixed threshold in order to ensure that the peripheral is in its functional supply range. 20/229 DocID025976 Rev 3 STM32L476xx 3.9.3 Functional overview Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 32 Kbyte SRAM2 in Standby with RAM2 retention. • Both regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. The ultralow-power STM32L476xx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the Main Regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency. There are two power consumption ranges: • Range 1 with the CPU running at up to 80 MHz. • Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also limited to 26 MHz. The VCORE can be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode. • 3.9.4 Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by HSI16. Low-power modes The ultra-low-power STM32L476xx supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources: DocID025976 Rev 3 21/229 54 Mode Run LPRun Sleep LPSleep Regulator (1) Range 1 Range2 LPR Range 1 Range 2 LPR Flash SRAM Clocks Yes ON(4) ON Any Yes ON(4) ON Any except PLL No ON(4) ON(5) Any No ON(4) ON(5) Any except PLL All except OTG_FS, RNG LSE LSI BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1,2) DACx (x=1,2) OPAMPx (x=1,2) USARTx (x=1...5)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) *** All other peripherals are frozen. DocID025976 Rev 3 Stop 1 LPR DMA & Peripherals(2) CPU No Off ON All All except OTG_FS, RNG Wakeup source N/A Consumption(3) 112 µA/MHz 100 µA/MHz Wakeup time N/A All except OTG_FS, RNG N/A 136 µA/MHz to Range 1: 4 µs to Range 2: 64 µs All Any interrupt or event 37 µA/MHz 6 cycles 35 µA/MHz 6 cycles Any interrupt or event 40 µA/MHz 6 cycles Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) USARTx (x=1...5)(6) LPUART1(6) I2Cx (x=1...3)(7) LPTIMx (x=1,2) OTG_FS(8) SWPMI1(9) 6.6 µA w/o RTC 6.9 µA w RTC 4 µs in SRAM 6 µs in Flash All except OTG_FS, RNG Functional overview 22/229 Table 4. STM32L476 modes overview STM32L476xx Mode Stop 2 Regulator (1) LPR CPU No Flash Off DocID025976 Rev 3 OFF Shutdown OFF ON Clocks DMA & Peripherals(2) Wakeup source Consumption(3) LSE LSI BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) I2C3(7) LPUART1(6) LPTIM1 *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) I2C3(7) LPUART1(6) LPTIM1 1.1 µA w/o RTC 1.4 µA w/RTC LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pull-down Reset pin 5 I/Os (WKUPx)(10) BOR, RTC, IWDG LSE RTC *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pull-down(11) Reset pin 5 I/Os (WKUPx)(10) RTC SRAM2 ON LPR Standby SRAM Powered Off Powered Off Off Off Powered Off Powered Off Wakeup time STM32L476xx Table 4. STM32L476 modes overview (continued) 5 µs in SRAM 7 µs in Flash 0.35 µA w/o RTC 0.65 µA w/ RTC 14 µs 0.12 µA w/o RTC 0.42 µA w/ RTC 0.03 µA w/o RTC 0.33 µA w/ RTC 256 µs 1. LPR means Main regulator is OFF and Low-power regulator is ON. 3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in LPRun/LPSleep. 4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM. 5. The SRAM1 and SRAM2 clocks can be gated on or off independently. 6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 23/229 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. Functional overview 2. All peripherals can be active or clock gated to save power consumption. 9. SWPMI1 wakeup by resume from suspend. 10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. Functional overview 24/229 8. OTG_FS wakeup by resume from suspend and attach detection protocol event. DocID025976 Rev 3 STM32L476xx STM32L476xx Functional overview By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. • Low-power sleep mode This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the lowpower run mode. • Stop 1 and Stop 2 modes Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition. Two Stop modes are available: Stop 1 and Stop 2 modes. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode. Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. The system clock when exiting from Stop1 or Stop2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration. • Standby mode The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The brown-out reset (BOR) always remains active in Standby mode. The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating. After entering Standby mode, SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in DocID025976 Rev 3 25/229 54 Functional overview STM32L476xx Standby mode, supplied by the low-power Regulator (Standby with RAM2 retention mode). The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE). The system clock after wakeup is MSI up to 8 MHz. • Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported. SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain. The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper). The system clock after wakeup is MSI at 4 MHz. 26/229 DocID025976 Rev 3 STM32L476xx Functional overview Table 5. Functionalities depending on the working mode(1) - - - Y - Y - - - - - - - - - - O(2) O(2) O(2) O(2) - - - - - - - - - SRAM1 (up to 96 KB) Y Y(3) Y Y(3) Y - Y - - - - - - SRAM2 (32 KB) Y Y(3) Y Y(3) Y - Y - O(4) - - - - FSMC O O O O - - - - - - - - - Quad SPI O O O O - - - - - - - - - Backup Registers Y Y Y Y Y - Y - Y - Y - Y Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - - Programmable Voltage Detector (PVD) O O O O O O O O - - - - - Peripheral Voltage Monitor (PVMx; x=1,2,3,4) O O O O O O O O - - - - - DMA O O O O - - - - - - - - - High Speed Internal (HSI16) O O O O (5) - (5) - - - - - - High Speed External (HSE) O O O O - - - - - - - - - Low Speed Internal (LSI) O O O O O - O - O - - - - Low Speed External (LSE) O O O O O - O - O - O - O Multi-Speed Internal (MSI) O O O O - - - - - - - - - Clock Security System (CSS) O O O O - - - - - - - - - Clock Security System on LSE O O O O O O O O O O - - - RTC / Auto wakeup O O O O O O O O O O O O O Number of RTC Tamper pins 3 3 3 3 3 O 3 O 3 O 3 O 3 Peripheral CPU Flash memory (up to 1 MB) Run Sleep Lowpower run Lowpower sleep - DocID025976 Rev 3 Wakeup capability Shutdown Wakeup capability Standby Wakeup capability Stop 2 Wakeup capability Stop 1 VBAT 27/229 54 Functional overview STM32L476xx Table 5. Functionalities depending on the working mode(1) (continued) O (8) O O (8) Lowpower run Lowpower sleep - O O O - - - - O O O - Wakeup capability USB OTG FS O Sleep - O - - - - - Shutdown Wakeup capability LCD Run Standby Wakeup capability Peripheral Stop 2 Wakeup capability Stop 1 - - - - - - - - - - - - - - VBAT USARTx (x=1,2,3,4,5) O O O O O(6) O(6) Low-power UART (LPUART) O O O O O(6) O(6) O(6) O(6) - - - - - I2Cx (x=1,2) O O O O O(7) O(7) (7) - - - - - - - O(7) O(7) O(7) - - - - - I2C3 O O O O O SPIx (x=1,2,3) O O O O - - - - - - - - - CAN O O O O - - - - - - - - - SDMMC1 O O O O - - - - - - - - - SWPMI1 O O O O - O - - - - - - - SAIx (x=1,2) O O O O - - - - - - - - - DFSDM O O O O - - - - - - - - - ADCx (x=1,2,3) O O O O - - - - - - - - - DACx (x=1,2) O O O O O - - - - - - - - VREFBUF O O O O O - - - - - - - - OPAMPx (x=1,2) O O O O O - - - - - - - - COMPx (x=1,2) O O O O O O O O - - - - - Temperature sensor O O O O - - - - - - - - - Timers (TIMx) O O O O - - - - - - - - - Low-power timer 1 (LPTIM1) O O O O O O O O - - - - - Low-power timer 2 (LPTIM2) O O O O O O - - - - - - - Independent watchdog (IWDG) O O O O O O O O O O - - - Window watchdog (WWDG) O O O O - - - - - - - - - SysTick timer O O O O - - - - - - - - - Touch sensing controller (TSC) O O O O - - - - - - - - - 28/229 DocID025976 Rev 3 STM32L476xx Functional overview Table 5. Functionalities depending on the working mode(1) (continued) - - - Random number generator (RNG) O(8) O(8) - - - - - - - - - - - CRC calculation unit O O O O - - - - - - - - - GPIOs O O O O O O O O (9) 5 pins (11) 5 pins - Peripheral Run Sleep Lowpower run Lowpower sleep - (10) Wakeup capability Shutdown Wakeup capability Standby Wakeup capability Stop 2 Wakeup capability Stop 1 VBAT (10) 1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. 2. The Flash can be configured in power-down mode. By default, it is not in power-down mode. 3. The SRAM clock can be gated on or off. 4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register. 5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore. 6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 8. Voltage scaling Range 1 only. 9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. 3.9.5 Reset mode In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal. 3.9.6 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. The VBAT pin supplies the RTC with LSE and the backup registers. Three antitamper detection pins are available in VBAT mode. VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. DocID025976 Rev 3 29/229 54 Functional overview 3.10 STM32L476xx Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 1 and Stop 2 modes. Run Sleep Low-power run Low-power sleep Stop 1 Stop 2 Table 6. STM32L476xx peripherals interconnect matrix TIMx Timers synchronization or chaining Y Y Y Y - - ADCx DACx DFSDM Conversion triggers Y Y Y Y - - DMA Memory to memory transfer trigger Y Y Y Y - - COMPx Comparator output blanking Y Y Y Y - - TIM1, 8 TIM2, 3 Timer input channel, trigger, break from analog signals comparison Y Y Y Y - - LPTIMERx Low-power timer triggered by analog signals comparison Y Y Y Y Y (1) TIM1, 8 Timer triggered by analog watchdog Y Y Y Y - - TIM16 Timer input channel from RTC events Y Y Y Y - - LPTIMERx Low-power timer triggered by RTC alarms or tampers Y Y Y Y Y (1) All clocks sources (internal TIM2 and external) TIM15, 16, 17 Clock source used as input channel for RC measurement and trimming Y Y Y Y - - USB Timer triggered by USB SOF Y Y - - - - Timer break Y Y Y Y - - Interconnect source TIMx COMPx ADCx RTC Interconnect destination TIM2 CSS CPU (hard fault) RAM (parity error) Flash memory (ECC error) TIM1,8 COMPx TIM15,16,17 PVD DFSDM (analog watchdog, short circuit detection) 30/229 Interconnect action DocID025976 Rev 3 Y Y STM32L476xx Functional overview Low-power run Low-power sleep Stop 1 Stop 2 GPIO Sleep Interconnect source Run Table 6. STM32L476xx peripherals interconnect matrix (continued) TIMx External trigger Y Y Y Y - - LPTIMERx External trigger Y Y Y Y Y (1) ADCx DACx DFSDM Conversion external trigger Y Y Y Y - - Interconnect destination Interconnect action Y 1. LPTIM1 only. DocID025976 Rev 3 31/229 54 Functional overview 3.11 STM32L476xx Clocks and startup The clock controller (see Figure 3) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: four different clock sources can be used to drive the master clock SYSCLK: • 32/229 – 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply a PLL. The HSE can also be configured in bypass mode for an external clock. – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL – Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the USB device, saving the need of an external high-speed crystal (HSE). The MSI can supply a PLL. – System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency at 80 MHz. Auxiliary clock source: two ultralow-power clock sources that can be used to drive the LCD controller and the real-time clock: – 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock. – 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock accuracy is ±5% accuracy. • Peripheral clock sources: Several peripherals (USB, SDMMC, RNG, SAI, USARTs, I2Cs, LPTimers, ADC, SWPMI) have their own independent clock whatever the system clock. Three PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, the USB/SDMMC/RNG and the two SAIs. • Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software DocID025976 Rev 3 STM32L476xx Functional overview interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes (except VBAT). Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 80 MHz. DocID025976 Rev 3 33/229 54 Functional overview STM32L476xx Figure 3. Clock tree WR,:'* /6,5&N+] /6&2 WR57&DQG/&' 26&B287 /6(26& N+] 26&B,1 /6( /6, +6( 0&2 ĺ WR3:5 6<6&/. +6, WR$+%EXVFRUHPHPRU\DQG'0$ &ORFN VRXUFH FRQWURO 26&B287 +6(26& 0+] 26&B,1 $+% 35(6& +6( &ORFN GHWHFWRU +&/. )&/.&RUWH[IUHHUXQQLQJFORFN WR&RUWH[V\VWHPWLPHU 06, +6, 6<6&/. $3% 35(6& 3&/. WR$3%SHULSKHUDOV [RU[ +6,5& 0+] /6( +6, 6<6&/. WR86$57[ ; WR/38$57 +6, 6<6&/. 06,5& N+]±0+] WR,&[ [ /6, /6( +6, WR/37,0[ [ +6, 06, 3// 0 3 3//6$,&/. 4 3//86%&/. 5 3//&/. 3 3//6$,&/. 4 3//86%&/. 5 3//$'&&/. 3 3//6$,&/. +6, $3% 35(6& +6( WR6:30, 3&/. WR$3%SHULSKHUDOV [RU[ WR7,0[ [ /6( +6, 6<6&/. 3//6$, 06, 4 WR 86$57 0+]FORFNWR86%51*6'00& 6<6&/. 3//6$, 5 WR7,0[ [ WR$'& WR6$, 3//$'&&/. 6$,B(;7&/. WR6$, 6$,B(;7&/. 069 34/229 DocID025976 Rev 3 STM32L476xx 3.12 Functional overview General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.13 Direct memory access controller (DMA) The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features implementation. Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The two DMA controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests. The DMA supports: • 14 independently configurable channels (requests) • Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. • Support for circular buffer management • 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers • Access to Flash, SRAM, APB and AHB peripherals as source and destination • Programmable number of data to be transferred: up to 65536. Table 7. DMA implementation DMA features DMA1 DMA2 Number of regular channels 7 7 DocID025976 Rev 3 35/229 54 Functional overview STM32L476xx 3.14 Interrupts and events 3.14.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4. The NVIC benefits are the following: • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.14.2 Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 36 edge detector lines used to generate interrupt/event requests and wake-up the system from Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 114 GPIOs can be connected to the 16 external interrupt lines. 36/229 DocID025976 Rev 3 STM32L476xx 3.15 Functional overview Analog to digital converter (ADC) The device embeds 3 successive approximation analog-to-digital converters with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 24 external channels, some of them shared between ADC1 and ADC2, or ADC1, ADC2 and ADC3. • 5 Internal channels: internal reference voltage, temperature sensor, VBAT/3, DAC1 and DAC2 outputs. • One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply • Single-ended and differential mode inputs • Low-power design • 3.15.1 – – Capable of low-current operation at low conversion rate (consumption decreases linearly with speed) – Dual clock domain architecture: ADC speed independent from CPU frequency Highly versatile digital interface – Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions – Handles two ADC converters for dual mode operation (simultaneous or interleaved sampling modes) – Each ADC support multiple trigger inputs for synchronization with on-chip timers and external signals – Results stored into 3 data register or in RAM with DMA controller support – Data pre-processing: left/right alignment and per channel offset compensation – Built-in oversampling unit for enhanced SNR – Channel-wise programmable sampling time – Three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers – Hardware assistant to prepare the context of the injected channels to allow fast context switching Temperature sensor The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN17 and ADC3_IN17 input channels which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. DocID025976 Rev 3 37/229 54 Functional overview STM32L476xx To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 8. Temperature sensor calibration values 3.15.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 110 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75CA - 0x1FFF 75CB Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 9. Internal voltage reference calibration values 3.15.3 Calibration value name Description Memory address VREFINT Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75AA - 0x1FFF 75AB VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN18 or ADC3_IN18. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third the VBAT voltage. 3.16 Digital to analog converter (DAC) Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This digital interface supports the following features: 38/229 • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability DocID025976 Rev 3 STM32L476xx Functional overview • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-power mode, with internal or external capacitor The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.17 Voltage reference buffer (VREFBUF) The STM32L476xx devices embed an voltage reference buffer which can be used as voltage reference for ADCs, DACs and also as voltage reference for external components through the VREF+ pin. The internal voltage reference buffer supports two voltages: • 2.048V • 2.5V. An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available. 3.18 Comparators (COMP) The STM32L476xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output channels • Internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. DocID025976 Rev 3 39/229 54 Functional overview 3.19 STM32L476xx Operational amplifier (OPAMP) The STM32L476xx embeds two operational amplifiers with external or internal follower routing and PGA capability. The operational amplifier features: 3.20 • Low input bias current • Low offset voltage • Low-power mode • Rail-to-rail input Touch sensing controller (TSC) The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application. The main features of the touch sensing controller are the following: Note: 40/229 • Proven and robust surface charge transfer acquisition principle • Supports up to 24 capacitive sensing channels • Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • Full hardware management of the charge transfer acquisition sequence • Programmable charge transfer frequency • Programmable sampling capacitor I/O pin • Programmable channel I/O pin • Programmable max count value to avoid long acquisition when a channel is faulty • Dedicated end of acquisition and max count error flags with interrupt capability • One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components • Compatible with proximity, touchkey, linear and rotary touch sensor implementation • Designed to operate with STMTouch touch sensing firmware library The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O availability. DocID025976 Rev 3 STM32L476xx 3.21 Functional overview Liquid crystal display controller (LCD) The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels. 3.22 • Internal step-up converter to guarantee functionality and contrast control irrespective of VDD. This converter can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD • Supports static, 1/2, 1/3, 1/4 and 1/8 duty • Supports static, 1/2, 1/3 and 1/4 bias • • Phase inversion to reduce power consumption and EMI Integrated voltage output buffers for higher LCD driving capability • Up to 8 pixels can be programmed to blink • Unneeded segments and common pins can be used as general I/O pins • LCD RAM can be updated at any time owing to a double-buffer • The LCD controller can operate in Stop mode Digital filter for Sigma-Delta Modulators (DFSDM) The device embeds one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware. DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM). DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution. DocID025976 Rev 3 41/229 54 Functional overview STM32L476xx The DFSDM peripheral supports: • • 8 multiplexed input digital serial channels: – configurable SPI interface to connect various SD modulator(s) – configurable Manchester coded 1 wire interface support – PDM (Pulse Density Modulation) microphone input support – maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) – clock output for SD modulator(s): 0..20 MHz alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution): – • 4 digital filter modules with adjustable digital signal processing: – Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024) – integrator: oversampling ratio (1..256) • up to 24-bit output data resolution, signed output data format • automatic data offset correction (offset stored in register by user) • continuous or single conversion • start-of-conversion triggered by: • • 42/229 internal sources: device memory data streams (DMA) – software trigger – internal timers – external events – start-of-conversion synchronously with first digital filter module (DFSDM0) analog watchdog feature: – low value and high value data threshold registers – dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) – input from final output data or from selected input digital serial channels – continuous monitoring independently from standard conversion short circuit detector to detect saturated analog input values (bottom and top range): – up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream – monitoring continuously each input serial channel • break signal generation on analog watchdog event or on short circuit detector event • extremes detector: – storage of minimum and maximum values of final conversion data – refreshed by software • DMA capability to read the final conversion data • interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence • “regular” or “injected” conversions: – “regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions – “injected” conversions for precise timing and with high conversion priority DocID025976 Rev 3 STM32L476xx 3.23 Functional overview Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.24 Timers and watchdogs The STM32L476 includes two advanced control timers, up to nine general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers. Table 10. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Advanced control TIM1, TIM8 16-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 3 Generalpurpose TIM2, TIM5 32-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM3, TIM4 16-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 1 Generalpurpose TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.24.1 Advanced-control timer (TIM1, TIM8) The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge or center-aligned modes) with full modulation capability (0100%) • One-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs. DocID025976 Rev 3 43/229 54 Functional overview STM32L476xx Many features are shared with those of the general-purpose TIMx timers (described in Section 3.24.2) using the same architecture, so the advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. 3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) There are up to seven synchronizable general-purpose timers embedded in the STM32L476 (see Table 10 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. • TIM2, TIM3, TIM4 and TIM5 They are full-featured general-purpose timers: – TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler – TIM3 and TIM4 has 16-bit auto-reload up/downcounter and 16-bit prescaler. These timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining. The counters can be frozen in debug mode. All have independent DMA request generation and support quadrature encoders. • TIM15, 16 and 17 They are general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. – TIM15 has 2 channels and 1 complementary channel – TIM16 and TIM17 have 1 channel and 1 complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode. 3.24.3 Basic timers (TIM6 and TIM7) The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases. 3.24.4 Low-power timer (LPTIM1 and LPTIM2) The devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode. LPTIM1 is active in Stop 1 and Stop 2 modes. LPTIM2 is active in Stop 1 mode. 44/229 DocID025976 Rev 3 STM32L476xx Functional overview This low-power timer supports the following features: 3.24.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application). • Programmable digital glitch filter • Encoder mode (LPTIM1 only) Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.24.6 System window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.24.7 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Programmable clock source DocID025976 Rev 3 45/229 54 Functional overview 3.25 STM32L476xx Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. • Three anti-tamper detection pins with programmable filter. • Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. • 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode. The RTC clock sources can be: • A 32.768 kHz external crystal (LSE) • An external resonator or oscillator (LSE) • The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) • The high-speed external clock (HSE) divided by 32. The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode. All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 46/229 DocID025976 Rev 3 STM32L476xx 3.26 Functional overview Inter-integrated circuit interface (I2C) The device embeds 3 I2C. Refer to Table 11: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to Figure 3: Clock tree. • Wakeup from Stop mode on address match • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 11. I2C implementation I2C features(1) I2C1 I2C2 I2C3 Standard-mode (up to 100 kbit/s) X X X Fast-mode (up to 400 kbit/s) X X X Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X Programmable analog and digital noise filters X X X SMBus/PMBus hardware support X X X Independent clock X X X Wakeup from Stop 1 mode on address match X X X Wakeup from Stop 2 mode on address match - - X 1. X: supported DocID025976 Rev 3 47/229 54 Functional overview 3.27 STM32L476xx Universal synchronous/asynchronous receiver transmitter (USART) The STM32L476xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4, UART5). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to 10Mbit/s. USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All USART have a clock domain independent from the CPU clock, allowing the USARTx (x=1,2,3,4,5) to wake up the MCU from Stop mode.The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame All USART interfaces can be served by the DMA controller. 3.28 Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode. The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. LPUART interface can be served by the DMA controller. 48/229 DocID025976 Rev 3 STM32L476xx 3.29 Functional overview Serial peripheral interface (SPI) Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.30 Serial audio interfaces (SAI) The device embeds 2 SAI. Refer to Table 12: SAI implementation for the features implementation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol. The SAI peripheral supports: • Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. • 8-word integrated FIFOs for each audio sub-block. • Synchronous or asynchronous mode between the audio sub-blocks. • Master or slave configuration independent for both audio sub-blocks. • Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode. • Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit. • Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out. • Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame. • Number of bits by frame may be configurable. • Frame synchronization active level configurable (offset, bit length, level). • First active bit position in the slot is configurable. • LSB first or MSB first for data transfer. • Mute mode. • Stereo/Mono audio frame capability. • Communication clock strobing edge configurable (SCK). • Error flags with associated interrupts if enabled respectively. • • – Overrun and underrun detection. – Anticipated frame synchronization signal detection in slave mode. – Late frame synchronization signal detection in slave mode. – Codec not ready for the AC’97 mode in reception. Interruption sources when enabled: – Errors. – FIFO requests. DMA interface with 2 dedicated channels to handle access to the dedicated integrated FIFO of each SAI audio sub-block. DocID025976 Rev 3 49/229 54 Functional overview STM32L476xx Table 12. SAI implementation SAI features(1) SAI1 SAI2 I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X Mute mode X X Stereo/Mono audio frame capability. X X 16 slots X X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X X (8 Word) X (8 Word) X X FIFO Size SPDIF 1. X: supported 3.31 Single wire protocol master interface (SWPMI) The Single wire protocol master interface (SWPMI) is the master interface corresponding to the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are: • full-duplex communication mode • automatic SWP bus state management (active, suspend, resume) • configurable bitrate up to 2 Mbit/s • automatic SOF, EOF and CRC handling SWPMI can be served by the DMA controller. 3.32 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. The CAN peripheral supports: 50/229 • Supports CAN protocol version 2.0 A, B Active • Bit rates up to 1 Mbit/s DocID025976 Rev 3 STM32L476xx • • • • 3.33 Functional overview Transmission – Three transmit mailboxes – Configurable transmit priority Reception – Two receive FIFOs with three stages – 14 Scalable filter banks: – Identifier list feature – Configurable FIFO overrun Time-triggered communication option – Disable automatic retransmission mode – 16-bit free running timer – Time Stamp sent in last two data bytes Management – Maskable interrupts – Software-efficient mailbox mapping at a unique address space Secure digital input/output and MultiMediaCards Interface (SDMMC) The card host interface (SDMMC) provides an interface between the APB peripheral bus and MultiMediaCards (MMCs), SD memory cards and SDIO cards. The SDMMC features include the following: 3.34 • Full compliance with MultiMediaCard System Specification Version 4.2. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit • Full compatibility with previous versions of MultiMediaCards (forward compatibility) • Full compliance with SD Memory Card Specifications Version 2.0 • Full compliance with SD I/O Card Specification Version 2.0: card support for two different databus modes: 1-bit (default) and 4-bit • Data transfer up to 48 MHz for the 8 bit mode • Data write and read with DMA capability Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz external oscillator (LSE).This allows to use the USB device without external high speed crystal (HSE). DocID025976 Rev 3 51/229 54 Functional overview STM32L476xx The major features are: • Combined Rx and Tx FIFO size of 1.25 KB with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints • 8 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • Software configurable to OTG 1.3 and OTG 2.0 modes of operation • OTG 2.0 Supports ADP (Attach detection Protocol) • USB 2.0 LPM (Link Power Management) support • Battery Charging Specification Revision 1.2 support • Internal FS OTG PHY support For OTG/Host modes, a power switch is needed in case bus-powered devices are connected. 3.35 Flexible static memory controller (FSMC) The Flexible static memory controller (FSMC) includes two memory controllers: • The NOR/PSRAM memory controller • The NAND/memory controller This memory controller is also named Flexible memory controller (FMC). The main features of the FMC controller are the following: • Interface with static-memory mapped devices including: – Static random access memory (SRAM) – NOR Flash memory/OneNAND Flash memory – PSRAM (4 memory banks) – NAND Flash memory with ECC hardware to check up to 8 Kbyte of data • 8-,16- bit data bus width • Independent Chip Select control for each memory bank • Independent configuration for each memory bank • Write FIFO • The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2. LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 52/229 DocID025976 Rev 3 STM32L476xx 3.36 Functional overview Quad SPI memory interface (QUADSPI) The Quad SPI is a specialized communication interface targeting single, dual or quad SPI flash memories. It can operate in any of the three following modes: • Indirect mode: all the operations are performed using the QUADSPI registers • Status polling mode: the external flash status register is periodically read and an interrupt can be generated in case of flag setting • Memory-mapped mode: the external flash is memory mapped and is seen by the system as if it were an internal memory The Quad SPI interface supports: • Three functional modes: indirect, status-polling, and memory-mapped • SDR and DDR support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode • Each of the 5 following phases can be configured independently (enable, length, single/dual/quad communication) – Instruction phase – Address phase – Alternate bytes phase – Dummy cycles phase – Data phase • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • DMA channel for indirect mode operations • Programmable masking for external flash flag management • Timeout management • Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error DocID025976 Rev 3 53/229 54 Functional overview STM32L476xx 3.37 Development support 3.37.1 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.37.2 Embedded Trace Macrocell™ The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L476xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 54/229 DocID025976 Rev 3 STM32L476xx Pinouts and pin description 9'' 966 3( 3( 3% 3% %227 3% 3% 3% 3% 3% 3* 9'',2 966 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ Figure 4. STM32L476Zx LQFP144 pinout(1) /4)3 9'' 966 9''86% 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 9'',2 966 3* 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 3( 3( 3( 3( 3( 9%$7 3& 3&26&B,1 3&26&B287 3) 3) 3) 3) 3) 3) 966 9'' 3) 3) 3) 3) 3) 3+26&B,1 3+26&B287 1567 3& 3& 3& 3& 966$ 95() 95() 9''$ 3$ 3$ 3$ 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3) 3) 966 9'' 3) 3) 3) 3* 3* 3( 3( 3( 966 9'' 3( 3( 3( 3( 3( 3( 3% 3% 966 9'' 4 Pinouts and pin description 069 1. The above figure shows the package top view. DocID025976 Rev 3 55/229 91 Pinouts and pin description STM32L476xx Figure 5. STM32L476Qx UFBGA132 ballout(1) $ 3( 3( 3% %227 3' 3' 3% 3% 3$ 3$ 3$ 3$ % 3( 3( 3% 3% 3% 3' 3' 3' 3' 3& 3& 3$ & 3& 3( 3( 9'' 3% 3* 3* 3' 3' 3& 9''86% 3$ ' 3& 26&B,1 3( 966 3) 3) 3) 3* 3* 3* 3$ 3$ 3& ( 3& 26&B287 9%$7 966 3) 3* 3& 3& 3& ) 3+26&B,1 966 3) 3) 966 966 3* 3* 966 966 * 3+ 26&B287 9'' 3* 3* 9'' 9'',2 3* 3* 9'' 9'' + 3& 1567 9'' 3* 3* 3' 3' 3' - 966$95() 3& 3& 3$ 3$ 3* 3) 3) 3) 3' 3' 3' . 3* 3& 3$ 3$ 3& 3) 3) 3' 3' 3% 3% 3% / 95() 3$ 3$ 3$ 3& 3% 3( 3( 3( 3% 3% 3% 0 9''$ 3$ 23$03B 9,10 23$03B 9,10 3% 3% 3( 3( 3( 3( 3( 3( 06Y9 1. The above figure shows the package top view. 9'' 966 3( 3( 3% 3% %227 3% 3% 3% 3% 3% 3' 3' 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ Figure 6. STM32L476Vx LQFP100 pinout(1) >Y&WϭϬϬ 9'' 966 9''86% 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3' 3' 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 966 9'' 3( 3( 3( 3( 3( 9%$7 3& 3&26&B,1 3&26&B287 966 9'' 3+26&B,1 3+26&B287 1567 3& 3& 3& 3& 966$ 95() 95() 9''$ 3$ 3$ 3$ 069 1. The above figure shows the package top view. 56/229 DocID025976 Rev 3 STM32L476xx Pinouts and pin description Figure 7. STM32L476Mx WLCSP81 ballout(1) $ 9''86% 3$ 3' 3* 3* 3% 3% 966 9'' % 966 3$ 3& 3* 3* 9'',2 3% 3& 9%$7 & 3$ 3$ 3& 3* 3* 3% 3% 3& 26&B287 3& 26&B,1 ' 3$ 3$ 3& 3' 3' 3' %227 3+ 26&B287 3+26&B,1 ( 3& 3$ 3$ 9'' 3' 3( 3% 3% 1567 ) 3& 3& 3& 3' 3' 3( 3& 3& 3& * 3% 3% 3% 3$ 3$ 3$ 3& 95() 966$95() + 3% 3% 3% 3$ 3$ 3$ 3$ 3$ 9''$ - 9'' 966 3% 3% 3% 3& 3& 9'' 966 06Y9 1. The above figure shows the package top view. Figure 8. STM32L476Jx WLCSP72 ballout(1) $ 9''86% 3$ 3' 3* 3* 3% 3% 966 9'' % 966 3$ 3& 3* 3* 9'',2 3% 3& 9%$7 & 3$ 3$ 3& 3* 3* 3% 3% 3& 26&B287 3& 26&B,1 ' 3$ 3$ 3& %227 3+ 26&B287 3+26&B,1 ( 3& 3$ 3$ 3% 3% 1567 ) 3& 3& 3& 3& 3& 3& * 3% 3% 3% 3$ 3$ 3$ 3& 95() 966$95() + 3% 3% 3% 3$ 3$ 3$ 3$ 3$ 9''$ - 9'' 966 3% 3% 3% 3& 3& 9'' 966 :/&63 06Y9 1. The above figure shows the package top view. DocID025976 Rev 3 57/229 91 Pinouts and pin description STM32L476xx 9'' 966 3% 3% %227 3% 3% 3% 3% 3% 3' 3& 3& 3& 3$ 3$ Figure 9. STM32L476Rx LQFP64 pinout(1) >Y&Wϲϰ 9''86% 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3% 3% 966 9'' 9%$7 3& 3&26&B,1 3&26&B287 3+26&B,1 3+26&B287 1567 3& 3& 3& 3& 966$95() 9''$95() 3$ 3$ 3$ 069 1. The above figure shows the package top view. Table 13. Legend/abbreviations used in the pinout table Name Pin name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin Pin type I/O Input / output pin FT 5 V tolerant I/O TT 3.6 V tolerant I/O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Option for TT or FT I/Os I/O structure _f (1) _l (2) Notes Definition I/O, Fm+ capable I/O, with LCD function supplied by VLCD _u (3) I/O, with USB function supplied by VDDUSB _a (4) I/O, with Analog switch function supplied by VDDA _s (5) I/O supplied only by VDDIO2 Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset. Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions 1. The related I/O structures in Table 14 are: FT_f, FT_fa, FT_fl, FT_fla. 58/229 DocID025976 Rev 3 STM32L476xx Pinouts and pin description 2. The related I/O structures in Table 14 are: FT_l, FT_fl, FT_lu. 3. The related I/O structures in Table 14 are: FT_u, FT_lu. 4. The related I/O structures in Table 14 are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la. 5. The related I/O structures in Table 14 are: FT_s, FT_fs. Table 14. STM32L476xxSTM32L476xx pin definitions - - - - - - - - - 1 2 3 B2 A1 B1 1 2 3 PE2 I/O PE3 I/O PE4 I/O FT_l FT_l FT Alternate functions Additional functions - TRACECK, TIM3_ETR, TSC_G7_IO1, LCD_SEG38, FMC_A23, SAI1_MCLK_A, EVENTOUT - - TRACED0, TIM3_CH1, TSC_G7_IO2, LCD_SEG39, FMC_A19, SAI1_SD_B, EVENTOUT - - TRACED1, TIM3_CH2, DFSDM_DATIN3, TSC_G7_IO3, FMC_A20, SAI1_FS_A, EVENTOUT - - Notes Pin type (function after reset) I/O structure Pin functions Pin name LQFP144 UFBGA132 LQFP100 WLCSP81 WLCSP72 LQFP64 Pin Number - - - 4 C2 4 PE5 I/O FT - TRACED2, TIM3_CH3, DFSDM_CKIN3, TSC_G7_IO4, FMC_A21, SAI1_SCK_A, EVENTOUT - - - 5 D2 5 PE6 I/O FT - TRACED3, TIM3_CH4, FMC_A22, SAI1_SD_A, EVENTOUT RTC_ TAMP3/ WKUP3 6 E2 6 VBAT S - - - - EVENTOUT RTC_ TAMP1/ RTC_TS/ RTC_OUT/ WKUP2 EVENTOUT OSC32_IN 1 B9 B9 (1) 2 B8 B8 7 C1 7 PC13 I/O FT 3 C9 C9 8 D1 8 PC14/ OSC32_IN I/O FT 4 C8 C8 9 E1 9 PC15/ OSC32_OUT I/O FT (2) EVENTOUT OSC32_ OUT (2) (1) (2) (1) - - - - D6 10 PF0 I/O FT_f - I2C2_SDA, FMC_A0, EVENTOUT - - - - - D5 11 PF1 I/O FT_f - I2C2_SCL, FMC_A1, EVENTOUT - DocID025976 Rev 3 59/229 91 Pinouts and pin description STM32L476xx Table 14. STM32L476xxSTM32L476xx pin definitions (continued) WLCSP72 WLCSP81 LQFP100 UFBGA132 LQFP144 (function after reset) Pin type I/O structure Notes Pin functions LQFP64 Pin Number - - - - D4 12 PF2 I/O FT - I2C2_SMBA, FMC_A2, EVENTOUT - - - - - E4 13 PF3 I/O FT_a - FMC_A3, EVENTOUT ADC3_IN6 - - - - F3 14 PF4 I/O FT_a - FMC_A4, EVENTOUT ADC3_IN7 - - - - F4 15 PF5 I/O FT_a - FMC_A5, EVENTOUT ADC3_IN8 - - - 10 F2 16 VSS S - - - - - - - 11 G2 17 VDD S - - - - - - - - - 18 PF6 I/O FT_a - TIM5_ETR, TIM5_CH1, SAI1_SD_B, EVENTOUT ADC3_IN9 - - - - - 19 PF7 I/O FT_a - TIM5_CH2, SAI1_MCLK_B, EVENTOUT ADC3_IN10 - - - - - 20 PF8 I/O FT_a - TIM5_CH3, SAI1_SCK_B, EVENTOUT ADC3_IN11 - - - - - 21 PF9 I/O FT_a - TIM5_CH4, SAI1_FS_B, TIM15_CH1, EVENTOUT ADC3_IN12 - - - - - 22 PF10 I/O FT_a - TIM15_CH2, EVENTOUT ADC3_IN13 Pin name Alternate functions Additional functions 5 D9 D9 12 F1 23 PH0/OSC_IN I/O FT - EVENTOUT OSC_IN 6 D8 D8 13 G1 24 PH1/OSC_OUT I/O FT - EVENTOUT OSC_OUT 7 E9 E9 14 H2 25 NRST I/O RST - - - - LPTIM1_IN1, I2C3_SCL, DFSDM_DATIN4, LPUART1_RX, LCD_SEG18, LPTIM2_IN1, EVENTOUT ADC123_ IN1 ADC123_ IN2 8 F9 F9 15 H1 26 PC0 I/O FT_fla 9 F8 F8 16 J2 27 PC1 I/O FT_fla - LPTIM1_OUT, I2C3_SDA, DFSDM_CKIN4, LPUART1_TX, LCD_SEG19, EVENTOUT 10 F7 F7 17 J3 28 PC2 I/O FT_la - LPTIM1_IN2, SPI2_MISO, DFSDM_CKOUT, LCD_SEG20, EVENTOUT ADC123_ IN3 ADC123_ IN4 11 G7 G7 18 K2 29 PC3 I/O FT_a - LPTIM1_ETR, SPI2_MOSI, LCD_VLCD, SAI1_SD_A, LPTIM2_ETR, EVENTOUT - - - 19 - 30 VSSA S - - - - - - - 20 - 31 VREF- S - - - - 60/229 DocID025976 Rev 3 STM32L476xx Pinouts and pin description Table 14. STM32L476xxSTM32L476xx pin definitions (continued) LQFP144 Pin type I/O structure Notes - J1 - VSSA/VREF- - - - - - G8 G8 21 L1 32 VREF+ S - - - VREFBUF_ OUT 13 H9 H9 22 M1 33 VDDA S - - - - WLCSP81 Alternate functions WLCSP72 (function after reset) LQFP64 UFBGA132 Pin functions LQFP100 Pin Number 12 G9 G9 - 14 H8 H8 - - - 15 G4 G4 Pin name 23 L2 34 PA0 I/O FT_a - - M3 - OPAMP1_ VINM I TT - 24 M2 35 PA1 I/O FT_la Additional functions TIM2_CH1, TIM5_CH1, OPAMP1_ TIM8_ETR, USART2_CTS, VINP, UART4_TX, ADC12_IN5, SAI1_EXTCLK, RTC_TAMP TIM2_ETR, EVENTOUT 2/WKUP1 - - - TIM2_CH2, TIM5_CH2, OPAMP1_ USART2_RTS_DE, VINM, UART4_RX, LCD_SEG0, ADC12_IN6 TIM15_CH1N, EVENTOUT 16 G6 G6 25 K3 36 PA2 I/O FT_la - TIM2_CH3, TIM5_CH3, ADC12_IN7, USART2_TX, LCD_SEG1, WKUP4/ SAI2_EXTCLK, LSCO TIM15_CH1, EVENTOUT 17 H7 H7 26 L3 37 PA3 I/O TT - TIM2_CH4, TIM5_CH4, USART2_RX, LCD_SEG2, TIM15_CH2, EVENTOUT OPAMP1_ VOUT, ADC12_IN8 18 J9 J9 27 E3 38 VSS S - - - - 19 J8 J8 28 H3 39 VDD S - - - - 20 G5 G5 29 J4 40 PA4 I/O TT_a - SPI1_NSS, SPI3_NSS, ADC12_ USART2_CK, SAI1_FS_B, IN9, DAC1_ LPTIM2_OUT, EVENTOUT OUT1 - TIM2_CH1, TIM2_ETR, TIM8_CH1N, SPI1_SCK, LPTIM2_ETR, EVENTOUT ADC12_ IN10, DAC1_ OUT2 OPAMP2_ VINP, ADC12_ IN11 - 21 H6 H6 22 H5 H5 - - - 30 K4 41 PA5 I/O TT_a 31 L4 42 PA6 I/O FT_la - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, USART3_CTS, QUADSPI_BK1_IO3, LCD_SEG3, TIM1_BKIN_COMP2, TIM8_BKIN_COMP2, TIM16_CH1, EVENTOUT - M4 - OPAMP2_ VINM - TT - - DocID025976 Rev 3 61/229 91 Pinouts and pin description STM32L476xx Table 14. STM32L476xxSTM32L476xx pin definitions (continued) 23 H4 H4 24 25 26 27 J7 J6 J5 J4 J7 J6 J5 J4 32 33 34 35 36 J5 K5 L5 M5 M6 43 44 45 46 47 PA7 PC4 PC5 PB0 PB1 I/O I/O I/O I/O I/O FT_la FT_la FT_la TT_la FT_la Alternate functions Additional functions - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, QUADSPI_BK1_IO2, LCD_SEG4, TIM17_CH1, EVENTOUT OPAMP2_ VINM, ADC12_ IN12 - USART3_TX, LCD_SEG22, EVENTOUT COMP1_ INM, ADC12_ IN13 - USART3_RX, LCD_SEG23, EVENTOUT COMP1_ INP, ADC12_ IN14, WKUP5 - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, USART3_CK, QUADSPI_BK1_IO1, LCD_SEG5, COMP1_OUT, EVENTOUT OPAMP2_ VOUT, ADC12_ IN15 - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM_DATIN0, USART3_RTS_DE, QUADSPI_BK1_IO0, LCD_SEG6, LPTIM2_IN1, EVENTOUT COMP1_ INM, ADC12_ IN16 COMP1_ INP Notes (function after reset) Pin type LQFP144 Pin name I/O structure Pin functions UFBGA132 LQFP100 WLCSP81 WLCSP72 LQFP64 Pin Number 28 J3 J3 37 L6 48 PB2 I/O FT_a - RTC_OUT, LPTIM1_OUT, I2C3_SMBA, DFSDM_CKIN0, EVENTOUT - - - - K6 49 PF11 I/O FT - EVENTOUT - - - - - J7 50 PF12 I/O FT - FMC_A6, EVENTOUT - - - - - - 51 VSS S - - - - - - - - - 52 VDD S - - - - - - - - K7 53 PF13 I/O FT - DFSDM_DATIN6, FMC_A7, EVENTOUT - - - - - J8 54 PF14 I/O FT - DFSDM_CKIN6, TSC_G8_IO1, FMC_A8, EVENTOUT - - - - - J9 55 PF15 I/O FT - TSC_G8_IO2, FMC_A9, EVENTOUT - 62/229 DocID025976 Rev 3 STM32L476xx Pinouts and pin description Table 14. STM32L476xxSTM32L476xx pin definitions (continued) WLCSP72 WLCSP81 LQFP100 UFBGA132 LQFP144 (function after reset) Pin type I/O structure Notes Pin functions LQFP64 Pin Number - - - - H9 56 PG0 I/O FT - TSC_G8_IO3, FMC_A10, EVENTOUT - - - - - G9 57 PG1 I/O FT - TSC_G8_IO4, FMC_A11, EVENTOUT - - Pin name Alternate functions Additional functions - - E6 38 M7 58 PE7 I/O FT - TIM1_ETR, DFSDM_DATIN2, FMC_D4, SAI1_SD_B, EVENTOUT - - F6 39 L7 59 PE8 I/O FT - TIM1_CH1N, DFSDM_CKIN2, FMC_D5, SAI1_SCK_B, EVENTOUT - - - - - 40 M8 60 PE9 I/O FT - TIM1_CH1, DFSDM_CKOUT, FMC_D6, SAI1_FS_B, EVENTOUT - - - - F6 61 VSS S - - - - - - - - G6 62 VDD S - - - - - TIM1_CH2N, DFSDM_DATIN4, TSC_G5_IO1, QUADSPI_CLK, FMC_D7, SAI1_MCLK_B, EVENTOUT - - TIM1_CH2, DFSDM_CKIN4, TSC_G5_IO2, QUADSPI_NCS, FMC_D8, EVENTOUT - - TIM1_CH3N, SPI1_NSS, DFSDM_DATIN5, TSC_G5_IO3, QUADSPI_BK1_IO0, FMC_D9, EVENTOUT - - TIM1_CH3, SPI1_SCK, DFSDM_CKIN5, TSC_G5_IO4, QUADSPI_BK1_IO1, FMC_D10, EVENTOUT - - TIM1_CH4, TIM1_BKIN2, TIM1_BKIN2_COMP2, SPI1_MISO, QUADSPI_BK1_IO2, FMC_D11, EVENTOUT - - - - - - - - - - - - - - - - 41 42 43 44 45 L8 M9 L9 M10 M11 63 64 65 66 67 PE10 PE11 PE12 PE13 PE14 I/O I/O I/O I/O I/O FT FT FT FT FT DocID025976 Rev 3 63/229 91 Pinouts and pin description STM32L476xx Table 14. STM32L476xxSTM32L476xx pin definitions (continued) - - - 29 H3 H3 46 47 M12 L10 68 69 PE15 PB10 I/O I/O FT FT_fl Alternate functions Additional functions - TIM1_BKIN, TIM1_BKIN_COMP1, SPI1_MOSI, QUADSPI_BK1_IO3, FMC_D12, EVENTOUT - - TIM2_CH3, I2C2_SCL, SPI2_SCK, DFSDM_DATIN7, USART3_TX, LPUART1_RX, QUADSPI_CLK, LCD_SEG10, COMP1_OUT, SAI1_SCK_A, EVENTOUT - - Notes Pin type (function after reset) I/O structure Pin functions Pin name LQFP144 UFBGA132 LQFP100 WLCSP81 WLCSP72 LQFP64 Pin Number 30 G3 G3 48 L11 70 PB11 I/O FT_fl - TIM2_CH4, I2C2_SDA, DFSDM_CKIN7, USART3_RX, LPUART1_TX, QUADSPI_NCS, LCD_SEG11, COMP2_OUT, EVENTOUT 31 J2 J2 49 F12 71 VSS S - - - - 32 J1 J1 50 G12 72 VDD S - - - - - TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, DFSDM_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, LCD_SEG12, SWPMI1_IO, SAI2_FS_A, TIM15_BKIN, EVENTOUT - - TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, LCD_SEG13, SWPMI1_TX, SAI2_SCK_A, TIM15_CH1N, EVENTOUT - 33 H1 H1 34 H2 H2 64/229 51 52 L12 K12 73 74 PB12 PB13 I/O I/O FT_l FT_fl DocID025976 Rev 3 STM32L476xx Pinouts and pin description Table 14. STM32L476xxSTM32L476xx pin definitions (continued) 35 G2 G2 36 G1 G1 - - - - - - - - F5 F4 - - 53 K11 75 PB14 I/O FT_fl Alternate functions Additional functions - TIM1_CH2N, TIM8_CH2N, I2C2_SDA, SPI2_MISO, DFSDM_DATIN2, USART3_RTS_DE, TSC_G1_IO3, LCD_SEG14, SWPMI1_RX, SAI2_MCLK_A, TIM15_CH1, EVENTOUT - - Notes (function after reset) Pin type LQFP144 Pin name I/O structure Pin functions UFBGA132 LQFP100 WLCSP81 WLCSP72 LQFP64 Pin Number 54 K10 76 PB15 I/O FT_l - RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI, DFSDM_CKIN2, TSC_G1_IO4, LCD_SEG15, SWPMI1_SUSPEND, SAI2_SD_A, TIM15_CH2, EVENTOUT 55 K9 77 PD8 I/O FT_l - USART3_TX, LCD_SEG28, FMC_D13, EVENTOUT - - USART3_RX, LCD_SEG29, FMC_D14, SAI2_MCLK_A, EVENTOUT - - USART3_CK, TSC_G6_IO1, LCD_SEG30, FMC_D15, SAI2_SCK_A, EVENTOUT - - USART3_CTS, TSC_G6_IO2, LCD_SEG31, FMC_A16, SAI2_SD_A, LPTIM2_ETR, EVENTOUT - - 56 57 58 K8 J12 J11 78 79 80 PD9 PD10 PD11 I/O I/O I/O FT_l FT_l FT_l - - - 59 J10 81 PD12 I/O FT_l - TIM4_CH1, USART3_RTS_DE, TSC_G6_IO3, LCD_SEG32, FMC_A17, SAI2_FS_A, LPTIM2_IN1, EVENTOUT - - - 60 H12 82 PD13 I/O FT_l - TIM4_CH2, TSC_G6_IO4, LCD_SEG33, FMC_A18, LPTIM2_OUT, EVENTOUT - - - - - - 83 VSS S - - - - - - - - - 84 VDD S - - - - DocID025976 Rev 3 65/229 91 Pinouts and pin description STM32L476xx Table 14. STM32L476xxSTM32L476xx pin definitions (continued) WLCSP72 WLCSP81 LQFP100 UFBGA132 LQFP144 (function after reset) Pin type I/O structure Notes Pin functions LQFP64 Pin Number - - - 61 H11 85 PD14 I/O FT_l - TIM4_CH3, LCD_SEG34, FMC_D0, EVENTOUT - - - - 62 H10 86 PD15 I/O FT_l - TIM4_CH4, LCD_SEG35, FMC_D1, EVENTOUT - - - - - G10 87 PG2 I/O FT_s - SPI1_SCK, FMC_A12, SAI2_SCK_B, EVENTOUT - - - - - F9 88 PG3 I/O FT_s - SPI1_MISO, FMC_A13, SAI2_FS_B, EVENTOUT - - - - - F10 89 PG4 I/O FT_s - SPI1_MOSI, FMC_A14, SAI2_MCLK_B, EVENTOUT - - Pin name Alternate functions Additional functions - - - - E9 90 PG5 I/O FT_s - SPI1_NSS, LPUART1_CTS, FMC_A15, SAI2_SD_B, EVENTOUT - - - - G4 91 PG6 I/O FT_s - I2C3_SMBA, LPUART1_RTS_DE, EVENTOUT - - - - - H4 92 PG7 I/O FT_fs - I2C3_SCL, LPUART1_TX, FMC_INT3, EVENTOUT - - - - - J6 93 PG8 I/O FT_fs - I2C3_SDA, LPUART1_RX, EVENTOUT - - - - - - 94 VSS S - - - - - - - - - 95 VDDIO2 S - - - - - TIM3_CH1, TIM8_CH1, DFSDM_CKIN3, TSC_G4_IO1, LCD_SEG24, SDMMC1_D6, SAI2_MCLK_A, EVENTOUT - - TIM3_CH2, TIM8_CH2, DFSDM_DATIN3, TSC_G4_IO2, LCD_SEG25, SDMMC1_D7, SAI2_MCLK_B, EVENTOUT - 37 38 F3 F3 F1 F1 66/229 63 64 E12 E11 96 97 PC6 PC7 I/O I/O FT_l FT_l DocID025976 Rev 3 STM32L476xx Pinouts and pin description Table 14. STM32L476xxSTM32L476xx pin definitions (continued) 39 F2 F2 40 E1 E1 65 66 E10 D12 98 99 PC8 PC9 I/O I/O FT_l FT_l Alternate functions Additional functions - TIM3_CH3, TIM8_CH3, TSC_G4_IO3, LCD_SEG26, SDMMC1_D0, EVENTOUT - - TIM8_BKIN2, TIM3_CH4, TIM8_CH4, TSC_G4_IO4, OTG_FS_NOE, LCD_SEG27, SDMMC1_D1, SAI2_EXTCLK, TIM8_BKIN2_COMP1, EVENTOUT - - Notes (function after reset) Pin type LQFP144 Pin name I/O structure Pin functions UFBGA132 LQFP100 WLCSP81 WLCSP72 LQFP64 Pin Number 41 E2 E2 67 D11 100 PA8 I/O FT_l - MCO, TIM1_CH1, USART1_CK, OTG_FS_SOF, LCD_COM0, LPTIM2_OUT, EVENTOUT 42 E3 E3 68 D10 101 PA9 I/O FT_lu - TIM1_CH2, USART1_TX, LCD_COM1, TIM15_BKIN, EVENTOUT OTG_FS_ VBUS 43 D2 D2 69 C12 102 PA10 I/O FT_lu - TIM1_CH3, USART1_RX, OTG_FS_ID, LCD_COM2, TIM17_BKIN, EVENTOUT - - TIM1_CH4, TIM1_BKIN2, USART1_CTS, CAN1_RX, OTG_FS_DM, TIM1_BKIN2_COMP1, EVENTOUT - - 44 D1 D1 70 B12 103 PA11 I/O FT_u 45 C1 C1 71 A12 104 PA12 I/O FT_u - TIM1_ETR, USART1_RTS_DE, CAN1_TX, OTG_FS_DP, EVENTOUT 46 C2 C2 72 A11 105 PA13 I/O FT (3) JTMS/SWDIO, IR_OUT, OTG_FS_NOE, EVENTOUT - 47 B1 B1 - VSS S - - - - 48 A1 A1 73 C11 106 VDDUSB S - - - - - - - - - 74 F11 107 VSS S - - - - - - - 75 G11 108 VDD S - - - - 76 A10 109 PA14 I/O FT (3) JTCK/SWCLK, EVENTOUT - 49 B2 B2 DocID025976 Rev 3 67/229 91 Pinouts and pin description STM32L476xx Table 14. STM32L476xxSTM32L476xx pin definitions (continued) 50 A2 A2 51 D3 D3 52 C3 C3 53 B3 B3 - - - - - - 54 A3 A3 - 68/229 - - 77 78 79 80 81 82 83 84 A9 B11 110 111 C10 112 B10 113 C9 B9 C8 B8 114 115 116 117 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 I/O I/O I/O I/O I/O I/O I/O I/O FT_l FT_l FT_l FT_l FT FT FT_l FT DocID025976 Rev 3 Alternate functions Additional functions (3) JTDI, TIM2_CH1, TIM2_ETR, SPI1_NSS, SPI3_NSS, UART4_RTS_DE, TSC_G3_IO1, LCD_SEG17, SAI2_FS_B, EVENTOUT - - SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, LCD_COM4/LCD_SEG28/ LCD_SEG40, SDMMC1_D2, SAI2_SCK_B, EVENTOUT - - SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, LCD_COM5/LCD_SEG29/ LCD_SEG41, SDMMC1_D3, SAI2_MCLK_B, EVENTOUT - - SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, LCD_COM6/LCD_SEG30/ LCD_SEG42, SDMMC1_CK, SAI2_SD_B, EVENTOUT - - SPI2_NSS, DFSDM_DATIN7, CAN1_RX, FMC_D2, EVENTOUT - - SPI2_SCK, DFSDM_CKIN7, CAN1_TX, FMC_D3, EVENTOUT - - TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, LCD_COM7/LCD_SEG31/ LCD_SEG43, SDMMC1_CMD, EVENTOUT - - SPI2_MISO, DFSDM_DATIN0, USART2_CTS, FMC_CLK, EVENTOUT - Notes Pin type (function after reset) I/O structure Pin functions Pin name LQFP144 UFBGA132 LQFP100 WLCSP81 WLCSP72 LQFP64 Pin Number STM32L476xx Pinouts and pin description Table 14. STM32L476xxSTM32L476xx pin definitions (continued) Notes (function after reset) Pin type LQFP144 Pin name I/O structure Pin functions UFBGA132 LQFP100 WLCSP81 WLCSP72 LQFP64 Pin Number Alternate functions Additional functions - - - E5 85 B7 118 PD4 I/O FT - SPI2_MOSI, DFSDM_CKIN0, USART2_RTS_DE, FMC_NOE, EVENTOUT - - D4 86 A6 119 PD5 I/O FT - USART2_TX, FMC_NWE, EVENTOUT - - - - - - 120 VSS S - - - - - - E4 - - 121 VDD S - - - - - - - D5 87 B6 122 PD6 I/O FT - DFSDM_DATIN1, USART2_RX, FMC_NWAIT, SAI1_SD_A, EVENTOUT - - D6 88 A5 123 PD7 I/O FT - DFSDM_CKIN1, USART2_CK, FMC_NE1, EVENTOUT - - SPI3_SCK, USART1_TX, FMC_NCE3/FMC_NE2, SAI2_SCK_A, TIM15_CH1N, EVENTOUT - - LPTIM1_IN1, SPI3_MISO, USART1_RX, FMC_NE3, SAI2_FS_A, TIM15_CH1, EVENTOUT - - LPTIM1_IN2, SPI3_MOSI, USART1_CTS, SAI2_MCLK_A, TIM15_CH2, EVENTOUT - - - - - A4 A4 B4 B4 C4 C4 - - - D9 D8 G3 124 125 126 PG9 PG10 PG11 I/O I/O I/O FT_s FT_s FT_s - C5 C5 - D7 127 PG12 I/O FT_s - LPTIM1_ETR, SPI3_NSS, USART1_RTS_DE, FMC_NE4, SAI2_SD_A, EVENTOUT - B5 B5 - C7 128 PG13 I/O FT_fs - I2C1_SDA, USART1_CK, FMC_A24, EVENTOUT - - A5 A5 - C6 129 PG14 I/O FT_fs - I2C1_SCL, FMC_A25, EVENTOUT - - F7 130 VSS S - - - - - G7 131 VDDIO2 S - - - - - K1 132 PG15 I/O FT_s - LPTIM1_OUT, I2C1_SMBA, EVENTOUT - - - - B6 B6 - - DocID025976 Rev 3 69/229 91 Pinouts and pin description STM32L476xx Table 14. STM32L476xxSTM32L476xx pin definitions (continued) 55 A6 A6 56 C6 C6 57 C7 C7 58 B7 B7 89 90 91 92 A8 A7 C5 B5 133 134 135 136 PB3 PB4 PB5 PB6 I/O I/O I/O I/O FT_la FT_la FT_la FT_fa Alternate functions Additional functions (3) JTDO/TRACESWO, TIM2_CH2, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, LCD_SEG7, SAI1_SCK_B, EVENTOUT COMP2_ INM (3) NJTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, USART1_CTS, UART5_RTS_DE, TSC_G2_IO1, LCD_SEG8, SAI1_MCLK_B, TIM17_BKIN, EVENTOUT COMP2_ INP - LPTIM1_IN1, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, UART5_CTS, TSC_G2_IO2, LCD_SEG9, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, EVENTOUT - - LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL, DFSDM_DATIN5, USART1_TX, TSC_G2_IO3, TIM8_BKIN2_COMP2, SAI1_FS_B, TIM16_CH1N, EVENTOUT COMP2_ INP COMP2_ INM, PVD_IN Notes Pin type (function after reset) I/O structure Pin functions Pin name LQFP144 UFBGA132 LQFP100 WLCSP81 WLCSP72 LQFP64 Pin Number 59 A7 A7 93 B4 137 PB7 I/O FT_fla - LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA, DFSDM_CKIN5, USART1_RX, UART4_CTS, TSC_G2_IO4, LCD_SEG21, FMC_NL, TIM8_BKIN_COMP1, TIM17_CH1N, EVENTOUT 60 D7 D7 94 A4 138 BOOT0 I - - - - - TIM4_CH3, I2C1_SCL, DFSDM_DATIN6, CAN1_RX, LCD_SEG16, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1, EVENTOUT - 61 E7 E7 70/229 95 A3 139 PB8 I/O FT_fl DocID025976 Rev 3 STM32L476xx Pinouts and pin description Table 14. STM32L476xxSTM32L476xx pin definitions (continued) 62 E8 E8 Notes Pin type (function after reset) I/O structure Pin functions Pin name LQFP144 UFBGA132 LQFP100 WLCSP81 WLCSP72 LQFP64 Pin Number Alternate functions Additional functions - 96 B3 140 PB9 I/O FT_fl - IR_OUT, TIM4_CH4, I2C1_SDA, SPI2_NSS, DFSDM_CKIN6, CAN1_TX, LCD_COM3, SDMMC1_D5, SAI1_FS_A, TIM17_CH1, EVENTOUT - - - 97 C3 141 PE0 I/O FT_l - TIM4_ETR, LCD_SEG36, FMC_NBL0, TIM16_CH1, EVENTOUT - - - - 98 A2 142 PE1 I/O FT_l - LCD_SEG37, FMC_NBL1, TIM17_CH1, EVENTOUT - 99 D3 143 VSS S - - - - 64 A9 A9 100 C4 144 VDD S - - - - 63 A8 A8 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF - These GPIOs must not be used as current sources (e.g. to drive an LED). 2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0351 reference manual. 3. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated. DocID025976 Rev 3 71/229 91 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR - - - USART2_CTS PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_RTS_ DE PA2 - TIM2_CH3 TIM5_CH3 - - - - USART2_TX PA3 - TIM2_CH4 TIM5_CH4 - - - - USART2_RX PA4 - - - - - SPI1_NSS SPI3_NSS USART2_CK PA5 - TIM2_CH1 TIM2_ETR TIM8_CH1N - SPI1_SCK - - PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO - USART3_CTS PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - SPI1_MOSI - - PA8 MCO TIM1_CH1 - - - - - USART1_CK PA9 - TIM1_CH2 - - - - - USART1_TX PA10 - TIM1_CH3 - - - - - USART1_RX PA11 - TIM1_CH4 TIM1_BKIN2 - - - - USART1_CTS PA12 - TIM1_ETR - - - - - USART1_RTS_ DE PA13 JTMS/SWDIO IR_OUT - - - - - - PA14 JTCK/SWCLK - - - - - - - PA15 JTDI TIM2_CH1 TIM2_ETR - - SPI1_NSS SPI3_NSS - Port DocID025976 Rev 3 Port A STM32L476xx AF0 Pinouts and pin description 72/229 Table 15. Alternate function AF0 to AF7 (for AF8 to AF15 see Table 16) AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - - USART3_CK PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - DFSDM_DATIN0 USART3_RTS_ DE PB2 RTC_OUT LPTIM1_OUT - - I2C3_SMBA - DFSDM_CKIN0 - PB3 JTDO/TRACES WO TIM2_CH2 - - - SPI1_SCK SPI3_SCK USART1_RTS_ DE PB4 NJTRST - TIM3_CH1 - - SPI1_MISO SPI3_MISO USART1_CTS PB5 - LPTIM1_IN1 TIM3_CH2 - I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK PB6 - LPTIM1_ETR TIM4_CH1 TIM8_BKIN2 I2C1_SCL - DFSDM_DATIN5 USART1_TX PB7 - LPTIM1_IN2 TIM4_CH2 TIM8_BKIN I2C1_SDA - DFSDM_CKIN5 USART1_RX PB8 - - TIM4_CH3 - I2C1_SCL - DFSDM_DATIN6 - PB9 - IR_OUT TIM4_CH4 - I2C1_SDA SPI2_NSS DFSDM_CKIN6 - PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK DFSDM_DATIN7 USART3_TX PB11 - TIM2_CH4 - - I2C2_SDA - DFSDM_CKIN7 USART3_RX PB12 - TIM1_BKIN - TIM1_BKIN_ COMP2 I2C2_SMBA SPI2_NSS DFSDM_DATIN1 USART3_CK PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK DFSDM_CKIN1 USART3_CTS PB14 - TIM1_CH2N - TIM8_CH2N I2C2_SDA SPI2_MISO DFSDM_DATIN2 USART3_RTS_ DE PB15 RTC_REFIN TIM1_CH3N - TIM8_CH3N - SPI2_MOSI DFSDM_CKIN2 - Port DocID025976 Rev 3 Port B 73/229 Pinouts and pin description AF0 STM32L476xx Table 15. Alternate function AF0 to AF7 (for AF8 to AF15 see Table 16) (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PC0 - LPTIM1_IN1 - - I2C3_SCL - DFSDM_DATIN4 - PC1 - LPTIM1_OUT - - I2C3_SDA - DFSDM_CKIN4 - PC2 - LPTIM1_IN2 - - - SPI2_MISO DFSDM_CKOUT - PC3 - LPTIM1_ETR - - - SPI2_MOSI - - PC4 - - - - - - - USART3_TX PC5 - - - - - - - USART3_RX PC6 - - TIM3_CH1 TIM8_CH1 - - DFSDM_CKIN3 - PC7 - - TIM3_CH2 TIM8_CH2 - - DFSDM_DATIN3 - PC8 - - TIM3_CH3 TIM8_CH3 - - - - PC9 - TIM8_BKIN2 TIM3_CH4 TIM8_CH4 - - - - PC10 - - - - - - SPI3_SCK USART3_TX PC11 - - - - - - SPI3_MISO USART3_RX PC12 - - - - - - SPI3_MOSI USART3_CK PC13 - - - - - - - - PC14 - - - - - - - - PC15 - - - - - - - - Port DocID025976 Rev 3 Port C STM32L476xx AF0 Pinouts and pin description 74/229 Table 15. Alternate function AF0 to AF7 (for AF8 to AF15 see Table 16) (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PD0 - - - - - SPI2_NSS DFSDM_DATIN7 - PD1 - - - - - SPI2_SCK DFSDM_CKIN7 - PD2 - - TIM3_ETR - - - - USART3_RTS_ DE PD3 - - - - - SPI2_MISO DFSDM_DATIN0 USART2_CTS PD4 - - - - - SPI2_MOSI DFSDM_CKIN0 USART2_RTS_ DE PD5 - - - - - - - USART2_TX PD6 - - - - - - DFSDM_DATIN1 USART2_RX PD7 - - - - - - DFSDM_CKIN1 USART2_CK PD8 - - - - - - - USART3_TX PD9 - - - - - - - USART3_RX PD10 - - - - - - - USART3_CK PD11 - - - - - - - USART3_CTS PD12 - - TIM4_CH1 - - - - USART3_RTS_ DE PD13 - - TIM4_CH2 - - - - - PD14 - - TIM4_CH3 - - - - - PD15 - - TIM4_CH4 - - - - - Port DocID025976 Rev 3 Port D 75/229 Pinouts and pin description AF0 STM32L476xx Table 15. Alternate function AF0 to AF7 (for AF8 to AF15 see Table 16) (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PE0 - - TIM4_ETR - - - - - PE1 - - - - - - - - PE2 TRACECK - TIM3_ETR - - - - - PE3 TRACED0 - TIM3_CH1 - - - - - PE4 TRACED1 - TIM3_CH2 - - - DFSDM_DATIN3 - PE5 TRACED2 - TIM3_CH3 - - - DFSDM_CKIN3 - PE6 TRACED3 - TIM3_CH4 - - - - - PE7 - TIM1_ETR - - - - DFSDM_DATIN2 - PE8 - TIM1_CH1N - - - - DFSDM_CKIN2 - PE9 - TIM1_CH1 - - - - DFSDM_CKOUT - PE10 - TIM1_CH2N - - - - DFSDM_DATIN4 - PE11 - TIM1_CH2 - - - - DFSDM_CKIN4 - PE12 - TIM1_CH3N - - - SPI1_NSS DFSDM_DATIN5 - PE13 - TIM1_CH3 - - - SPI1_SCK DFSDM_CKIN5 - PE14 - TIM1_CH4 TIM1_BKIN2 TIM1_BKIN2_ COMP2 - SPI1_MISO - - PE15 - TIM1_BKIN - TIM1_BKIN_ COMP1 - SPI1_MOSI - - Port DocID025976 Rev 3 Port E Pinouts and pin description 76/229 Table 15. Alternate function AF0 to AF7 (for AF8 to AF15 see Table 16) (continued) STM32L476xx AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PF0 - - - - I2C2_SDA - - - PF1 - - - - I2C2_SCL - - - PF2 - - - - I2C2_SMBA - - - PF3 - - - - - - - - PF4 - - - - - - - - PF5 - - - - - - - - PF6 - TIM5_ETR TIM5_CH1 - - - - - PF7 - - TIM5_CH2 - - - - - PF8 - - TIM5_CH3 - - - - - PF9 - - TIM5_CH4 - - - - - PF10 - - - - - - - - PF11 - - - - - - - - PF12 - - - - - - - - PF13 - - - - - - DFSDM_DATIN6 - PF14 - - - - - - DFSDM_CKIN6 - PF15 - - - - - - - - Port DocID025976 Rev 3 Port F 77/229 Pinouts and pin description AF0 STM32L476xx Table 15. Alternate function AF0 to AF7 (for AF8 to AF15 see Table 16) (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/TIM2/ TIM5/TIM8/ LPTIM1 TIM1/TIM2/ TIM3/TIM4/ TIM5 TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM USART1/ USART2/ USART3 PG0 - - - - - - - - PG1 - - - - - - - - PG2 - - - - - SPI1_SCK - - PG3 - - - - - SPI1_MISO - - PG4 - - - - - SPI1_MOSI - - PG5 - - - - - SPI1_NSS - - PG6 - - - - I2C3_SMBA - - - PG7 - - - - I2C3_SCL - - - PG8 - - - - I2C3_SDA - - - PG9 - - - - - - SPI3_SCK USART1_TX PG10 - LPTIM1_IN1 - - - - SPI3_MISO USART1_RX PG11 - LPTIM1_IN2 - - - - SPI3_MOSI USART1_CTS PG12 - LPTIM1_ETR - - - - SPI3_NSS USART1_RTS_ DE PG13 - - - - I2C1_SDA - - USART1_CK PG14 - - - - I2C1_SCL - - - PG15 - LPTIM1_OUT - - I2C1_SMBA - - - PH0 - - - - - - - - PH1 - - - - - - - - Port DocID025976 Rev 3 Port G Port H STM32L476xx AF0 Pinouts and pin description 78/229 Table 15. Alternate function AF0 to AF7 (for AF8 to AF15 see Table 16) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PA0 UART4_TX - - - - SAI1_EXTCLK TIM2_ETR EVENTOUT PA1 UART4_RX - - LCD_SEG0 - - TIM15_CH1N EVENTOUT PA2 - - - LCD_SEG1 - SAI2_EXTCLK TIM15_CH1 EVENTOUT PA3 - - - LCD_SEG2 - - TIM15_CH2 EVENTOUT PA4 - - - - - SAI1_FS_B LPTIM2_OUT EVENTOUT PA5 - - - - - - LPTIM2_ETR EVENTOUT PA6 - - QUADSPI_BK1_IO3 LCD_SEG3 TIM1_BKIN_ COMP2 TIM8_BKIN_ COMP2 TIM16_CH1 EVENTOUT PA7 - - QUADSPI_BK1_IO2 LCD_SEG4 - - TIM17_CH1 EVENTOUT PA8 - - OTG_FS_SOF LCD_COM0 - - LPTIM2_OUT EVENTOUT PA9 - - - LCD_COM1 - - TIM15_BKIN EVENTOUT PA10 - - OTG_FS_ID LCD_COM2 - - TIM17_BKIN EVENTOUT PA11 - CAN1_RX OTG_FS_DM - TIM1_BKIN2_ COMP1 - - EVENTOUT PA12 - CAN1_TX OTG_FS_DP - - - - EVENTOUT PA13 - - OTG_FS_NOE - - - - EVENTOUT PA14 - - - - - - - EVENTOUT PA15 UART4_RTS _DE TSC_G3_IO1 - LCD_SEG17 - SAI2_FS_B - EVENTOUT Port DocID025976 Rev 3 Port A 79/229 Pinouts and pin description AF8 STM32L476xx Table 16. Alternate function AF8 to AF15 (for AF0 to AF7 see Table 15) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PB0 - - QUADSPI_BK1_IO1 LCD_SEG5 COMP1_OUT - - EVENTOUT PB1 - - QUADSPI_BK1_IO0 LCD_SEG6 - - LPTIM2_IN1 EVENTOUT PB2 - - - - - - - EVENTOUT PB3 - - - LCD_SEG7 - SAI1_SCK_B - EVENTOUT PB4 UART5_RTS _DE TSC_G2_IO1 - LCD_SEG8 - SAI1_MCLK_ B TIM17_BKIN EVENTOUT PB5 UART5_CTS TSC_G2_IO2 - LCD_SEG9 COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT PB6 - TSC_G2_IO3 - - TIM8_BKIN2_ COMP2 SAI1_FS_B TIM16_CH1N EVENTOUT PB7 UART4_CTS TSC_G2_IO4 - LCD_SEG21 FMC_NL TIM8_BKIN_ COMP1 TIM17_CH1N EVENTOUT PB8 - CAN1_RX - LCD_SEG16 SDMMC1_D4 SAI1_MCLK_ A TIM16_CH1 EVENTOUT PB9 - CAN1_TX - LCD_COM3 SDMMC1_D5 SAI1_FS_A TIM17_CH1 EVENTOUT PB10 LPUART1_ RX - QUADSPI_CLK LCD_SEG10 COMP1_OUT SAI1_SCK_A - EVENTOUT PB11 LPUART1_TX - QUADSPI_NCS LCD_SEG11 COMP2_OUT - - EVENTOUT PB12 LPUART1_ RTS_DE TSC_G1_IO1 - LCD_SEG12 SWPMI1_IO SAI2_FS_A TIM15_BKIN EVENTOUT PB13 LPUART1_ CTS TSC_G1_IO2 - LCD_SEG13 SWPMI1_TX SAI2_SCK_A TIM15_CH1N EVENTOUT PB14 - TSC_G1_IO3 - LCD_SEG14 SWPMI1_RX SAI2_MCLK_ A TIM15_CH1 EVENTOUT PB15 - TSC_G1_IO4 - LCD_SEG15 SWPMI1_SUSPEND SAI2_SD_A TIM15_CH2 EVENTOUT Port DocID025976 Rev 3 Port B STM32L476xx AF8 Pinouts and pin description 80/229 Table 16. Alternate function AF8 to AF15 (for AF0 to AF7 see Table 15) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PC0 LPUART1_ RX - - LCD_SEG18 - - LPTIM2_IN1 EVENTOUT PC1 LPUART1_TX - - LCD_SEG19 - - - EVENTOUT PC2 - - - LCD_SEG20 - - - EVENTOUT PC3 - - - LCD_VLCD - SAI1_SD_A LPTIM2_ETR EVENTOUT PC4 - - - LCD_SEG22 - - - EVENTOUT PC5 - - - LCD_SEG23 - - - EVENTOUT PC6 - TSC_G4_IO1 - LCD_SEG24 SDMMC1_D6 SAI2_MCLK_ A - EVENTOUT PC7 - TSC_G4_IO2 - LCD_SEG25 SDMMC1_D7 SAI2_MCLK_ B - EVENTOUT PC8 - TSC_G4_IO3 - LCD_SEG26 SDMMC1_D0 - - EVENTOUT PC9 - TSC_G4_IO4 OTG_FS_NOE LCD_SEG27 SDMMC1_D1 SAI2_EXTCLK TIM8_BKIN2_ COMP1 EVENTOUT PC10 UART4_TX TSC_G3_IO2 - LCD_COM4/ LCD_SEG28/ LCD_SEG40 SDMMC1_D2 SAI2_SCK_B - EVENTOUT PC11 UART4_RX TSC_G3_IO3 - LCD_COM5/ LCD_SEG29/ LCD_SEG41 SDMMC1_D3 SAI2_MCLK_ B - EVENTOUT PC12 UART5_TX TSC_G3_IO4 - LCD_COM6/ LCD_SEG30/ LCD_SEG42 SDMMC1_CK SAI2_SD_B - EVENTOUT PC13 - - - - - - - EVENTOUT PC14 - - - - - - - EVENTOUT PC15 - - - - - - - EVENTOUT Port DocID025976 Rev 3 Port C 81/229 Pinouts and pin description AF8 STM32L476xx Table 16. Alternate function AF8 to AF15 (for AF0 to AF7 see Table 15) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PD0 - CAN1_RX - - FMC_D2 - - EVENTOUT PD1 - CAN1_TX - - FMC_D3 - - EVENTOUT PD2 UART5_RX TSC_SYNC - LCD_COM7/ LCD_SEG31/ LCD_SEG43 SDMMC1_CMD - - EVENTOUT PD3 - - - - FMC_CLK - - EVENTOUT PD4 - - - - FMC_NOE - - EVENTOUT PD5 - - - - FMC_NWE - - EVENTOUT PD6 - - - - FMC_NWAIT SAI1_SD_A - EVENTOUT PD7 - - - - FMC_NE1 - - EVENTOUT PD8 - - - LCD_SEG28 FMC_D13 - - EVENTOUT PD9 - - - LCD_SEG29 FMC_D14 SAI2_MCLK_ A - EVENTOUT PD10 - TSC_G6_IO1 - LCD_SEG30 FMC_D15 SAI2_SCK_A - EVENTOUT PD11 - TSC_G6_IO2 - LCD_SEG31 FMC_A16 SAI2_SD_A LPTIM2_ETR EVENTOUT PD12 - TSC_G6_IO3 - LCD_SEG32 FMC_A17 SAI2_FS_A LPTIM2_IN1 EVENTOUT PD13 - TSC_G6_IO4 - LCD_SEG33 FMC_A18 - LPTIM2_OUT EVENTOUT PD14 - - - LCD_SEG34 FMC_D0 - - EVENTOUT PD15 - - - LCD_SEG35 FMC_D1 - - EVENTOUT Port DocID025976 Rev 3 Port D STM32L476xx AF8 Pinouts and pin description 82/229 Table 16. Alternate function AF8 to AF15 (for AF0 to AF7 see Table 15) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PE0 - - - LCD_SEG36 FMC_NBL0 - TIM16_CH1 EVENTOUT PE1 - - - LCD_SEG37 FMC_NBL1 - TIM17_CH1 EVENTOUT PE2 - TSC_G7_IO1 - LCD_SEG38 FMC_A23 SAI1_MCLK_ A - EVENTOUT PE3 - TSC_G7_IO2 - LCD_SEG39 FMC_A19 SAI1_SD_B - EVENTOUT PE4 - TSC_G7_IO3 - - FMC_A20 SAI1_FS_A - EVENTOUT PE5 - TSC_G7_IO4 - - FMC_A21 SAI1_SCK_A - EVENTOUT PE6 - - - - FMC_A22 SAI1_SD_A - EVENTOUT PE7 - - - - FMC_D4 SAI1_SD_B - EVENTOUT PE8 - - - - FMC_D5 SAI1_SCK_B - EVENTOUT PE9 - - - - FMC_D6 SAI1_FS_B - EVENTOUT PE10 - TSC_G5_IO1 QUADSPI_CLK - FMC_D7 SAI1_MCLK_ B - EVENTOUT PE11 - TSC_G5_IO2 QUADSPI_NCS - FMC_D8 - - EVENTOUT PE12 - TSC_G5_IO3 QUADSPI_BK1_IO0 - FMC_D9 - - EVENTOUT PE13 - TSC_G5_IO4 QUADSPI_BK1_IO1 - FMC_D10 - - EVENTOUT PE14 - - QUADSPI_BK1_IO2 - FMC_D11 - - EVENTOUT PE15 - - QUADSPI_BK1_IO3 - FMC_D12 - - EVENTOUT Port DocID025976 Rev 3 Port E 83/229 Pinouts and pin description AF8 STM32L476xx Table 16. Alternate function AF8 to AF15 (for AF0 to AF7 see Table 15) (continued) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PF0 - - - - FMC_A0 - - EVENTOUT PF1 - - - - FMC_A1 - - EVENTOUT PF2 - - - - FMC_A2 - - EVENTOUT PF3 - - - - FMC_A3 - - EVENTOUT PF4 - - - - FMC_A4 - - EVENTOUT PF5 - - - - FMC_A5 - - EVENTOUT PF6 - - - - - SAI1_SD_B - EVENTOUT PF7 - - - - - SAI1_MCLK_ B - EVENTOUT PF8 - - - - - SAI1_SCK_B - EVENTOUT PF9 - - - - - SAI1_FS_B TIM15_CH1 EVENTOUT PF10 - - - - - - TIM15_CH2 EVENTOUT PF11 - - - - - - - EVENTOUT PF12 - - - - FMC_A6 - - EVENTOUT PF13 - - - - FMC_A7 - - EVENTOUT PF14 - TSC_G8_IO1 - - FMC_A8 - - EVENTOUT PF15 - TSC_G8_IO2 - - FMC_A9 - - EVENTOUT Port DocID025976 Rev 3 Port F Pinouts and pin description 84/229 Table 16. Alternate function AF8 to AF15 (for AF0 to AF7 see Table 15) (continued) STM32L476xx AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PG0 - TSC_G8_IO3 - - FMC_A10 - - EVENTOUT PG1 - TSC_G8_IO4 - - FMC_A11 - - EVENTOUT PG2 - - - - FMC_A12 SAI2_SCK_B - EVENTOUT PG3 - - - - FMC_A13 SAI2_FS_B - EVENTOUT PG4 - - - - FMC_A14 SAI2_MCLK_ B - EVENTOUT PG5 LPUART1_ CTS - - - FMC_A15 SAI2_SD_B - EVENTOUT PG6 LPUART1_ RTS_DE - - - - - - EVENTOUT PG7 LPUART1_TX - - - FMC_INT3 - - EVENTOUT PG8 LPUART1_ RX - - - - - - EVENTOUT PG9 - - - - FMC_NCE3/ FMC_NE2 SAI2_SCK_A TIM15_CH1N EVENTOUT PG10 - - - - FMC_NE3 SAI2_FS_A TIM15_CH1 EVENTOUT PG11 - - - - - SAI2_MCLK_ A TIM15_CH2 EVENTOUT PG12 - - - - FMC_NE4 SAI2_SD_A - EVENTOUT PG13 - - - - FMC_A24 - - EVENTOUT PG14 - - - - FMC_A25 - - EVENTOUT PG15 - - - - - - - EVENTOUT Port DocID025976 Rev 3 Port G 85/229 Pinouts and pin description AF8 STM32L476xx Table 16. Alternate function AF8 to AF15 (for AF0 to AF7 see Table 15) (continued) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4, UART5, LPUART1 CAN1, TSC OTG_FS, QUADSPI LCD SDMMC1, COMP1, COMP2, FMC, SWPMI1 SAI1, SAI2 TIM2, TIM15, TIM16, TIM17, LPTIM2 EVENTOUT PH0 - - - - - - - EVENTOUT PH1 - - - - - - - EVENTOUT Port Port H Pinouts and pin description 86/229 Table 16. Alternate function AF8 to AF15 (for AF0 to AF7 see Table 15) (continued) DocID025976 Rev 3 STM32L476xx STM32L476xx 5 Memory mapping Memory mapping Figure 10. STM32L476 memory map [)))))))) [%))))))) &RUWH[0 ZLWK)38 ,QWHUQDO 3HULSKHUDOV 5HVHUYHG [$ 48$'63,UHJLVWHUV [$ )0&UHJLVWHUV [$ [( [))))))) 5HVHUYHG [& $+% [ [& 5HVHUYHG [ )0&DQG 48$'63, UHJLVWHUV $+% [ [ [$ 48$'63,)ODVK EDQN [ )0&EDQN [ [ 5HVHUYHG $3% 5HVHUYHG [ $3% [))))))) [ 5HVHUYHG [)))) )0&EDQN EDQN 2SWLRQ%\WHV [)))) 5HVHUYHG [)))) 6\VWHPPHPRU\ [ [))) [))) [))) 5HVHUYHG 2SWLRQV%\WHV 5HVHUYHG [))) 3HULSKHUDOV [ 273DUHD [))) 6\VWHPPHPRU\ [))) [ 65$0 5HVHUYHG [ 65$0 [ 5HVHUYHG &2'( [ )ODVKPHPRU\ [ [ [ 5HVHUYHG [ 5HVHUYHG )ODVKV\VWHPPHPRU\ RU65$0GHSHQGLQJRQ %227FRQILJXUDWLRQ 069 DocID025976 Rev 3 87/229 91 Memory mapping STM32L476xx Table 17. STM32L476xx memory map and peripheral register boundary addresses (1) Bus AHB3 AHB2 - AHB1 88/229 Boundary address Size (bytes) Peripheral 0xA000 1000 - 0xA000 13FF 1 KB QUADSPI 0xA000 0000 - 0xA000 0FFF 4 KB FMC 0x5006 0800 - 0x5006 0BFF 1 KB RNG 0x5004 0400 - 0x5006 07FF 129 KB 0x5004 0000 - 0x5004 03FF 1 KB ADC 0x5000 0000 - 0x5003 FFFF 16 KB OTG_FS 0x4800 2000 - 0x4FFF FFFF ~127 MB Reserved 0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH 0x4800 1800 - 0x4800 1BFF 1 KB GPIOG 0x4800 1400 - 0x4800 17FF 1 KB GPIOF 0x4800 1000 - 0x4800 13FF 1 KB GPIOE 0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD 0x4800 0800 - 0x4800 0BFF 1 KB GPIOC 0x4800 0400 - 0x4800 07FF 1 KB GPIOB 0x4800 0000 - 0x4800 03FF 1 KB GPIOA 0x4002 4400 - 0x47FF FFFF ~127 MB 0x4002 4000 - 0x4002 43FF 1 KB TSC 0x4002 3400 - 0x4002 3FFF 1 KB Reserved 0x4002 3000 - 0x4002 33FF 1 KB CRC 0x4002 2400 - 0x4002 2FFF 3 KB Reserved 0x4002 2000 - 0x4002 23FF 1 KB FLASH registers 0x4002 1400 - 0x4002 1FFF 3 KB Reserved 0x4002 1000 - 0x4002 13FF 1 KB RCC 0x4002 0800 - 0x4002 0FFF 2 KB Reserved 0x4002 0400 - 0x4002 07FF 1 KB DMA2 0x4002 0000 - 0x4002 03FF 1 KB DMA1 DocID025976 Rev 3 Reserved Reserved STM32L476xx Memory mapping Table 17. STM32L476xx memory map and peripheral register boundary addresses (continued)(1) Bus APB2 APB2 Boundary address Size (bytes) Peripheral 0x4001 6400 - 0x4001 FFFF 39 KB Reserved 0x4001 6000 - 0x4000 63FF 1 KB DFSDM 0x4001 5C00 - 0x4000 5FFF 1 KB Reserved 0x4001 5800 - 0x4000 5BFF 1 KB SAI2 0x4001 5400 - 0x4000 57FF 1 KB SAI1 0x4001 4C00 - 0x4000 53FF 2 KB Reserved 0x4001 4800 - 0x4001 4BFF 1 KB TIM17 0x4001 4400 - 0x4001 47FF 1 KB TIM16 0x4001 4000 - 0x4001 43FF 1 KB TIM15 0x4001 3C00 - 0x4001 3FFF 1 KB Reserved 0x4001 3800 - 0x4001 3BFF 1 KB USART1 0x4001 3400 - 0x4001 37FF 1 KB TIM8 0x4001 3000 - 0x4001 33FF 1 KB SPI1 0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 0x4001 2800 - 0x4001 2BFF 1 KB SDMMC1 0x4001 2000 - 0x4001 27FF 2 KB Reserved 0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL 0x4001 0800- 0x4001 1BFF 5 KB Reserved 0x4001 0400 - 0x4001 07FF 1 KB EXTI 0x4001 0200 - 0x4001 03FF 0x4001 0030 - 0x4001 01FF 0x4001 0000 - 0x4001 002F DocID025976 Rev 3 COMP 1 KB VREFBUF SYSCFG 89/229 91 Memory mapping STM32L476xx Table 17. STM32L476xx memory map and peripheral register boundary addresses (continued)(1) Bus APB1 90/229 Boundary address Size (bytes) Peripheral 0x4000 9800 - 0x4000 FFFF 26 KB Reserved 0x4000 9400 - 0x4000 97FF 1 KB LPTIM2 0x4000 8C00 - 0x4000 93FF 2 KB Reserved 0x4000 8800 - 0x4000 8BFF 1 KB SWPMI1 0x4000 8400 - 0x4000 87FF 1 KB Reserved 0x4000 8000 - 0x4000 83FF 1 KB LPUART1 0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1 0x4000 7800 - 0x4000 7BFF 1 KB OPAMP 0x4000 7400 - 0x4000 77FF 1 KB DAC 0x4000 7000 - 0x4000 73FF 1 KB PWR 0x4000 6800 - 0x4000 6FFF 1 KB Reserved 0x4000 6400 - 0x4000 67FF 1 KB CAN1 0x4000 6000 - 0x4000 63FF 1 KB Reserved 0x4000 5C00- 0x4000 5FFF 1 KB I2C3 0x4000 5800 - 0x4000 5BFF 1 KB I2C2 0x4000 5400 - 0x4000 57FF 1 KB I2C1 0x4000 5000 - 0x4000 53FF 1 KB UART5 0x4000 4C00 - 0x4000 4FFF 1 KB UART4 0x4000 4800 - 0x4000 4BFF 1 KB USART3 0x4000 4400 - 0x4000 47FF 1 KB USART2 DocID025976 Rev 3 STM32L476xx Memory mapping Table 17. STM32L476xx memory map and peripheral register boundary addresses (continued)(1) Bus APB1 Boundary address Size (bytes) Peripheral 0x4000 4000 - 0x4000 43FF 1 KB Reserved 0x4000 3C00 - 0x4000 3FFF 1 KB SPI3 0x4000 3800 - 0x4000 3BFF 1 KB SPI2 0x4000 3400 - 0x4000 37FF 1 KB Reserved 0x4000 3000 - 0x4000 33FF 1 KB IWDG 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG 0x4000 2800 - 0x4000 2BFF 1 KB RTC 0x4000 2400 - 0x4000 27FF 1 KB LCD 0x4000 1800 - 0x4000 23FF 3 KB Reserved 0x4000 1400 - 0x4000 17FF 1 KB TIM7 0x4000 1000 - 0x4000 13FF 1 KB TIM6 0x4000 0C00- 0x4000 0FFF 1 KB TIM5 0x4000 0800 - 0x4000 0BFF 1 KB TIM4 0x4000 0400 - 0x4000 07FF 1 KB TIM3 0x4000 0000 - 0x4000 03FF 1 KB TIM2 1. The gray color is used for reserved boundary addresses. DocID025976 Rev 3 91/229 91 Electrical characteristics STM32L476xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 11. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 12. Figure 11. Pin loading conditions Figure 12. Pin input voltage 0&8SLQ 0&8SLQ & S) 9,1 069 92/229 DocID025976 Rev 3 069 STM32L476xx 6.1.6 Electrical characteristics Power supply scheme Figure 13. Power supply scheme 9%$7 9%$7 9%$7 ĂĐŬƵƉĐŝƌĐƵŝƚƌLJ %DFNXSFLUFXLWU\ ĂĐŬƵƉĐŝƌĐƵŝƚƌLJ ;>^͕Zd͕ /6(57& ;>^͕Zd͕ ĂĐŬƵƉƌĞŐŝƐƚĞƌƐͿ %DFNXSUHJLVWHUV ĂĐŬƵƉƌĞŐŝƐƚĞƌƐͿ ϭ͘ϱϱʹϯ͘ϲs ±9 ϭ͘ϱϱʹϯ͘ϲs WŽǁĞƌƐǁŝƚĐŚ 3RZHUVZLWFK WŽǁĞƌƐǁŝƚĐŚ 99'' '' 9'' 99&25( &25( 9&25( Q[9'' Q[9'' Q[9'' ZĞŐƵůĂƚŽƌ 5HJXODWRU ZĞŐƵůĂƚŽƌ Q[Q) Q[Q) Q[Q) [) [) [) *3,2V *3,2V *3,2V ,1 /E /E /HYHOVKLIWHU /HYHOVKLIWHU /HYHOVKLIWHU Khd 287 Khd ,2 ,2 ,2 ORJLF ORJLF ORJLF /HYHOVKLIWHU /HYHOVKLIWHU /HYHOVKLIWHU 9 '',2 99'',2 '',2 ,2 ,2 ,2 ORJLF ORJLF ORJLF <ĞƌŶĞůůŽŐŝĐ .HUQHOORJLF <ĞƌŶĞůůŽŐŝĐ ;Wh͕ŝŐŝƚĂů &38'LJLWDO ;Wh͕ŝŐŝƚĂů 0HPRULHV ΘDĞŵŽƌŝĞƐͿ ΘDĞŵŽƌŝĞƐͿ Q[966 Q[966 '',2 99'',2 P[9'',2 P[9'',2 '',2 99'',2 '',2 287 Khd Khd P[Q) P[Q) P[Q) ) ) ) *3,2V *3,2V *3,2V ,1 ,1 ,1 P[966 P[966 P[966 ''$ 99''$ 9''$ Q) ϭϬŶ& ) ϭϬŶ& ) ) 95() 95() 9''$ 9''$ 9''$ ϭϬϬŶ& ) ϭϬϬŶ& ) 966$ 5() 995() 995() 5() 95() 95() $'&V $'&V '$&V $'&V '$&V 23$03V '$&V 23$03V &203V 23$03V &203V 95() &203V 95()%8) 95() 966$ 966$ 069 069 Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DocID025976 Rev 3 93/229 204 Electrical characteristics 6.1.7 STM32L476xx Current consumption measurement Figure 14. Current consumption measurement scheme ,''B86% 9''86% ,''B9%$7 9%$7 ,'' 9'' 9'',2 ,''$ 9''$ 069 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics, Table 19: Current characteristics and Table 20: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 18. Voltage characteristics(1) Symbol Ratings Min Max Unit VDDX - VSS External main supply voltage (including VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT) -0.3 4.0 V Input voltage on FT_xxx pins VSS-0.3 min (VDD, VDDA, VDDIO2, VDDUSB, VLCD) + 4.0(3)(4) Input voltage on TT_xx pins VSS-0.3 4.0 Input voltage on BOOT0 pin VSS 9.0 VSS-0.3 4.0 Variations between different VDDX power pins of the same domain - 50 mV Variations between all the different ground pins - 50 mV VIN(2) Input voltage on any other pins |∆VDDx| |VSSx-VSS| V 1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 94/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics 2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum allowed injected current values. 3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table. 4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled. Table 19. Current characteristics Symbol Ratings Max ∑IVDD Total current into sum of all VDD power lines (source)(1) 150 ∑IVSS (sink)(1) 150 Total current out of sum of all VSS ground lines IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100 IVSS(PIN) (1) 100 IIO(PIN) ∑IIO(PIN) IINJ(PIN)(3) ∑IINJ(PIN) Maximum current out of each VSS ground pin (sink) Output current sunk by any I/O and control pin except FT_f 20 Output current sunk by any FT_f pin 20 Output current sourced by any I/O and control pin 20 Total output current sunk by sum of all I/Os and control pins(2) Total output current sourced by sum of all I/Os and control pins Unit mA 100 (2) 100 Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5 -5/+0(4) Injected current on PA4, PA5 -5/0 Total injected current (sum of all I/Os and control pins)(5) ±25 1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 20. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DocID025976 Rev 3 Value Unit –65 to +150 °C 150 °C 95/229 204 Electrical characteristics STM32L476xx 6.3 Operating conditions 6.3.1 General operating conditions Table 21. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 80 fPCLK1 Internal APB1 clock frequency - 0 80 fPCLK2 Internal APB2 clock frequency - 0 80 Standard operating voltage - VDD VDDIO2 PG[15:2] I/Os supply voltage VDDA Analog supply voltage 1.71 At least one I/O in PG[15:2] used PG[15:2] not used 96/229 3.6 VREFBUF used 2.4 USB used USB not used Power dissipation at TA = 85 °C for suffix 6 or TA = 105 °C for suffix 7(4) Power dissipation at TA = 125 °C for suffix 3(4) V V V 1.55 3.6 V 3.0 3.6 0 3.6 -0.3 VDDIOx+0.3 0 9 -0.3 MIN(MIN(VDD, VDDA, VDDIO2, VDDUSB, VLCD)+3.6 V, 5.5 V)(2)(3) 0 LQFP144 - - 625 LQFP100 - - 476 LQFP64 - - 444 UFBGA132 - - 363 WLCSP81 - - 487 WLCSP72 - - 434 LQFP144 - - 156 LQFP100 - - 119 LQFP64 - - 111 UFBGA132 - - 90 WLCSP81 - - 121 WLCSP72 - - 108 DocID025976 Rev 3 MHz 3.6 I/O input voltage All I/O except BOOT0 and TT_xx PD 0 1.8 BOOT0 PD 3.6 DAC or OPAMP used TT_xx I/O VIN 1.08 1.62 Backup operating voltage VDDUSB USB supply voltage 3.6 ADC or COMP used ADC, DAC, OPAMP, COMP, VREFBUF not used VBAT (1) Unit V V mW mW STM32L476xx Electrical characteristics Table 21. General operating conditions (continued) Symbol TA TJ Parameter Conditions Min Max Ambient temperature for the suffix 6 version Maximum power dissipation –40 85 Low-power dissipation(5) –40 105 Ambient temperature for the suffix 7 version Maximum power dissipation –40 105 –40 125 Ambient temperature for the suffix 3 version Maximum power dissipation –40 125 Low-power dissipation(5) –40 130 Suffix 6 version –40 105 Suffix 7 version –40 125 Suffix 3 version –40 130 Junction temperature range Low-power dissipation (5) Unit °C °C 1. When RESET is released functionality is guaranteed down to VBOR0 Min. 2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA, VDDIO2, VDDUSB, VLCD)+3.6 V and 5.5V. 3. For operation with voltage higher than Min (VDD, VDDA, VDDIO2, VDDUSB, VLCD) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled. 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.7: Thermal characteristics). 5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.7: Thermal characteristics). 6.3.2 Operating conditions at power-up / power-down The parameters given in Table 22 are derived from tests performed under the ambient temperature condition summarized in Table 21. Table 22. Operating conditions at power-up / power-down Symbol tVDD tVDDA tVDDUSB tVDDIO2 6.3.3 Parameter Conditions VDD rise time rate - VDD fall time rate VDDA rise time rate - VDDA fall time rate VDDUSB rise time rate VDDUSB fall time rate VDDIO2 rise time rate VDDIO2 fall time rate - - Min Max 0 ∞ 10 ∞ 0 ∞ 10 ∞ 0 ∞ 10 ∞ 0 ∞ 10 ∞ Unit µs/V Embedded reset and power control block characteristics The parameters given in Table 23 are derived from tests performed under the ambient temperature conditions summarized in Table 21: General operating conditions. DocID025976 Rev 3 97/229 204 Electrical characteristics STM32L476xx Table 23. Embedded reset and power control block characteristics Symbol tRSTTEMPO(2) Conditions(1) Min Typ Max Unit - 250 400 μs Rising edge 1.62 1.66 1.7 Falling edge 1.6 1.64 1.69 Rising edge 2.06 2.1 2.14 Falling edge 1.96 2 2.04 Rising edge 2.26 2.31 2.35 Falling edge 2.16 2.20 2.24 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.85 2.90 2.95 Falling edge 2.76 2.81 2.86 Rising edge 2.1 2.15 2.19 Falling edge 2 2.05 2.1 Rising edge 2.26 2.31 2.36 Falling edge 2.15 2.20 2.25 Rising edge 2.41 2.46 2.51 Falling edge 2.31 2.36 2.41 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.69 2.74 2.79 Falling edge 2.59 2.64 2.69 Rising edge 2.85 2.91 2.96 Falling edge 2.75 2.81 2.86 Rising edge 2.92 2.98 3.04 Falling edge 2.84 2.90 2.96 Hysteresis in continuous Hysteresis voltage of BORH0 mode - 20 - Hysteresis in other mode - 30 - Reset temporization after BOR0 is detected VBOR0(2) Brown-out reset threshold 0 VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 VBOR3 Brown-out reset threshold 3 VBOR4 Brown-out reset threshold 4 VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Vhyst_BORH0 VDD rising V V V V V V V V V V V V mV Hysteresis voltage of BORH (except BORH0) and PVD - - 100 - mV BOR(3) (except BOR0) and IDD (BOR_PVD)(2) PVD consumption from VDD - - 1.1 1.6 µA - 1.18 1.22 1.26 V Vhyst_BOR_PVD VPVM1 98/229 Parameter VDDUSB peripheral voltage monitoring DocID025976 Rev 3 STM32L476xx Electrical characteristics Table 23. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions(1) Min Typ Max Unit - 0.92 0.96 1 V VPVM2 VDDIO2 peripheral voltage monitoring VPVM3 VDDA peripheral voltage monitoring Rising edge 1.61 1.65 1.69 Falling edge 1.6 1.64 1.68 VPVM4 VDDA peripheral voltage monitoring Rising edge 1.78 1.82 1.86 Falling edge 1.77 1.81 1.85 V V Vhyst_PVM3 PVM3 hysteresis - - 10 - mV Vhyst_PVM4 PVM4 hysteresis - - 10 - mV IDD PVM1 and PVM2 (PVM1/PVM2) consumption from VDD (2) - - 0.2 - µA IDD PVM3 and PVM4 (PVM3/PVM4) consumption from VDD (2) - - 2 - µA 1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 2. Guaranteed by design. 3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables. DocID025976 Rev 3 99/229 204 Electrical characteristics 6.3.4 STM32L476xx Embedded voltage reference The parameters given in Table 24 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. Table 24. Embedded internal voltage reference Symbol VREFINT Parameter Conditions Internal reference voltage –40 °C < TA < +130 °C Min Typ Max Unit 1.182 1.212 1.232 V tS_vrefint (1) ADC sampling time when reading the internal reference voltage - 4(2) - - µs tstart_vrefint Start time of reference voltage buffer when ADC is enable - - 8 12(2) µs - - 12.5 20(2) µA VDD = 3 V - - TBD(2) mV –40°C < TA < +105°C - - TBD(2) –40°C < TA < +50°C - - TBD(2) 1000 hours, T = 25°C - - TBD(2) ppm - - TBD(2) ppm/V 24 25 26 49 50 51 74 75 76 VREFINT buffer consumption from VDD when converted by IDD(VREFINTBUF) ADC ∆VREFINT Internal reference voltage spread over the temperature range TCoeff Temperature coefficient ACoeff Long term stability VDDCoeff Voltage coefficient VREFINT_DIV1 1/4 reference voltage VREFINT_DIV2 1/2 reference voltage VREFINT_DIV3 3/4 reference voltage 3.0 V < VDD < 3.6 V - 1. The shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. 100/229 DocID025976 Rev 3 ppm/°C % VREFINT STM32L476xx 6.3.5 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 14: Current consumption measurement scheme. Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode • All peripherals are disabled except when explicitly mentioned • The Flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0351 reference manual). • When the peripherals are enabled fPCLK = fHCLK The parameters given in Table 25 to Table 38 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. DocID025976 Rev 3 101/229 204 running from Flash, ART enable (Cache ON Prefetch OFF) Conditions Symbol Parameter - Voltage scaling Unit 55 °C 85 °C 3.20 3.37 3.51 3.93 4.76 2.49 2.01 2.16 2.30 2.72 3.34 1.29 1.62 1.10 1.17 1.31 1.73 2.56 0.69 0.85 1.18 0.61 0.70 0.89 1.24 1.95 0.37 0.47 0.64 0.96 0.37 0.46 0.64 0.98 1.71 0.23 0.26 0.36 0.53 0.85 0.27 0.33 0.50 0.86 1.57 100 kHz 0.14 0.17 0.27 0.43 0.75 0.17 0.21 0.38 0.74 1.44 80 MHz 10.2 10.3 10.5 10.7 11.1 11.22 11.8 12.1 12.5 13.3 72 MHz 9.24 9.31 9.47 9.69 10.1 10.16 10.7 11.0 11.4 12.2 64 MHz 8.25 8.32 8.46 8.68 9.09 9.08 9.6 9.9 10.3 11.1 Range 1 48 MHz 6.28 6.35 6.5 6.72 7.11 6.91 7.3 7.6 8.0 8.8 32 MHz 4.24 4.30 4.44 4.65 5.04 4.66 4.97 5.26 5.67 6.51 24 MHz 3.21 3.27 3.4 3.61 3.98 3.53 3.76 4.05 4.46 5.30 16 MHz 2.19 2.24 2.36 2.56 2.94 2.41 2.66 2.95 3.16 3.99 2 MHz 272 303 413 592 958 330 393 579 954 1704 1 MHz 154 184 293 473 835 195 265 457 822 1572 400 kHz 78 108 217 396 758 110 180 380 755 1505 100 kHz 42 73 182 360 723 75 138 331 706 1456 Range 2 DocID025976 Rev 3 IDD(Run) MAX(1) TYP fHCLK = fHSE up to 48MHz included, Supply bypass mode current in PLL ON above Run mode 48 MHz all peripherals disable Supply current in fHCLK = fMSI IDD(LPRun) Low-power all peripherals disable run mode 25 °C 55 °C 85 °C 26 MHz 2.88 2.93 3.05 3.23 3.58 16 MHz 1.83 1.87 1.98 2.16 8 MHz 0.98 1.02 1.12 4 MHz 0.55 0.59 2 MHz 0.34 1 MHz fHCLK 105 °C 125 °C mA µA STM32L476xx 1. Guaranteed by characterization results, unless otherwise specified. 105 °C 125 °C 25 °C Electrical characteristics 102/229 Table 25. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART disable Conditions Symbol Parameter - Voltage scaling Range 2 IDD(Run) DocID025976 Rev 3 fHCLK = fHSE up to 48MHz included, Supply bypass mode current in PLL ON above Run mode 48 MHz all peripherals disable MAX(1) TYP Unit 25 °C 55 °C 85 °C 26 MHz 3.15 3.19 3.31 3.50 3.85 16 MHz 2.24 2.28 2.39 2.57 8 MHz 1.26 1.29 1.40 1.57 4 MHz 0.71 0.75 0.85 2 MHz 0.42 0.45 1 MHz 0.27 0.30 100 kHz 0.14 0.17 80 MHz 10.0 10.1 fHCLK 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 3.47 3.70 3.84 4.26 4.88 2.90 2.46 2.60 2.74 3.16 3.78 1.89 1.40 1.50 1.64 2.06 2.68 1.02 1.34 0.79 0.88 1.06 1.38 2.21 0.55 0.72 1.04 0.46 0.55 0.73 1.09 1.88 0.40 0.57 0.89 0.30 0.38 0.57 0.90 1.61 0.27 0.43 0.75 0.17 0.22 0.40 0.74 1.44 10.3 10.6 11.0 11.00 11.35 11.64 12.26 13.10 72 MHz 9.06 9.13 9.28 9.51 9.92 9.97 10.36 10.65 11.06 11.69 64 MHz 8.96 9.04 9.22 9.48 9.92 9.86 10.25 10.54 10.95 11.79 Range 1 48 MHz 7.64 7.72 7.91 8.17 8.62 8.40 8.76 8.90 9.52 10.36 32 MHz 5.49 5.57 5.74 5.98 6.40 6.04 6.40 6.69 7.10 7.94 24 MHz 4.16 4.22 4.36 4.57 4.96 4.60 4.86 5.15 5.56 6.19 16 MHz 2.93 2.99 3.13 3.35 3.75 3.22 3.43 3.72 4.13 4.97 2 MHz 358 392 503 683 1050 435 501 694 1069 1819 1 MHz 197 230 340 519 880 245 312 512 887 1637 400 kHz 97 126 235 414 778 130 202 402 777 1527 100 kHz 47 77 186 365 726 85 147 347 711 1472 Supply current in fHCLK = fMSI IDD(LPRun) Low-power all peripherals disable run mA µA 103/229 Electrical characteristics 1. Guaranteed by characterization results, unless otherwise specified. STM32L476xx Table 26. Current consumption in Run and Low-power run modes, code with data processing Conditions Symbol Parameter - Voltage scaling Range 2 IDD(Run) Supply current in Run mode DocID025976 Rev 3 fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Range 1 IDD(LPRun) Supply current in low-power run mode fHCLK = fMSI all peripherals disable FLASH in power-down MAX(1) TYP fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 26 MHz 2.88 2.94 3.05 3.23 3.58 3.18 3.26 3.40 4.02 4.65 16 MHz 1.83 1.87 1.98 2.15 2.50 2.01 2.16 2.30 2.72 3.34 8 MHz 0.97 1.00 1.11 1.27 1.62 1.07 1.16 1.32 1.73 2.36 4 MHz 0.54 0.57 0.67 0.84 1.18 0.59 0.69 0.88 1.23 1.96 2 MHz 0.33 0.36 0.46 0.62 0.96 0.37 0.45 0.63 0.98 1.70 1 MHz 0.22 0.25 0.35 0.51 0.85 0.25 0.33 0.50 0.86 1.57 100 kHz 0.12 0.15 0.25 0.41 0.75 0.15 0.21 0.39 0.74 1.45 80 MHz 10.2 10.3 10.5 10.7 11.1 11.22 11.57 11.86 12.07 13.11 72 MHz 9.25 9.31 9.46 9.68 10.1 10.18 10.41 10.55 10.76 11.80 64 MHz 8.25 8.31 8.46 8.67 9.08 9.08 9.37 9.66 9.87 10.91 48 MHz 6.26 6.33 6.48 6.69 7.11 6.89 7.11 7.25 7.67 8.50 32 MHz 4.22 4.28 4.42 4.63 5.03 4.64 4.86 5.15 5.56 6.19 24 MHz 3.20 3.25 3.38 3.59 3.99 3.52 3.70 3.84 4.26 5.09 16 MHz 2.18 2.22 2.35 2.55 2.94 2.40 2.55 2.84 3.25 4.09 2 MHz 242 275 384 562 924 300 380 573 927 1677 1 MHz 130 162 269 445 809 180 243 435 810 1560 400 kHz 61 90 197 374 734 95 160 353 728 1478 100 kHz 26 56 163 339 702 55 122 314 679 1429 Unit Electrical characteristics 104/229 Table 27. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 mA µA 1. Guaranteed by characterization results, unless otherwise specified. STM32L476xx STM32L476xx Electrical characteristics Table 28. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) Conditions - IDD(Run) Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling Range 2 fHCLK = 26 MHz Parameter Unit 25 °C 25 °C Reduced code(1) 2.9 111 Coremark 3.1 118 Dhrystone 2.1 3.1 Fibonacci 2.9 112 2.8 108 Reduced code 10.2 127 Coremark 10.9 136 Dhrystone 2.1 11.0 Fibonacci 10.5 131 9.9 124 Reduced code 272 136 Coremark 291 145 Dhrystone 2.1 302 Fibonacci 269 135 While(1) 269 135 While(1) While(1) (1) Supply current in fHCLK = fMSI = 2 MHz IDD(LPRun) Low-power all peripherals disable run TYP Unit Code (1) Range 1 fHCLK = 80 MHz Symbol TYP mA mA µA 119 137 151 µA/MHz µA/MHz µA/MHz 1. Reduced code used for characterization results provided in Table 25, Table 26, Table 27. DocID025976 Rev 3 105/229 204 Electrical characteristics STM32L476xx Table 29. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable Conditions Parameter - IDD(Run) Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Supply current in fHCLK = fMSI = 2 MHz IDD(LPRun) Low-power all peripherals disable run TYP Unit Voltage scaling Range 1 Range 2 fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP Code Unit 25 °C 25 °C Reduced code(1) 3.1 119 Coremark 2.9 111 Dhrystone 2.1 2.8 Fibonacci 2.7 104 While(1) 2.6 100 Reduced code 10.0 125 Coremark 9.4 (1) Dhrystone 2.1 9.1 Fibonacci 9.0 mA 111 µA/MHz 117 mA 114 µA/MHz 112 While(1) 9.3 116 Reduced code(1) 358 179 Coremark 392 Dhrystone 2.1 390 196 Fibonacci 385 192 While(1) 385 192 µA 195 µA/MHz 1. Reduced code used for characterization results provided in Table 25, Table 26, Table 27. Table 30. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 Conditions Parameter - IDD(Run) fHCLK = fHSE up to 48 MHz included, Supply bypass mode current in PLL ON above Run mode 48 MHz all peripherals disable Voltage scaling Range 1 Range 2 fHCLK = 80 MHz fHCLK = 26 MHz Symbol Supply current in fHCLK = fMSI = 2 MHz IDD(LPRun) Low-power all peripherals disable run TYP Unit Code Unit 25 °C 25 °C 2.9 111 Reduced code(1) Coremark 2.9 Dhrystone 2.1 2.9 111 mA 111 Fibonacci 2.6 100 While(1) 2.6 100 Reduced code(1) 10.2 127 Coremark 10.4 Dhrystone 2.1 10.3 Fibonacci 9.6 129 µA/MHz 120 9.3 116 Reduced code(1) 242 121 Coremark 242 121 µA Dhrystone 2.1 242 Fibonacci 225 112 While(1) 242 121 DocID025976 Rev 3 µA/MHz 130 mA While(1) 1. Reduced code used for characterization results provided in Table 25, Table 26, Table 27. 106/229 TYP 121 µA/MHz Conditions Symbol Parameter - Voltage scaling Unit fHCLK 26 MHz IDD(Sleep) DocID025976 Rev 3 IDD(LPSleep) 25 °C 55 °C 85 °C 0.92 1.07 0.96 105 °C 125 °C 25 °C 1.25 1.59 1.012 55 °C 85 °C 1.14 1.36 105 °C 125 °C 1.77 2.40 16 MHz 0.61 0.65 0.75 0.92 1.27 0.69 0.78 0.97 1.32 2.04 8 MHz 0.36 0.40 0.50 0.66 1.01 0.42 0.50 0.68 1.03 1.75 4 MHz 0.24 0.27 0.37 0.53 0.87 0.28 0.36 0.54 0.89 1.60 2 MHz 0.18 0.20 0.30 0.47 0.81 0.215 0.29 0.46 0.82 1.53 1 MHz 0.15 0.17 0.27 0.43 0.77 0.18 0.25 0.44 0.78 1.49 100 kHz 0.12 0.14 0.24 0.41 0.74 0.15 0.21 0.39 0.74 1.44 80 MHz 2.96 3.00 3.13 3.33 3.73 3.26 3.43 3.72 4.13 4.97 72 MHz 2.69 2.73 2.85 3.05 3.45 2.96 3.21 3.50 3.71 4.54 64 MHz 2.41 2.45 2.58 2.77 3.17 2.65 2.88 3.17 3.58 4.21 Range 1 48 MHz 1.88 1.93 2.07 2.27 2.67 2.10 2.27 2.41 2.83 3.66 32 MHz 1.30 1.35 1.48 1.68 2.08 1.43 1.56 1.85 2.26 3.10 24 MHz 1.01 1.05 1.17 1.37 1.76 1.11 1.23 1.52 1.93 2.77 16 MHz 0.71 0.75 0.87 1.07 1.45 0.80 0.90 1.19 1.60 2.44 2 MHz 96 126 233 412 775 130 202 402 777 1527 1 MHz 65 94 202 381 742 95 166 358 733 1483 400 kHz 43 73 181 359 718 75 138 331 706 1456 100 kHz 33 63 171 348 708 65 128 322 691 1441 Range 2 Supply current in sleep mode, MAX(1) TYP fHCLK = fHSE up to 48 MHz included, bypass mode pll ON above 48 MHz all peripherals disable Supply current in =f f low-power HCLK MSI all peripherals disable sleep mode mA µA 107/229 Electrical characteristics 1. Guaranteed by characterization results, unless otherwise specified. STM32L476xx Table 31. Current consumption in Sleep and Low-power sleep modes, Flash ON Conditions Symbol Parameter - IDD(LPSleep ) Supply current in low-power sleep mode Voltage scaling fHCLK = fMSI all peripherals disable MAX(1) TYP Unit fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 2 MHz 81 110 217 395 754 115 182 375 750 1500 1 MHz 50 78 185 362 720 80 149 342 717 1456 400 kHz 28 57 163 340 698 60 122 314 689 1429 100 kHz 18 47 155 332 686 50 114 313 688 1438 µA Electrical characteristics 108/229 Table 32. Current consumption in Low-power sleep modes, Flash in power-down 1. Guaranteed by characterization results, unless otherwise specified. DocID025976 Rev 3 STM32L476xx Symbol Parameter Supply current in Stop 1 IDD (Stop 1) mode, RTC disabled Conditions - - Regulator in low- LCD power mode disabled LCD Regulator in low- enabled(2) clocked by power mode LSI DocID025976 Rev 3 LCD disabled RTC clocked by LSI, regulator in low-power mode LCD disabled LCD disabled VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 6.59 24.7 92.7 208 437 16 62 232 520 1093 2.4 V 6.65 24.8 92.9 209 439 17 62 232 523 1098 3V 6.65 24.9 93.3 210 442 17 62 233 525 1105 3.6 V 6.70 25.1 93.8 212 447 17 63 235 530 1118 1.8 V 7.00 25.2 97.2 219 461 18 63 243 548 1153 2.4 V 7.14 25.4 97.5 220 463 18 64 244 550 1158 3V 7.24 25.7 97.7 221 465 18 64 244 553 1163 3.6 V 7.36 26.1 98.7 223 471 18 65 247 558 1178 1.8 V 6.88 25.0 93.1 209 439 17 63 233 523 1098 2.4 V 7.02 25.2 93.7 210 441 18 63 234 525 1103 3V 7.12 25.4 94.2 212 444 18 64 236 530 1110 3.6 V 7.25 25.7 95.2 214 449 18 64 238 535 1123 1.8 V 7.01 26.1 99.0 223 467 18 65 248 558 1168 2.4 V 7.14 26.3 99.6 225 470 18 66 249 563 1175 3V 7.31 26.6 100.0 226 474 18 67 250 565 1185 3.6 V 7.41 26.9 102.0 229 480 19 67 255 573 1200 1.8 V 6.91 25.2 93.4 210 440 17 63 234 525 1100 2.4 V 7.04 25.3 94.2 211 443 18 63 236 528 1108 3V 7.19 25.7 95.0 212 446 18 64 238 530 1115 3.6 V 7.97 26.0 96.1 215 451 20 65 240 538 1128 1.8 V 6.85 25.0 93.0 208.3 - 17 63 233 521 - 2.4 V 6.94 25.1 93.2 209.3 - 17 63 233 523 - 3V 7.10 25.2 93.6 210.3 - 18 63 234 526 - 3.6 V 7.34 25.4 94.1 212.3 - 18 64 235 531 - Unit µA µA 109/229 Electrical characteristics Supply current IDD (Stop 1 in stop 1 with RTC) mode, RTC clocked by RTC enabled LSE bypassed at 32768 Hz, regulator in lowpower mode RTC clocked by LSE quartz(3) in low drive mode, regulator in lowpower mode LCD enabled(2) MAX(1) TYP STM32L476xx Table 33. Current consumption in Stop 1 mode Symbol Parameter Conditions - - wakeup clock MSI = 48 MHz, Supply current Voltage Range 1 IDD (wakeup during wakeup clock MSI = 4 MHz, from Stop1) wakeup from Voltage Range 2 Stop 1 wakeup clock HSI16 = 16 MHz, Voltage Range 1 MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 3V 1.47 - - - - 3V 1.7 - - - - 3V 1.62 - - - - - Unit mA Electrical characteristics 110/229 Table 33. Current consumption in Stop 1 mode (continued) 1. Guaranteed by characterization results, unless otherwise specified. 2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. DocID025976 Rev 3 STM32L476xx Symbol Parameter Conditions - VDD Supply current in IDD (Stop 1) Main regulator ON Stop 1 mode, RTC disabled MAX(1) TYP 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 108 132 217 356 631 153 213 426 773 1461 2.4 V 110 134 219 358 634 158 218 431 778 1468 3V 111 135 220 360 637 161 221 433 783 1476 3.6 V 113 137 222 363 642 166 226 438 791(2) 1488 Unit STM32L476xx Table 34. Current consumption in Stop 1 mode with main regulator µA 1. Guaranteed by characterization results, unless otherwise specified. 2. Guaranteed by test in production. Table 35. Current consumption in Stop 2 mode DocID025976 Rev 3 Symbol Parameter Conditions - LCD disabled IDD(Stop 2) Supply current in Stop 2 mode, RTC disabled LCD enabled(3) clocked by LSI MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 1.8 V 1.14 3.77 14.7 34.7 77 2.4 V 1.15 3.86 15 35.5 3V 1.18 3.97 15.4 36.4 105 °C 125 °C 2.7 9 37 87 193 79.1 2.7 10 38 89 198 81.3 2.8 10 39 91 203 (2) 95 213 3.6 V 1.26 4.11 16 38 85.1 3.0 10 40 1.8 V 1.43 3.98 15 35 77.3 3.2 10 38 88 193 2.4 V 1.49 4.07 15.3 35.8 79.4 3.2 10 38 90 199 3V 1.54 4.24 15.7 36.7 81.6 3.3 11 39 92 204 3.6 V 1.75 4.47 16.1 38.3 85.4 3.5 11 40 96 214 Unit µA Electrical characteristics 111/229 Symbol Parameter Conditions 85 °C 3.1 10 38 87 193 79.2 3.2 11 39 89 198 81.4 3.4 11 40 92 204 38.4 85.4 3.6 12 42 96 214 15.1 35.1 77.4 3.3 10 38 88 194 4.32 15.5 35.9 79.5 3.4 11 39 90 199 4.43 15.9 36.8 81.7 3.5 11 40 92 204 1.86 4.65 16.7 38.5 85.5 3.7 12 42 96 214 1.8 V 1.5 4.13 15.2 35.3 77.6 3.2 10 38 88 194 RTC clocked by LSE 2.4 V bypassed at 32768Hz,LCD disabled 3 V 3.6 V 1.63 4.33 15.6 36 79.6 3.4 11 39 90 199 1.79 4.55 16.1 37 81.8 3.6 11 40 93 205 2.04 4.9 16.8 38.7 85.6 3.9 12 42 97 214 1.8 V 1.43 3.99 14.7 35 - 3.2 10 37 88 - 2.4 V 1.54 4.11 15 35.8 - 3.3 10 38 90 - 3V 1.67 4.29 15.5 36.7 - 3.4 11 39 92 - 3.6 V 1.87 4.57 16.2 38.3 - 3.7 11 41 96 - wakeup clock is MSI = 48 MHz, Voltage Range 1 3V 1.9 - - - - wakeup clock is MSI = 4 MHz, Voltage Range 2 3V 2.24 - - - - wakeup clock is HSI16 = 16 MHz, Voltage Range 1 3V 2.1 - - - - RTC clocked by LSI, LCD enabled(3) Supply current in Stop 2 mode, RTC enabled DocID025976 Rev 3 RTC clocked by LSE quartz(4) in low drive mode, LCD disabled IDD(wakeup from Stop2) Supply current during wakeup from Stop 2mode VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 1.8 V 1.42 4.04 15 34.9 77.2 2.4 V 1.5 4.22 15.4 35.7 3V 1.64 4.37 15.8 36.7 3.6 V 1.79 4.65 16.6 1.8 V 1.53 4.07 2.4 V 1.62 3V 1.69 3.6 V 1. Guaranteed by characterization results, unless otherwise specified. 2. Guaranteed by test in production. 3. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD. 4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. - 105 °C 125 °C Unit µA mA STM32L476xx 55 °C - RTC clocked by LSI, LCD disabled IDD(Stop 2 with RTC) MAX(1) TYP Electrical characteristics 112/229 Table 35. Current consumption in Stop 2 mode (continued) Symbol Parameter Supply current in Standby mode (backup IDD(Standby) registers retained), RTC disabled Conditions - no independent watchdog with independent watchdog DocID025976 Rev 3 RTC clocked by LSI, no independent watchdog Supply current in Standby IDD(Standby mode (backup with RTC) registers retained), RTC enabled RTC clocked by LSI, with independent watchdog RTC clocked by LSE bypassed at 32768Hz MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 114 355 1540 4146 10735 176 888 3850 10365 26838 2.4 V 138 407 1795 4828 12451 223 1018 4488 12070 31128 3V 150 486 2074 5589 14291 263 1215 5185 13973 35728 3.6 V 198 618 2608 6928 17499 383 1545 6520 1.8 V 317 - - - - - - 2.4 V 391 - - - - - - 17320 (2) 43748 - - - - - - 3V 438 - - - - - - - - - 3.6 V 566 - - - - - - - - - 1.8 V 377 621 1873 4564 11318 491 1207 4250 10867 27537 2.4 V 464 756 2210 5348 13166 614 1436 4986 12694 31986 3V 572 913 2599 6219 15197 770 1727 5815 14729 36815 3.6 V 722 1144 3253 7724 18696 1012 2176 7294 18275 45184 1.8 V 456 - - - - - - - - - 2.4 V 557 - - - - - - - - - 3V 663 - - - - - - - - - 3.6 V 885 - - - - - - - - - 1.8 V 289 527 1747 4402 11009 - - - - - 2.4 V 396 671 2108 5202 12869 - - - - - 528 853 2531 6095 14915 - - - - - 710 1111 3115 7470 18221 - - - - - 1.8 V 416 640 1862 4479 11908 - - - - - 2.4 V RTC clocked by LSE quartz (3) in low drive mode 3 V 514 796 2193 5236 13689 - - - - - 652 961 2589 6103 15598 - - - - - 3.6 V 821 1226 3235 7551 17947 - - - - - nA nA nA 113/229 Electrical characteristics 3V 3.6 V Unit STM32L476xx Table 36. Current consumption in Standby mode Symbol Conditions Parameter Supply current IDD(SRAM2) to be added in Standby mode (4) when SRAM2 is retained Supply current IDD(wakeup during wakeup from from Standby Standby) mode - VDD - wakeup clock is MSI = 4 MHz MAX(1) TYP 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 235 641 2293 5192 11213 588 1603 5733 12980 28033 2.4 V 237 645 2303 5213 11246 593 1613 5758 13033 28115 3V 236 647 2306 5221 11333 593 1618 5765 13053 28333 3.6 V 235 646 2308 5200 11327 595 1620 5770 13075 28350 3V 1.7 - - - - - Unit nA Electrical characteristics 114/229 Table 36. Current consumption in Standby mode (continued) mA 1. Guaranteed by characterization results, unless otherwise specified. 2. Guaranteed by test in production. DocID025976 Rev 3 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 4. The supply current in Standby with SRAM2 mode is: IDD(Standby) + IDD(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IDD(Standby + RTC) + IDD(SRAM2). Table 37. Current consumption in Shutdown mode Symbol Parameter Supply current in Shutdown mode IDD(Shutdown) (backup registers retained) RTC disabled Conditions - - MAX(1) TYP VDD 25 °C 55 °C 85 °C 1.8 V 29.8 194 1110 3250 9093 2.4 V 44.3 237 1310 3798 3V 64.1 293 1554 4461 3.6 V 112 420 2041 5689 105 °C 125 °C 25 °C 55 °C 85 °C 75 485 2775 10473 111 593 12082 160 733 15186 280 1050 105 °C 125 °C 8125 22733 3275 9495 26183 3885 11153 30205 5103 14223 37965 Unit nA STM32L476xx Symbol Parameter Supply current in Shutdown mode IDD(Shutdown (backup with RTC) registers retained) RTC enabled DocID025976 Rev 3 IDD(wakeup from Shutdown) Supply current during wakeup from Shutdown mode Conditions - RTC clocked by LSE bypassed at 32768 Hz RTC clocked by LSE quartz (2) in low drive mode wakeup clock is MSI = 4 MHz MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 210 378 1299 3437 9357 - - - - - 2.4 V 303 499 1577 4056 10825 - - - - - 3V 422 655 1925 4820 12569 - - - - - 3.6 V 584 888 2511 6158 15706 - - - - - 1.8 V 329 499 1408 3460 - - - - - - 2.4 V 431 634 1688 4064 - - - - - - 3V 554 791 2025 4795 - - - - - - 3.6 V 729 1040 2619 6129 - - - - - - 3V 0.6 - - - - - - - - - Unit STM32L476xx Table 37. Current consumption in Shutdown mode (continued) nA mA 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. Electrical characteristics 115/229 Symbol Parameter Conditions - RTC disabled IDD(VBAT) RTC enabled and Backup domain clocked by LSE supply current bypassed at 32768 Hz DocID025976 Rev 3 RTC enabled and clocked by LSE quartz(2) MAX(1) TYP VBAT 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 73 490 1468 4158 1.8 V 4 29 196 587 1663 10.8 2.4 V 5.27 36 226 673 1884 13.2 90 565 1683 4710 3V 6 42 264 775 2147 15.5 106 660 1938 5368 3.6 V 10 58 323 919 2488 25.8 144 808 2298 6220 1.8 V 183 201 367 729 - - - - - - 2.4 V 268 295 486 901 - - - - - - 3V 376 412 602 1075 - - - - - - 3.6 V 508 558 752 1299 - - - - - - 1.8 V 302 344 521 915 1978 - - - - - 2.4 V 388 436 639 1091 2289 - - - - - 3V 494 549 784 1301 2656 - - - - - 3.6 V 630 692 971 1571 3115 - - - - - Unit Electrical characteristics 116/229 Table 38. Current consumption in VBAT mode nA 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. STM32L476xx STM32L476xx Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 57: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 39: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DDIOx × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDIOx is the I/O supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS CS is the PCB board capacitance including the pad pin. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. DocID025976 Rev 3 117/229 204 Electrical characteristics STM32L476xx On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 39. The MCU is placed under the following conditions: • All I/O pins are in Analog mode • The given value is calculated by measuring the difference of the current consumptions: – when the peripheral is clocked on – when the peripheral is clocked off • Ambient operating temperature and supply voltage conditions summarized in Table 18: Voltage characteristics • The power consumption of the digital part of the on-chip peripherals is given in Table 39. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. Table 39. Peripheral current consumption Range 1 Range 2 Low-power run and sleep Bus Matrix(1) 4.5 3.7 4.1 ADC independent clock domain 0.4 0.1 0.2 ADC AHB clock domain 5.5 4.7 5.5 CRC 0.4 0.2 0.3 DMA1 1.4 1.3 1.4 DMA2 1.5 1.3 1.4 FLASH 6.2 5.2 5.8 FMC 8.9 7.5 8.4 GPIOA(2) 4.8 3.8 4.4 (2) 4.8 4.0 4.6 GPIOC(2) 4.5 3.8 4.3 (2) GPIOD 4.6 3.9 4.4 GPIOE(2) 5.2 4.5 4.9 GPIOF(2) 5.9 4.9 5.7 (2) 4.3 3.8 4.2 (2) GPIOH 0.7 0.6 0.8 OTG_FS independent clock domain 23.2 NA NA OTG_FS AHB clock domain 16.4 NA NA QUADSPI 7.8 6.7 7.3 RNG independent clock domain 2.2 NA NA RNG AHB clock domain 0.6 NA NA SRAM1 0.9 0.8 0.9 Peripheral GPIOB AHB GPIOG 118/229 DocID025976 Rev 3 Unit µA/MHz STM32L476xx Electrical characteristics Table 39. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep SRAM2 1.6 1.4 1.6 TSC 1.8 1.4 1.6 118.5 77.3 87.6 AHB to APB1 bridge 0.9 0.7 0.9 CAN1 4.6 4.0 4.4 DAC1 2.4 1.9 2.2 I2C1 independent clock domain 3.7 3.1 3.2 I2C1 APB clock domain 1.3 1.1 1.5 I2C2 independent clock domain 3.7 3.0 3.2 I2C2 APB clock domain 1.4 1.1 1.5 I2C3 independent clock domain 2.9 2.3 2.5 I2C3 APB clock domain 0.9 0.9 1.1 LCD 1.0 0.8 0.9 LPUART1 independent clock domain 2.1 1.6 2.0 LPUART1 APB clock domain 0.6 0.6 0.6 LPTIM1 independent clock domain 3.3 2.6 2.9 LPTIM1 APB clock domain 0.9 0.8 1.0 LPTIM2 independent clock domain 3.1 2.7 2.9 LPTIM2 APB clock domain 0.8 0.6 0.7 OPAMP 0.4 0.4 0.3 PWR 0.5 0.5 0.4 SPI2 1.8 1.6 1.6 SPI3 2.1 1.7 1.8 SWPMI1 independent clock domain 2.3 1.8 2.2 SWPMI1 APB clock domain 1.1 1.1 1.0 TIM2 6.8 5.7 6.3 TIM3 5.4 4.6 5.0 TIM4 5.2 4.4 4.9 TIM5 6.5 5.5 6.1 TIM6 1.1 1.0 1.0 TIM7 1.1 0.9 1.0 Peripheral AHB All AHB Peripherals (3) APB1 DocID025976 Rev 3 Unit µA/MHz µA/MHz 119/229 204 Electrical characteristics STM32L476xx Table 39. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep USART2 independent clock domain 4.1 3.6 3.8 USART2 APB clock domain 1.4 1.1 1.5 USART3 independent clock domain 4.7 4.1 4.2 USART3 APB clock domain 1.5 1.3 1.7 UART4 independent clock domain 3.9 3.2 3.5 UART4 APB clock domain 1.5 1.3 1.6 UART5 independent clock domain 3.9 3.2 3.5 UART5 APB clock domain 1.3 1.2 1.4 WWDG 0.5 0.5 0.5 All APB1 on 84.2 70.7 80.2 AHB to APB2 bridge(4) 1.0 0.9 0.9 DFSDM 5.6 4.6 5.3 FW 0.7 0.5 0.7 SAI1 independent clock domain 2.6 2.1 2.3 SAI1 APB clock domain 2.1 1.8 2.0 SAI2 independent clock domain 3.3 2.7 3.0 SAI2 APB clock domain 2.4 2.1 2.2 SDMMC1 independent clock domain 4.7 3.9 4.2 SDMMC1 APB clock domain 2.5 1.9 2.1 SPI1 2.0 1.6 1.9 SYSCFG/VREFBUF/COMP 0.6 0.4 0.5 TIM1 8.3 6.9 7.9 TIM8 8.6 7.1 8.1 TIM15 4.1 3.4 3.9 TIM16 3.0 2.5 2.9 TIM17 3.0 2.4 2.9 USART1 independent clock domain 4.9 4.0 4.4 USART1 APB clock domain 1.5 1.3 1.7 All APB2 on 56.8 43.3 48.2 256.8 189.6 215.5 Peripheral APB1 APB2 ALL 120/229 DocID025976 Rev 3 Unit µA/MHz STM32L476xx Electrical characteristics 1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA). 2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes). 3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1. 4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2. 6.3.6 Wakeup time from low-power modes and voltage scaling transition times The wakeup times given in Table 40 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction. Table 40. Low-power mode wakeup timings(1) Symbol tWUSLEEP Parameter Wakeup time from Sleep mode to Run mode Wakeup time from Low-power sleep tWULPSLEEP mode to Low-power run mode Conditions Typ Max - 6 6 Wakeup in Flash with Flash in power-down during lowpower sleep mode (SLEEP_PD=1 in FLASH_ACR) DocID025976 Rev 3 6 9.3 Unit Nb of CPU cycles 121/229 204 Electrical characteristics STM32L476xx Table 40. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Range 1 Typ Max 5.6 10.9 4.7 10.4 5.7 11.1 4.5 10.5 Wakeup clock MSI = 4 MHz 6.6 14.2 Wakeup clock MSI = 48 MHz 6.2 10.2 6.3 8.99 Wakeup clock MSI = 48 MHz Wakeup clock HSI16 = 16 MHz Regulator in main mode Wakeup clock MSI = 24 MHz during Stop 1 mode Range 2 Wakeup clock HSI16 = 16 MHz Wake up time from Stop 1 mode to Run mode in Flash Range 1 Wakeup clock HSI16 = 16 MHz Regulator in low-power Wakeup clock MSI = 24 MHz mode during Stop 1 mode Range 2 Wakeup clock HSI16 = 16 MHz Range 1 tWUSTOP1 Wake up time from Stop 1 mode to Run mode in SRAM1 Range 1 Wake up time from Stop 1 mode to Lowpower run mode in SRAM1 122/229 8.87 Wakeup clock MSI = 48 MHz 0.7 2.05 1.7 2.8 0.8 2.72 1.7 2.8 Wakeup clock MSI = 4 MHz 2.4 11.32 Wakeup clock MSI = 48 MHz 4.5 5.78 5.5 7.1 5.0 6.5 5.5 7.1 8.2 13.5 12.7 20 Wakeup clock MSI = 4 MHz Regulator in lowpower mode (LPR=1 in PWR_CR1) 6.3 8.0 13.23 Wakeup clock HSI16 = 16 MHz Regulator in low-power Wakeup clock MSI = 24 MHz mode during Stop 1 mode Range 2 Wakeup clock HSI16 = 16 MHz Wake up time from Stop 1 mode to Lowpower run mode in Flash 6.3 10.46 Wakeup clock MSI = 4 MHz Wakeup clock HSI16 = 16 MHz Regulator in main mode Wakeup clock MSI = 24 MHz during Stop 1 mode Range 2 Wakeup clock HSI16 = 16 MHz Wakeup clock MSI = 2 MHz 10.7 21.5 DocID025976 Rev 3 Unit µs STM32L476xx Electrical characteristics Table 40. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Range 1 Wake up time from Stop 2 mode to Run mode in Flash Wakeup clock HSI16 = 16 MHz Regulator in low-power Wakeup clock MSI = 24 MHz mode during Stop 2 mode Range 2 Wakeup clock HSI16 = 16 MHz tWUSTOP2 Range 1 Wake up time from Stop 2 mode to Run mode in SRAM1 Wakeup clock MSI = 48 MHz tWUSTBY SRAM2 tWUSHDN Max 8.0 9.4 7.3 9.3 8.2 9.9 7.3 9.3 Wakeup clock MSI = 4 MHz 10.6 15.8 Wakeup clock MSI = 48 MHz 5.1 6.7 5.7 8 5.5 6.65 5.7 7.53 8.2 16.6 Wakeup clock HSI16 = 16 MHz Regulator in low-power Wakeup clock MSI = 24 MHz mode during Stop 2 mode Range 2 Wakeup clock HSI16 = 16 MHz Wakeup clock MSI = 4 MHz tWUSTBY Typ Wakeup clock MSI = 8 MHz Wakeup time from Standby mode to Range 1 Run mode Wakeup clock MSI = 4 MHz 14.3 20.8 Wakeup clock MSI = 8 MHz 14.3 24.3 Unit µs 20.1 35.5 Wakeup time from Standby with SRAM2 to Run mode Range 1 Wakeup clock MSI = 4 MHz 20.1 38.5 Wakeup time from Shutdown mode to Run mode Range 1 Wakeup clock MSI = 4 MHz 256 330.6 1. Guaranteed by characterization results. Table 41. Regulator modes transition times(1) Symbol tWULPRUN tVOST Parameter Conditions Typ Max Wakeup time from Low-power run mode to Code run with MSI 2 MHz Run mode(2) 5 7 Regulator transition time from Range 2 to Range 1 or Range 1 to Range 2(3) 20 Code run with MSI 24 MHz Unit µs 40 1. Guaranteed by characterization results. 2. Time until REGLPF flag is cleared in PWR_SR2. 3. Time until VOSF flag is cleared in PWR_SR2. DocID025976 Rev 3 123/229 204 Electrical characteristics 6.3.7 STM32L476xx External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 15: High-speed external clock source AC timing diagram. Table 42. High-speed external user clock characteristics(1) Symbol fHSE_ext Parameter Conditions User external clock source frequency Min Typ Max Voltage scaling Range 1 - 8 48 Voltage scaling Range 2 - 8 26 Unit MHz VHSEH OSC_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIOx Voltage scaling Range 1 7 - - Voltage scaling Range 2 18 tw(HSEH) OSC_IN high or low time tw(HSEL) V ns - - 1. Guaranteed by design. Figure 15. High-speed external clock source AC timing diagram WZ+6(+ 9+6(+ 9+6(/ WU+6( WI+6( WZ+6(/ W 7+6( 069 124/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 16. Table 43. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency - - 32.768 1000 VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIOx - 250 - - tw(LSEH) OSC32_IN high or low time tw(LSEL) V ns 1. Guaranteed by design. Figure 16. Low-speed external clock source AC timing diagram WZ/6(+ 9/6(+ 9/6(/ WU/6( WI/6( WZ/6(/ W 7/6( 069 DocID025976 Rev 3 125/229 204 Electrical characteristics STM32L476xx High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 44. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 44. HSE oscillator characteristics(1) Symbol fOSC_IN RF Conditions(2) Min Typ Max Unit Oscillator frequency - 4 8 48 MHz Feedback resistor - - 200 - kΩ - - 5.5 VDD = 3 V, Rm = 30 Ω, CL = 10 pF@8 MHz - 0.44 - VDD = 3 V, Rm = 45 Ω, CL = 10 pF@8 MHz - 0.45 - VDD = 3 V, Rm = 30 Ω, CL = 5 pF@48 MHz - 0.68 - VDD = 3 V, Rm = 30 Ω, CL = 10 pF@48 MHz - 0.94 - VDD = 3 V, Rm = 30 Ω, CL = 20 pF@48 MHz - 1.77 - Startup - - 1.5 mA/V VDD is stabilized - 2 - ms Parameter (3) During startup IDD(HSE) Gm HSE current consumption Maximum critical crystal transconductance tSU(HSE)(4) Startup time mA 1. Guaranteed by design. 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 17). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. 126/229 DocID025976 Rev 3 STM32L476xx Note: Electrical characteristics For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 17. Typical application with an 8 MHz crystal 5HVRQDWRUZLWKLQWHJUDWHG FDSDFLWRUV &/ 26&B,1 0+] UHVRQDWRU &/ 5(;7 I+6( 5) %LDV FRQWUROOHG JDLQ 26&B287 069 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 45. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 45. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol IDD(LSE) Parameter LSE current consumption Maximum critical crystal Gmcritmax gm tSU(LSE)(3) Startup time Conditions(2) Min Typ Max LSEDRV[1:0] = 00 Low drive capability - 250 - LSEDRV[1:0] = 01 Medium low drive capability - 315 - LSEDRV[1:0] = 10 Medium high drive capability - 500 - LSEDRV[1:0] = 11 High drive capability - 630 - LSEDRV[1:0] = 00 Low drive capability - - 0.5 LSEDRV[1:0] = 01 Medium low drive capability - - 0.75 LSEDRV[1:0] = 10 Medium high drive capability - - 1.7 LSEDRV[1:0] = 11 High drive capability - - 2.7 VDD is stabilized - 2 - DocID025976 Rev 3 Unit nA µA/V s 127/229 204 Electrical characteristics STM32L476xx 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 18. Typical application with a 32.768 kHz crystal 5HVRQDWRUZLWKLQWHJUDWHG FDSDFLWRUV &/ 26&B,1 I/6( 'ULYH SURJUDPPDEOH DPSOLILHU N+] UHVRQDWRU 26&B287 &/ 069 Note: 128/229 An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. DocID025976 Rev 3 STM32L476xx 6.3.8 Electrical characteristics Internal clock source characteristics The parameters given in Table 46 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 46. HSI16 oscillator characteristics(1) Symbol fHSI16 TRIM Parameter HSI16 Frequency HSI16 user trimming step DuCy(HSI16)(2) Duty Cycle Conditions Min Typ Max Unit 15.88 - 16.08 MHz Trimming code is not a multiple of 64 0.2 0.3 0.4 Trimming code is a multiple of 64 -4 -6 -8 45 - 55 % -1 - 1 % -2 - 1.5 % -0.1 - 0.05 % VDD=3.0 V, TA=30 °C - % ∆Temp(HSI16) HSI16 oscillator frequency TA= 0 to 85 °C drift over temperature TA= -40 to 125 °C ∆VDD(HSI16) HSI16 oscillator frequency VDD=1.62 V to 3.6 V drift over VDD tsu(HSI16)(2) HSI16 oscillator start-up time - - 0.8 1.2 μs tstab(HSI16)(2) HSI16 oscillator stabilization time - - 3 5 μs IDD(HSI16)(2) HSI16 oscillator power consumption - - 155 190 μA 1. Guaranteed by characterization results. 2. Guaranteed by design. DocID025976 Rev 3 129/229 204 Electrical characteristics STM32L476xx Figure 19. HSI16 frequency versus temperature 0+] PLQ PHDQ & PD[ 06Y9 130/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics Multi-speed internal (MSI) RC oscillator Table 47. MSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Range 0 99 100 101 Range 1 198 200 202 Range 2 396 400 404 Range 3 792 800 808 Range 4 0.99 1 1.01 Range 5 1.98 2 2.02 Range 6 3.96 4 4.04 Range 7 7.92 8 8.08 Range 8 15.8 16 16.16 Range 9 23.8 24 24.4 Range 10 31.7 32 32.32 Range 11 47.5 48 48.48 Range 0 - 98.304 - Range 1 - 196.608 - Range 2 - 393.216 - Range 3 - 786.432 - Range 4 - 1.016 - PLL mode Range 5 XTAL= 32.768 kHz Range 6 - 1.999 - - 3.998 - Range 7 - 7.995 - Range 8 - 15.991 - Range 9 - 23.986 - Range 10 - 32.014 - Range 11 - 48.005 - -3.5 - 3 -8 - 6 MSI mode fMSI ∆TEMP(MSI)(2) MSI frequency after factory calibration, done at VDD=3 V and TA=30 °C MSI oscillator frequency drift over temperature MSI mode TA= -0 to 85 °C TA= -40 to 125 °C DocID025976 Rev 3 Unit kHz MHz kHz MHz % 131/229 204 Electrical characteristics STM32L476xx Table 47. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD=1.62 V to 3.6 V -1.2 - VDD=2.4 V to 3.6 V -0.5 - VDD=1.62 V to 3.6 V -2.5 - VDD=2.4 V to 3.6 V -0.8 - VDD=1.62 V to 3.6 V -5 - VDD=2.4 V to 3.6 V -1.6 - TA= -40 to 85 °C - 1 2 TA= -40 to 125 °C - 2 4 Range 0 to 3 ∆VDD(MSI) (2) MSI oscillator frequency drift MSI mode over VDD (reference is 3 V) Range 4 to 7 Range 8 to 11 ∆FSAMPLING (MSI)(2)(6) Frequency variation in MSI mode sampling mode(3) P_USB Jitter(MSI)(6) Period jitter for USB clock(4) MT_USB Jitter(MSI)(6) Medium term jitter PLL mode for USB clock(5) Range 11 CC jitter(MSI)(6) P jitter(MSI)(6) tSU(MSI)(6) tSTAB(MSI)(6) 132/229 PLL mode Range 11 Max Unit 0.5 0.7 % 1 for next transition - - - 3.458 for paired transition - - - 3.916 for next transition - - - 2 for paired transition - - - 1 % ns ns RMS cycle-tocycle jitter PLL mode Range 11 - - 60 - ps RMS Period jitter PLL mode Range 11 - - 50 - ps Range 0 - - 10 20 Range 1 - - 5 10 Range 2 - - 4 8 Range 3 - - 3 7 Range 4 to 7 - - 3 6 Range 8 to 11 - - 2.5 6 10 % of final frequency - - 0.25 500 5 % of final frequency - - 0.5 1.25 1 % of final frequency - - - 2.5 MSI oscillator start-up time MSI oscillator stabilization time PLL mode Range 11 DocID025976 Rev 3 us ms STM32L476xx Electrical characteristics Table 47. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(6) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Min Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.5 25 Range 8 - - 62 80 Range 9 - - 85 110 Range 10 - - 110 130 Range 11 - - 155 190 Unit µA 1. Guaranteed by characterization results. 2. This is a deviation for an individual part once the initial frequency has been measured. 3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable. 4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter of MSI @48 MHz clock. 5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles. For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28 cycles. For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over 56 cycles. 6. Guaranteed by design. DocID025976 Rev 3 133/229 204 Electrical characteristics STM32L476xx Figure 20. Typical current consumption versus MSI frequency Low-speed internal (LSI) RC oscillator Table 48. LSI oscillator characteristics(1) Symbol fLSI tSU(LSI)(2) tSTAB(LSI)(2) IDD(LSI)(2) Parameter LSI Frequency Conditions Min Typ Max VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34 - - 80 130 μs 5% of final frequency - 125 180 μs - - 110 180 nA LSI oscillator startup time LSI oscillator stabilisation time LSI oscillator power consomption Unit kHz 1. Guaranteed by characterization results. 2. Guaranteed by design. 6.3.9 PLL characteristics The parameters given in Table 49 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 21: General operating conditions. 134/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics Table 49. PLL, PLLSAI1, PLLSAI2 characteristics(1) Symbol fPLL_IN Parameter Conditions Min Typ Max Unit (2) - 4 - 16 MHz - 45 - 55 % Voltage scaling Range 1 2.0645 - 80 Voltage scaling Range 2 2.0645 - 26 Voltage scaling Range 1 8 - 80 Voltage scaling Range 2 8 - 26 Voltage scaling Range 1 8 - 80 Voltage scaling Range 2 8 - 26 Voltage scaling Range 1 64 - 344 Voltage scaling Range 2 64 - 128 - 15 40 - 40 - - 30 - VCO freq = 64 MHz - 150 200 VCO freq = 96 MHz - 200 260 VCO freq = 192 MHz - 300 380 VCO freq = 344 MHz - 520 650 PLL input clock PLL input clock duty cycle fPLL_P_OUT PLL multiplier output clock P fPLL_Q_OUT PLL multiplier output clock Q fPLL_R_OUT PLL multiplier output clock R fVCO_OUT tLOCK Jitter IDD(PLL) PLL VCO output PLL lock time RMS cycle-to-cycle jitter RMS period jitter PLL power consumption on VDD(1) System clock 80 MHz MHz MHz MHz MHz μs ±ps μA 1. Guaranteed by design. 2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the 3 PLLs. DocID025976 Rev 3 135/229 204 Electrical characteristics 6.3.10 STM32L476xx Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 50. Flash memory characteristics(1) Symbol Parameter Conditions Typ Max Unit tprog 64-bit programming time - 81.69 90.76 µs tprog_row one row (32 double word) programming time normal programming 2.61 2.90 fast programming 1.91 2.12 tprog_page one page (2 Kbyte) programming time normal programming 20.91 23.24 fast programming 15.29 16.98 22.02 24.47 normal programming 5.35 5.95 fast programming 3.91 4.35 22.13 24.59 Write mode 3.4 - Erase mode 3.4 - Write mode 7 (for 2 μs) - Erase mode 7 (for 41 μs) - tERASE tprog_bank tME IDD Page (2 KB) erase time one bank (512 Kbyte) programming time - Mass erase time (one or two banks) - Average consumption from VDD Maximum current (peak) ms s ms mA 1. Guaranteed by design. Table 51. Flash memory endurance and data retention Symbol NEND Parameter Endurance Conditions TA = –40 to +105 °C 1 kcycle(2) Data retention 10 kcycles 30 at TA = 105 °C 15 1 kcycle(2) at TA = 125 °C 7 (2) (2) at TA = 55 °C 30 10 kcycles(2) at TA = 85 °C 15 10 kcycles 10 kcycles (2) at TA = 105 °C 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. 136/229 Unit at TA = 85 °C 1 kcycle tRET Min(1) DocID025976 Rev 3 10 Years STM32L476xx 6.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 52. They are based on the EMS levels and classes defined in application note AN1709. Table 52. EMS characteristics Conditions Level/ Class Symbol Parameter VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 80 MHz, conforming to IEC 61000-4-2 3B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 80 MHz, conforming to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) DocID025976 Rev 3 137/229 204 Electrical characteristics STM32L476xx Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 53. EMI characteristics Symbol SEMI 6.3.12 Parameter Monitored frequency band Conditions Max vs. [fHSE/fHCLK] Unit fMSI = 24 MHz 8 MHz/ 80 MHz -9 2 -8 3 -10 14 1.5 3.5 0.1 to 30 MHz VDD = 3.6 V, TA = 25 °C, 30 to 130 MHz LQFP144 package Peak level compliant with IEC 130 MHz to 1 GHz 61967-2 EMI Level dBµV - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard. Table 54. ESD absolute maximum ratings Symbol VESD(HBM) Ratings Conditions TA = +25 °C, conforming Electrostatic discharge to ANSI/ESDA/JEDEC voltage (human body model) JS-001 Electrostatic discharge VESD(CDM) voltage (charge device model) TA = +25 °C, conforming to ANSI/ESD S5.3.1 1. Guaranteed by characterization results. 138/229 DocID025976 Rev 3 Class Maximum value(1) 2 2000 Unit V C3 250 STM32L476xx Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin. • A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 55. Electrical sensitivities Symbol LU Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II level A(1) 1. Negative injection is limited to -30 mA for PF0, PF1, PG6, PG7, PG8, PG12, PG13, PG14. 6.3.13 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in Table 56. Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. Table 56. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Unit Negative injection Positive injection Injected current on BOOT0 pin -0 NA(1) Injected current on pins except PA4, PA5, BOOT0 -5 NA(1) Injected current on PA4, PA5 pins -5 0 mA 1. NA: not applicable DocID025976 Rev 3 139/229 204 Electrical characteristics 6.3.14 STM32L476xx I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 57 are derived from tests performed under the conditions summarized in Table 21: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant (except BOOT0). Table 57. I/O static characteristics Symbol VIL(1) Parameter Conditions Min Typ Max I/O input low level voltage except BOOT0 1.62 V<VDDIOx<3.6 V - - 0.3xVDDIOx I/O input low level voltage except BOOT0 1.62 V<VDDIOx<3.6 V - - 0.39xVDDIOx-0.06 I/O input low level voltage except BOOT0 1.08 V<VDDIOx<1.62 V V BOOT0 I/O input low 1.62 V<VDDIOx<3.6 V level voltage VIH(1) Vhys(1) 140/229 Unit - - 0.43xVDDIOx-0.1 - - 0.17xVDDIOx I/O input high level voltage except BOOT0 1.62 V<VDDIOx<3.6 V 0.7xVDDIOx - - I/O input high level voltage except BOOT0 1.62 V<VDDIOx<3.6 V 0.49xVDDIOX+0.26 - - I/O input high level voltage except BOOT0 1.08 V<VDDIOx<1.62 V 0.61xVDDIOX+0.05 - - BOOT0 I/O input high level voltage 1.62 V<VDDIOx<3.6 V 0.77xVDDIOX - - TT_xx, FT_xxx and NRST I/O input hysteresis 1.62 V<VDDIOx<3.6 V - 200 - FT_sx 1.08 V<VDDIOx<1.62 V - 150 - BOOT0 I/O input hysteresis 1.62 V<VDDIOx<3.6 V - 200 - V DocID025976 Rev 3 mV STM32L476xx Electrical characteristics Table 57. I/O static characteristics (continued) Symbol Parameter Conditions Min Typ Max - - ±100 - - 650(1)(4) - - 200(4) VIN ≤ Max(VDDXXX) (2) - - ±150 Max(VDDXXX) ≤ VIN ≤ Max(VDDXXX)+1 V(2) - - 2500(1)(5) Max(VDDXXX)+1 V < VIN ≤ 5.5 V(2)(3)(5) - - 250(5) - - ±150 - - 2000(1) (2) VIN ≤ Max(VDDXXX) Max(VDDXXX) ≤ VIN ≤ FT_xx input leakage Max(VDDXXX)+1 V(2)(3) (1) current Max(VDDXXX)+1 V < VIN ≤ 5.5 V(1)(3) Ilkg FT_lu, FT_u and PC3 IO VIN ≤ Max(VDDXXX)(4) TT_xx input leakage Max(VDDXXX) ≤ VIN < current 3.6 V(4) Unit nA RPU Weak pull-up V = VSS equivalent resistor (6) IN 25 40 55 kΩ RPD Weak pull-down VIN = VDDIOx equivalent resistor(6) 25 40 55 kΩ CIO I/O pin capacitance - 5 - pF - 1. Guaranteed by design. 2. Max(VDDXXX) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table. 3. All TX_xx IO except FT_lu, FT_u and PC3. 4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula: ITotal_Ileak_max = 10 µA + [number of IOs where VIN is applied on the pad] ₓ Ilkg(Max). 5. To sustain a voltage higher than MIN(VDD, VDDA, VDDIO2, VDDUSB, VLCD) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled. 6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). DocID025976 Rev 3 141/229 204 Electrical characteristics STM32L476xx All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 21 for standard I/Os, and in Figure 21 for 5 V tolerant I/Os. Figure 21. I/O input characteristics 77/UHTXLUHPHQW9LKPLQ 9 GL HVWH QSU RGX 7 %DVH %DV G LPX RQV FW &0 LRQ PLQ 9LK PHQ 26UHTX LU [9 [9' G G [9 LOPD[ HPHQW9 '',2 [! RU9'',2 RU 9'',2[ IRU [ ,2 [ [ I ',2[ ! ',2[ IRU9 ' RU IRU [ [9 '',2 ,2 [9'' D[ Q9LOP WLRQ&0 SURGXF HVWHGLQ ,2[ 9 '' ODWLRQ WLR VLPXOD HGRQ 7 26 LUH UHTX [9 '' PLQ W9LK 77/UHTXLUHPHQW9LOPD[ 9 06Y9 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: 142/229 • The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 18: Voltage characteristics). • The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see Table 18: Voltage characteristics). DocID025976 Rev 3 STM32L476xx Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified). Table 58. Output voltage characteristics(1) Symbol VOL VOH Parameter Conditions Min Max - 0.4 VDDIOx-0.4 - - 0.4 2.4 - - 1.3 VDDIOx-1.3 - - 0.45 VDDIOx-0.45 - - 0.35ₓVDDIOx 0.65ₓVDDIOx - |IIO| = 20 mA VDDIOx ≥ 2.7 V - 0.4 |IIO| = 10 mA VDDIOx ≥ 1.62 V - 0.4 |IIO| = 2 mA 1.62 V ≥ VDDIOx ≥ 1.08 V - 0.4 (2) Output low level voltage for an I/O pin CMOS port |IIO| = 8 mA Output high level voltage for an I/O pin V DDIOx ≥ 2.7 V VOH(3) TTL port(2) |IIO| = 8 mA Output high level voltage for an I/O pin V DDIOx ≥ 2.7 V VOL(3) Output low level voltage for an I/O pin VOL(3) VOH VOL (3) (3) Output low level voltage for an I/O pin |IIO| = 20 mA Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V Output low level voltage for an I/O pin VOH(3) |IIO| = 4 mA Output high level voltage for an I/O pin VDDIOx ≥ 1.62 V VOL(3) Output low level voltage for an I/O pin VOH (3) VOLFM+ (3) |IIO| = 2 mA Output high level voltage for an I/O pin 1.62 V ≥ VDDIOx ≥ 1.08 V Output low level voltage for an FT I/O pin in FM+ mode (FT I/O with "f" option) Unit V 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ΣIIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Guaranteed by design. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 22 and Table 59, respectively. Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. DocID025976 Rev 3 143/229 204 Electrical characteristics STM32L476xx Table 59. I/O AC characteristics(1)(2) Speed Symbol Fmax Parameter Maximum frequency 00 Tr/Tf Fmax Output rise and fall time Maximum frequency 01 Tr/Tf 144/229 Output rise and fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 1 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 10 C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 1.5 C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1 C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 52 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 140 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 17 C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37 C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 110 C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 10 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 1 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 50 C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 15 C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 1 C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 9 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 16 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 40 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 4.5 C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 9 C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 21 DocID025976 Rev 3 Unit MHz ns MHz ns STM32L476xx Electrical characteristics Table 59. I/O AC characteristics(1)(2) (continued) Speed Symbol Fmax Parameter Maximum frequency 10 Tr/Tf Fmax Output rise and fall time Maximum frequency 11 Tr/Tf Fm+ Fmax Tf Output rise and fall time Maximum frequency (4) Output fall time Conditions Min Max C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 5 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100(3) C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37.5 C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 5 C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5.8 C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 11 C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 28 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 2.5 C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 5 C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 12 C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 120(3) C=30 pF, 1.62 V≤VDDIOx≤2.7 V - 50 C=30 pF, 1.08 V≤VDDIOx≤1.62 V - 10 C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 180(3) C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 75 C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 10 C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 3.3 C=30 pF, 1.62 V≤VDDIOx≤2.7 V - 6 C=30 pF, 1.08 V≤VDDIOx≤1.62 V - 16 - 1 MHz - 5 ns C=50 pF, 1.6 V≤VDDIOx≤3.6 V Unit MHz ns MHz ns 1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register. Refer to the RM0351 reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design. 3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz. 4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification. DocID025976 Rev 3 145/229 204 Electrical characteristics STM32L476xx Figure 22. I/O AC characteristics definition(1) W I,2RXW W U,2RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLIWW7DQGLIWKHGXW\F\FOHLV U I ZKHQORDGHGE\WKHVSHFLILHGFDSDFLWDQFH 069 1. Refer to Table 59: I/O AC characteristics. 6.3.15 NRST pin characteristics The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU. Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions. Table 60. NRST pin characteristics(1) Symbol Parameter Conditions Min Typ Max - - 0.3ₓVDDIOx Unit VIL(NRST) NRST input low level voltage - VIH(NRST) NRST input high level voltage - 0.7ₓVDDIOx - - Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV RPU Weak pull-up equivalent resistor(2) VIN = VSS 25 40 55 kΩ - - - 70 ns 1.71 V ≤ VDD ≤ 3.6 V 350 - - ns VF(NRST) NRST input filtered pulse VNF(NRST) NRST input not filtered pulse 1. V Guaranteed by design. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order). 146/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics Figure 23. Recommended NRST pin protection ([WHUQDO UHVHWFLUFXLW 9 '' 5 38 1567 ,QWHUQDOUHVHW )LOWHU ) 069 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 60: NRST pin characteristics. Otherwise the reset will not be taken into account by the device. 6.3.16 Analog switches booster Table 61. Analog switches booster characteristics(1) Symbol VDD VBOOST tSU(BOOST) IDD(BOOST) Parameter Min Typ Max Supply voltage 1.62 - 3.6 Boost supply 2.7 - 4 Booster startup time - - 240 Booster consumption for 1.62 V ≤ VDD ≤ 2.0 V - - 250 Booster consumption for 2.0 V ≤ VDD ≤ 2.7 V - - 500 Booster consumption for 2.7 V ≤ VDD ≤ 3.6 V - - 900 Unit V µs µA 1. Guaranteed by design. DocID025976 Rev 3 147/229 204 Electrical characteristics 6.3.17 STM32L476xx Analog-to-Digital converter characteristics Unless otherwise specified, the parameters given in Table 62 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 21: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 62. ADC characteristics(1) (2) Symbol Parameter VDDA Analog supply voltage VREF+ Positive reference voltage VREF- Negative reference voltage fADC ADC clock frequency Min Typ Max Unit - 1.62 - 3.6 V 2 - VDDA V VDDA ≥ 2 V VDDA < 2 V - VDDA V VSSA V Range 1 - - 80 Range 2 - - 26 Resolution = 12 bits - - 5.33 Resolution = 10 bits - - 6.15 Resolution = 8 bits - - 7.27 Resolution = 6 bits - - 8.88 Resolution = 12 bits - - 4.21 Resolution = 10 bits - - 4.71 Resolution = 8 bits - - 5.33 Resolution = 6 bits - - 6.15 fADC = 80 MHz Resolution = 12 bits External trigger frequency - - 5.33 MHz Resolution = 12 bits - - 15 1/fADC Sampling rate for FAST channels fs Sampling rate for SLOW channels fTRIG Conditions MHz Msps Conversion voltage range(2) - 0 - VREF+ V RAIN External input impedance - - - 50 kΩ CADC Internal sample and hold capacitor - - 5 - pF tSTAB Power-up time - tCAL Calibration time tLATR Trigger conversion latency Regular and injected channels without conversion abort VAIN (3) 148/229 fADC = 80 MHz - 1 conversion cycle 1.45 µs 116 1/fADC CKMODE = 00 1.5 2 2.5 CKMODE = 01 - - 2.0 CKMODE = 10 - - 2.25 CKMODE = 11 - - 2.125 DocID025976 Rev 3 1/fADC STM32L476xx Electrical characteristics Table 62. ADC characteristics(1) (2) (continued) Symbol tLATRINJ ts Parameter Conditions Sampling time IDDV_S(ADC) IDDV_D(ADC) Max 2.5 3 3.5 - - 3.0 - - 3.25 - - 3.125 0.03125 - 8.00625 µs - 2.5 - 640.5 1/fADC - - - 20 µs 0.1875 - 8.1625 µs fADC = 80 MHz ADC voltage regulator IDDA(ADC) Typ CKMODE = 00 Trigger conversion latency Injected channels CKMODE = 01 aborting a regular CKMODE = 10 conversion CKMODE = 11 tADCVREG_STUP start-up time tCONV Min Total conversion time (including sampling time) ADC consumption from the VDDA supply ADC consumption from the VREF+ single ended mode ADC consumption from the VREF+ differential mode fADC = 80 MHz Resolution = 12 bits Resolution = 12 bits ts + 12.5 cycles for successive approximation = 15 to 653 fs = 5 Msps - 730 830 fs = 1 Msps - 160 220 fs = 10 ksps - 16 50 fs = 5 Msps - 130 160 fs = 1 Msps - 30 40 fs = 10 ksps - 0.6 2 fs = 5 Msps - 260 310 fs = 1 Msps - 60 70 fs = 10 ksps - 1.3 3 Unit 1/fADC 1/fADC µA µA µA 1. Guaranteed by design 2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V. 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 4: Pinouts and pin description for further details. DocID025976 Rev 3 149/229 204 Electrical characteristics STM32L476xx Equation 1: RAIN max formula TS - – R ADC R AIN < --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 63. Maximum ADC RAIN(1)(2) Resolution 12 bits 10 bits 8 bits 150/229 Sampling cycle @80 MHz Sampling time [ns] @80 MHz 2.5 RAIN max (Ω) Fast channels(3) Slow channels(4) 31.25 100 N/A 6.5 81.25 330 100 12.5 156.25 680 470 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 4700 3900 247.5 3093.75 12000 10000 640.5 8006.75 39000 33000 2.5 31.25 120 N/A 6.5 81.25 390 180 12.5 156.25 820 560 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 5600 4700 247.5 3093.75 12000 10000 640.5 8006.75 47000 39000 2.5 31.25 180 N/A 6.5 81.25 470 270 12.5 156.25 1000 680 24.5 306.25 1800 1500 47.5 593.75 2700 2200 92.5 1156.25 6800 5600 247.5 3093.75 15000 12000 640.5 8006.75 50000 50000 DocID025976 Rev 3 STM32L476xx Electrical characteristics Table 63. Maximum ADC RAIN(1)(2) (continued) Resolution 6 bits Sampling cycle @80 MHz Sampling time [ns] @80 MHz 2.5 RAIN max (Ω) Fast channels(3) Slow channels(4) 31.25 220 N/A 6.5 81.25 560 330 12.5 156.25 1200 1000 24.5 306.25 2700 2200 47.5 593.75 3900 3300 92.5 1156.25 8200 6800 247.5 3093.75 18000 15000 640.5 8006.75 50000 50000 1. Guaranteed by design. 2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V. 3. Fast channels are: PC0, PC1, PC2, PC3, PA0, PA1. 4. Slow channels are: all ADC inputs except the fast channels. DocID025976 Rev 3 151/229 204 Electrical characteristics STM32L476xx Table 64. ADC accuracy - limited test conditions 1(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.33 Msps, VDDA = VREF+ = 3 V, Integral TA = 25 °C linearity error Effective ENOB number of bits Signal-tonoise and SINAD distortion ratio SNR Signal-tonoise ratio Single ended Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential 152/229 Min Typ Max Unit Fast channel (max speed) - 4 5 Slow channel (max speed) - 4 5 Fast channel (max speed) - 3.5 4.5 Slow channel (max speed) - 3.5 4.5 Fast channel (max speed) - 1 2.5 Slow channel (max speed) - 1 2.5 Fast channel (max speed) - 1.5 2.5 Slow channel (max speed) - 1.5 2.5 Fast channel (max speed) - 2.5 4.5 Slow channel (max speed) - 2.5 4.5 Fast channel (max speed) - 2.5 3.5 Slow channel (max speed) - 2.5 3.5 Fast channel (max speed) - 1 1.5 Slow channel (max speed) - 1 1.5 Fast channel (max speed) - 1 1.2 Slow channel (max speed) - 1 1.2 Fast channel (max speed) - 1.5 2.5 Slow channel (max speed) - 1.5 2.5 Fast channel (max speed) - 1 2 Slow channel (max speed) - 1 2 Fast channel (max speed) 10.4 10.5 - Slow channel (max speed) 10.4 10.5 - Fast channel (max speed) 10.8 10.9 - Slow channel (max speed) 10.8 10.9 - Fast channel (max speed) 64.4 65 - Slow channel (max speed) 64.4 65 - Fast channel (max speed) 66.8 67.4 - Slow channel (max speed) 66.8 67.4 - Fast channel (max speed) 65 66 - Slow channel (max speed) 65 66 - Fast channel (max speed) 67 68 - Slow channel (max speed) 67 68 - DocID025976 Rev 3 LSB bits dB STM32L476xx Electrical characteristics Table 64. ADC accuracy - limited test conditions 1(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, VDDA = VREF+ = 3 V, Differential TA = 25 °C Min Typ Max Unit Fast channel (max speed) - -74 -73 Slow channel (max speed) - -74 -73 Fast channel (max speed) - -79 -76 Slow channel (max speed) - -79 -76 dB 1. Guaranteed by design. 2. ADC DC accuracy values are measured after internal calibration. 3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. 4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling. DocID025976 Rev 3 153/229 204 Electrical characteristics STM32L476xx Table 65. ADC accuracy - limited test conditions 2(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity error ADC clock frequency ≤ 80 MHz, Sampling rate ≤ 5.33 Msps, 2 V ≤ VDDA Integral linearity error Effective ENOB number of bits Signal-tonoise and SINAD distortion ratio SNR Signal-tonoise ratio Single ended Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential 154/229 Min Typ Max Unit Fast channel (max speed) - 4 6.5 Slow channel (max speed) - 4 6.5 Fast channel (max speed) - 3.5 5.5 Slow channel (max speed) - 3.5 5.5 Fast channel (max speed) - 1 4.5 Slow channel (max speed) - 1 5 Fast channel (max speed) - 1.5 3 Slow channel (max speed) - 1.5 3 Fast channel (max speed) - 2.5 6 Slow channel (max speed) - 2.5 6 Fast channel (max speed) - 2.5 3.5 Slow channel (max speed) - 2.5 3.5 Fast channel (max speed) - 1 1.5 Slow channel (max speed) - 1 1.5 Fast channel (max speed) - 1 1.2 Slow channel (max speed) - 1 1.2 Fast channel (max speed) - 1.5 3.5 Slow channel (max speed) - 1.5 3.5 Fast channel (max speed) - 1 3 Slow channel (max speed) - 1 2.5 Fast channel (max speed) 10 10.5 - Slow channel (max speed) 10 10.5 - Fast channel (max speed) 10.7 10.9 - Slow channel (max speed) 10.7 10.9 - Fast channel (max speed) 62 65 - Slow channel (max speed) 62 65 - Fast channel (max speed) 66 67.4 - Slow channel (max speed) 66 67.4 - Fast channel (max speed) 64 66 - Slow channel (max speed) 64 66 - Fast channel (max speed) 66.5 68 - Slow channel (max speed) 66.5 68 - DocID025976 Rev 3 LSB bits dB STM32L476xx Electrical characteristics Table 65. ADC accuracy - limited test conditions 2(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion Fast channel (max speed) Single ADC clock frequency ≤ ended Slow channel (max speed) 80 MHz, Sampling rate ≤ 5.33 Msps, Fast channel (max speed) Differential 2 V ≤ VDDA Slow channel (max speed) Min Typ Max Unit - -74 -65 - -74 -67 - -79 -70 - -79 -71 dB 1. Guaranteed by design. 2. ADC DC accuracy values are measured after internal calibration. 3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. 4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling. DocID025976 Rev 3 155/229 204 Electrical characteristics STM32L476xx Table 66. ADC accuracy - limited test conditions 3(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 80 MHz, Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Integral Voltage scaling Range 1 linearity error Effective ENOB number of bits Signal-tonoise and SINAD distortion ratio SNR Signal-tonoise ratio Single ended Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential 156/229 Min Typ Max Unit Fast channel (max speed) - 5.5 7.5 Slow channel (max speed) - 4.5 6.5 Fast channel (max speed) - 4.5 7.5 Slow channel (max speed) - 4.5 5.5 Fast channel (max speed) - 2 5 Slow channel (max speed) - 2.5 5 Fast channel (max speed) - 2 3.5 Slow channel (max speed) - 2.5 3 Fast channel (max speed) - 4.5 7 Slow channel (max speed) - 3.5 6 Fast channel (max speed) - 3.5 4 Slow channel (max speed) - 3.5 5 Fast channel (max speed) - 1.2 1.5 Slow channel (max speed) - 1.2 1.5 Fast channel (max speed) - 1 1.2 Slow channel (max speed) - 1 1.2 Fast channel (max speed) - 3 3.5 Slow channel (max speed) - 2.5 3.5 Fast channel (max speed) - 2 2.5 Slow channel (max speed) - 2 2.5 Fast channel (max speed) 10 10.4 - Slow channel (max speed) 10 10.4 - Fast channel (max speed) 10.6 10.7 - Slow channel (max speed) 10.6 10.7 - Fast channel (max speed) 62 64 - Slow channel (max speed) 62 64 - Fast channel (max speed) 65 66 - Slow channel (max speed) 65 66 - Fast channel (max speed) 63 65 - Slow channel (max speed) 63 65 - Fast channel (max speed) 66 67 - Slow channel (max speed) 66 67 - DocID025976 Rev 3 LSB bits dB STM32L476xx Electrical characteristics Table 66. ADC accuracy - limited test conditions 3(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ Single 80 MHz, ended Sampling rate ≤ 5.33 Msps, 1.65 V ≤ VDDA = VREF+ ≤ Differential 3.6 V, Voltage scaling Range 1 Min Typ Max Unit Fast channel (max speed) - -69 -67 Slow channel (max speed) - -71 -67 Fast channel (max speed) - -72 -71 Slow channel (max speed) - -72 -71 dB 1. Guaranteed by design. 2. ADC DC accuracy values are measured after internal calibration. 3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. 4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling. DocID025976 Rev 3 157/229 204 Electrical characteristics STM32L476xx Table 67. ADC accuracy - limited test conditions 4(1)(2)(3) Symbol Parameter ET Total unadjusted error EO Conditions(4) Single ended Differential Single ended Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity ADC clock frequency ≤ error 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Integral Voltage scaling Range 2 linearity error Effective ENOB number of bits Signal-tonoise and SINAD distortion ratio SNR Signal-tonoise ratio Single ended Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential 158/229 Min Typ Max Unit Fast channel (max speed) - 5 5.4 Slow channel (max speed) - 4 5 Fast channel (max speed) - 4 5 Slow channel (max speed) - 3.5 4.5 Fast channel (max speed) - 2 4 Slow channel (max speed) - 2 4 Fast channel (max speed) - 2 3.5 Slow channel (max speed) - 2 3.5 Fast channel (max speed) - 4 4.5 Slow channel (max speed) - 4 4.5 Fast channel (max speed) - 3 4 Slow channel (max speed) - 3 4 Fast channel (max speed) - 1 1.5 Slow channel (max speed) - 1 1.5 Fast channel (max speed) - 1 1.2 Slow channel (max speed) - 1 1.2 Fast channel (max speed) - 2.5 3 Slow channel (max speed) - 2.5 3 Fast channel (max speed) - 2 2.5 Slow channel (max speed) - 2 2.5 Fast channel (max speed) 10.2 10.5 - Slow channel (max speed) 10.2 10.5 - Fast channel (max speed) 10.6 10.7 - Slow channel (max speed) 10.6 10.7 - Fast channel (max speed) 63 65 - Slow channel (max speed) 63 65 - Fast channel (max speed) 65 66 - Slow channel (max speed) 65 66 - Fast channel (max speed) 64 65 - Slow channel (max speed) 64 65 - Fast channel (max speed) 66 67 - Slow channel (max speed) 66 67 - DocID025976 Rev 3 LSB bits dB STM32L476xx Electrical characteristics Table 67. ADC accuracy - limited test conditions 4(1)(2)(3) (continued) Symbol THD Conditions(4) Parameter Total harmonic distortion ADC clock frequency ≤ 26 MHz, 1.65 V ≤ VDDA = VREF+ ≤ 3.6 V, Voltage scaling Range 2 Single ended Differential Min Typ Max Unit Fast channel (max speed) - -71 -69 Slow channel (max speed) - -71 -69 Fast channel (max speed) - -73 -72 Slow channel (max speed) - -73 -72 dB 1. Guaranteed by design. 2. ADC DC accuracy values are measured after internal calibration. 3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. 4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling. DocID025976 Rev 3 159/229 204 Electrical characteristics STM32L476xx Figure 24. ADC accuracy characteristics 966$ (* ([DPSOHRIDQDFWXDOWUDQVIHUFXUYH 7KHLGHDOWUDQVIHUFXUYH (QGSRLQWFRUUHODWLRQOLQH (7 7RWDO8QDMXVWHG(UURUPD[LPXPGHYLDWLRQ EHWZHHQWKHDFWXDODQGLGHDOWUDQVIHUFXUYHV (2 2IIVHW(UURUPD[LPXPGHYLDWLRQ EHWZHHQWKHILUVWDFWXDOWUDQVLWLRQDQGWKHILUVW LGHDORQH (* *DLQ(UURUGHYLDWLRQEHWZHHQWKHODVW LGHDOWUDQVLWLRQDQGWKHODVWDFWXDORQH (' 'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXP GHYLDWLRQEHWZHHQDFWXDOVWHSVDQGWKHLGHDORQHV (/ ,QWHJUDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW FRUUHODWLRQOLQH (7 (2 (/ (' /6%,'($/ 9''$ 069 Figure 25. Typical connection diagram using the ADC 9''$ 97 5$,1 9$,1 6DPSOHDQGKROG$'&FRQYHUWHU 5$'& $,1[ &SDUDVLWLF 97 ,/$ ELW FRQYHUWHU &$'& 069 1. Refer to Table 62: ADC characteristics for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 13: Power supply scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. 160/229 DocID025976 Rev 3 STM32L476xx 6.3.18 Electrical characteristics Digital-to-Analog converter characteristics Table 68. DAC characteristics(1) Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage for DAC ON - 1.8 - 3.6 VREF+ Positive reference voltage - 1.8 - VDDA VREF- Negative reference voltage - - - connected to VDDA 25 - - DAC output buffer OFF 9.6 11.7 13.8 kΩ DAC output buffer ON - - 50 pF Sample and hold mode - 0.1 1 µF Voltage on DAC_OUT output DAC output buffer ON 0.2 - VREF+ – 0.2 V DAC output buffer OFF 0 - VREF+ Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±0.5LSB, ±1 LSB, ±2 LSB, ±4 LSB, ±8 LSB) ±0.5 LSB - 1.7 3 Normal mode DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ ±1 LSB - 1.6 2.9 ±2 LSB - 1.55 2.85 ±4 LSB - 1.48 2.8 ±8 LSB - 1.4 2.75 Normal mode DAC output buffer OFF, ±1LSB, CL = 10 pF - 2 2.5 Wakeup time from off state (setting the ENx bit in the DAC Control register) until final value ±1 LSB Normal mode DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - 4.2 7.5 Normal mode DAC output buffer OFF, CL ≤ 10 pF - 2 5 Normal mode DAC output buffer ON CL ≤ 50 pF, RL = 5 kΩ, DC - -80 -28 - 0.7 3.5 DAC output buffer ON RO Output Impedance VDAC_OUT tSETTLING tWAKEUP(2) PSRR tSAMP Ileak VSSA 5 Resistive load CSH V connected to VSSA RL CL Unit Capacitive load VDDA supply rejection ratio Sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when DACOUT reaches final value ±1LSB) Output leakage current DAC output buffer ON, CSH = 100 nF DAC_OUT pin connected DAC output buffer OFF, CSH = 100 nF DAC_OUT pin not connected (internal connection only) DAC output buffer OFF Sample and hold mode, DAC_OUT pin connected DocID025976 Rev 3 kΩ µs µs dB ms - 10.5 18 - 2 3.5 µs - - -(3) nA 161/229 204 Electrical characteristics STM32L476xx Table 68. DAC characteristics(1) (continued) Symbol Parameter CIint Internal sample and hold capacitor tTRIM Middle code offset trim time Voffset Middle code offset for 1 trim code step Conditions Min Typ Max Unit - 5.2 7 8.8 pF 50 - - µs VREF+ = 3.6 V - 1500 - VREF+ = 1.8 V - 750 - No load, middle code (0x800) - 315 500 No load, worst code (0xF1C) - 450 670 No load, middle code (0x800) - - 0.2 DAC output buffer ON DAC output buffer ON IDDA(DAC) DAC consumption from VDDA DAC output buffer OFF Sample and hold mode, CSH = 100 nF DAC output buffer ON DAC output buffer OFF IDDV(DAC) DAC consumption from VREF+ - (4) (4) - 185 240 No load, worst code (0xF1C) - 340 400 No load, middle code (0x800) - 155 205 Sample and hold mode, buffer OFF, CSH = 100 nF, worst case - 400 ₓ 185 ₓ Ton/(Ton Ton/(Ton +Toff) +Toff) (4) - (4) 205 ₓ 155 ₓ Ton/(Ton Ton/(Ton +Toff) +Toff) (4) (4) 1. Guaranteed by design. 2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value). 3. Refer to Table 57: I/O static characteristics. 4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0351 reference manual for more details. 162/229 DocID025976 Rev 3 µA 315 ₓ 670 ₓ Ton/(Ton Ton/(Ton +Toff) +Toff) No load, middle code (0x800) Sample and hold mode, buffer ON, CSH = 100 nF, worst case µV µA STM32L476xx Electrical characteristics Figure 26. 12-bit buffered / non-buffered DAC %XIIHUHGQRQEXIIHUHG'$& %XIIHU 5/2$' ELW GLJLWDOWR DQDORJ FRQYHUWHU '$&[B287 &/2$' DLG 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. Table 69. DAC accuracy(1) . Symbol Parameter DNL Differential non linearity (2) - monotonicity 10 bits INL Integral non linearity(3) Offset Offset1 OffsetCal Gain Offset error at code 0x800(3) Offset error at code 0x001(4) Conditions Min Typ Max DAC output buffer ON - - ±2 DAC output buffer OFF - - ±2 guaranteed DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - - ±4 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±4 VREF+ = 3.6 V - - ±12 VREF+ = 1.8 V - - ±25 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±8 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±5 VREF+ = 3.6 V - - ±5 VREF+ = 1.8 V - - ±7 DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - - ±0.5 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±0.5 DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ Offset Error at DAC output buffer ON code 0x800 CL ≤ 50 pF, RL ≥ 5 kΩ after calibration Gain error(5) Unit LSB DocID025976 Rev 3 % 163/229 204 Electrical characteristics STM32L476xx Table 69. DAC accuracy(1) (continued) Symbol TUE TUECal SNR THD SINAD ENOB Parameter Total unadjusted error Total unadjusted error after calibration Signal-to-noise ratio Total harmonic distortion Signal-to-noise and distortion ratio Effective number of bits Conditions Min Typ Max DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - - ±30 DAC output buffer OFF CL ≤ 50 pF, no RL - - ±12 DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ - - ±23 DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ 1 kHz, BW 500 kHz - 71.2 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz BW 500 kHz - 71.6 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - -78 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - -79 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 70.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - 71 - DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 11.4 - DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz - Unit LSB LSB dB dB dB bits 11.5 - 1. Guaranteed by design. 2. Difference between two consecutive codes - 1 LSB. 3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095. 4. Difference between the value measured at Code (0x001) and the ideal value. 5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON. 164/229 DocID025976 Rev 3 STM32L476xx 6.3.19 Electrical characteristics Voltage reference buffer characteristics Table 70. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA VREFBUF_ OUT Analog supply voltage Voltage reference output Degraded mode(2) Normal mode Degraded mode(2) Min Typ Max VRS = 0 2.4 - 3.6 VRS = 1 2.8 - 3.6 VRS = 0 1.65 - 2.4 VRS = 1 1.65 - 2.8 2.048 2.049(3) (3) VRS = 0 2.046 VRS = 1 2.498(3) 2.5 2.502(3) VRS = 0 VDDA-150 mV - VDDA VRS = 1 VDDA-150 mV - VDDA Unit V Trim step resolution - - - ±0.05 ±0.1 % CL Load capacitor - - 0.5 1 1.5 µF esr Equivalent Serial Resistor of Cload - - - - 2 Ω Iload Static load current - - - - 4 mA Iload = 500 µA - 200 1000 Iload = 4 mA - 100 500 500 μA ≤ Iload ≤4 mA Normal mode - 50 500 -40 °C < TJ < +125 °C - - TRIM Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V Iload_reg Load regulation TCoeff Temperature coefficient PSRR tSTART IINRUSH Power supply rejection Start-up time Control of maximum DC current drive on VREFBUF_ OUT during start-up phase vrefint + - - Tcoeff_ vrefint + 50 DC 40 60 - 100 kHz 25 40 - CL = 0.5 µF - 300 350 CL = 1.1 µF - 500 650 CL = 1.5 µF - 650 800 - 8 - - - ppm/mA Tcoeff_ 50 0 °C < TJ < +50 °C ppm/V ppm/ °C dB µs mA (4) DocID025976 Rev 3 165/229 204 Electrical characteristics STM32L476xx Table 70. VREFBUF characteristics(1) (continued) Symbol Parameter VREFBUF IDDA(VREF consumption BUF) from VDDA Conditions Min Typ Max Iload = 0 µA - 16 25 Iload = 500 µA - 18 30 Iload = 4 mA - 35 50 Unit µA 1. Guaranteed by design, unless otherwise specified. 2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA drop voltage). 3. Guaranteed by test in production. 4. To well control inrush current of VREFBUF during start-up phase and scaling change, VDDA voltage should be in the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 0. 166/229 DocID025976 Rev 3 STM32L476xx 6.3.20 Electrical characteristics Comparator characteristics Table 71. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 - 3.6 Comparator input voltage range - 0 - VDDA V VBG(2) Scaler input voltage - VSC Scaler offset voltage - VDDA VIN IDDA(SCALER) Parameter VREFINT - ±5 ±10 mV BRG_EN=0 (bridge disable) - 200 300 nA BRG_EN=1 (bridge enable) - 0.8 1 µA - 100 200 µs VDDA ≥ 2.7 V - - 5 VDDA < 2.7 V Comparator startup time to VDDA ≥ 2.7 V reach propagation delay Medium mode specification VDDA < 2.7 V - - 7 - - 15 - - 25 - - 80 VDDA ≥ 2.7 V - 55 80 VDDA < 2.7 V - 65 100 VDDA ≥ 2.7 V - 0.55 0.9 VDDA < 2.7 V - 0.65 1 - 5 12 - ±5 ±20 No hysteresis - 0 - Low hysteresis - 8 - Medium hysteresis - 15 - High hysteresis - 27 - Static - 400 600 With 50 kHz ±100 mV overdrive square signal - 1200 - Static - 5 7 - 6 - Static - 70 100 With 50 kHz ±100 mV overdrive square signal - 75 - Scaler static consumption from VDDA tSTART_SCALER Scaler startup time High-speed mode tSTART Ultra-low-power mode tD(3) Propagation delay for 200 mV step with 100 mV overdrive High-speed mode Medium mode Ultra-low-power mode Voffset Vhys Comparator offset error Comparator hysteresis Full common mode range Ultra-lowpower mode IDDA(COMP) Unit Comparator consumption from VDDA - Medium mode With 50 kHz ±100 mV overdrive square signal High-speed mode DocID025976 Rev 3 µs ns µs mV mV nA µA 167/229 204 Electrical characteristics STM32L476xx 1. Guaranteed by design, unless otherwise specified. 2. Refer to Table 24: Embedded internal voltage reference. 3. Guaranteed by characterization results. 6.3.21 Operational amplifiers characteristics Table 72. OPAMP characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage(2) - 1.8 - 3.6 V CMIR Common mode input range - 0 - VDDA V 25 °C, No Load on output. - - ±1.5 All voltage/Temp. - - ±3 Normal mode - ±5 - Low-power mode - ±10 - - 0.8 1.1 VIOFFSET Input offset voltage ∆VIOFFSET Input offset voltage drift Offset trim step TRIMOFFSETP at low common TRIMLPOFFSETP input voltage (0.1 ₓ VDDA) - Offset trim step TRIMOFFSETN at high common TRIMLPOFFSETN input voltage (0.9 ₓ VDDA) - ILOAD Drive current ILOAD_PGA Drive current in PGA mode RLOAD Resistive load (connected to VSSA or to VDDA) RLOAD_PGA Resistive load in PGA mode (connected to VSSA or to VDDA) CLOAD Capacitive load CMRR Common mode rejection ratio 168/229 mV μV/°C mV - 1 1.35 - - 500 - - 100 - - 450 - - 50 4 - - Low-power mode 20 - - Normal mode 4.5 - - 40 - - - - 50 Normal mode - -85 - Low-power mode - -90 - Normal mode Low-power mode Normal mode Low-power mode VDDA ≥ 2 V VDDA ≥ 2 V Normal mode µA VDDA < 2 V kΩ VDDA < 2 V Low-power mode - DocID025976 Rev 3 pF dB STM32L476xx Electrical characteristics Table 72. OPAMP characteristics(1) (continued) Symbol PSRR Parameter Power supply rejection ratio Conditions AO VOHSAT Open loop gain (3) High saturation voltage VOLSAT(3) Low saturation voltage φm Phase margin GM Gain margin tWAKEUP Ibias PGA gain(3) Non inverting gain value - Low-power mode CLOAD ≤ 50 pf, RLOAD ≥ 20 kΩ DC 72 90 - 550 1600 2200 100 420 600 250 700 950 40 180 280 - 700 - - 180 - - 300 - - 80 - Normal mode 55 110 - Low-power mode 45 110 - - - - - - - 100 - - 50 Normal mode - 74 - Low-power mode - 66 - Normal mode - 13 - Low-power mode - 20 - Normal mode CLOAD ≤ 50 pf, RLOAD ≥ 4 kΩ follower configuration - 5 10 Low-power mode CLOAD ≤ 50 pf, RLOAD ≥ 20 kΩ follower configuration - 10 30 Dedicated input (BGA132 only) - - -(4) General purpose input (all packages except BGA132) - - -(4) - 2 - - 4 - - 8 - - 16 - Normal mode Low-power mode Normal mode Low-power mode Normal mode Low-power mode Normal mode Low-power mode Wake up time from OFF state. OPAMP input bias current 85 70 Low-power mode SR(3) Max CLOAD ≤ 50 pf, RLOAD ≥ 4 kΩ DC Gain Bandwidth Low-power mode Product Normal mode Slew rate (from 10 and 90% of output voltage) Typ Normal mode Normal mode GBW Min VDDA ≥ 2.4 V (OPA_RANGE = 1) VDDA < 2.4 V (OPA_RANGE = 0) VDDA ≥ 2.4 V VDDA < 2.4 V dB VDDA 100 Iload = max or Rload = min Input at VDDA. VDDA 50 Iload = max or Rload = min Input at 0. - DocID025976 Rev 3 Unit kHz V/ms dB mV ° dB µs nA - 169/229 204 Electrical characteristics STM32L476xx Table 72. OPAMP characteristics(1) (continued) Symbol Rnetwork Parameter R2/R1 internal resistance values in PGA mode(5) Conditions Min Typ Max PGA Gain = 2 - 80/80 - PGA Gain = 4 - 120/ 40 - PGA Gain = 8 - 140/ 20 - PGA Gain = 16 - 150/ 10 - Unit kΩ/kΩ Delta R Resistance variation (R1 or R2) - -15 - 15 % PGA gain error PGA gain error - -1 - 1 % PGA BW Gain = 2 - - GBW/ 2 - PGA bandwidth Gain = 4 for different non inverting gain Gain = 8 - - GBW/ 4 - - - GBW/ 8 - - - GBW/ 16 - Gain = 16 en IDDA(OPAMP)(3) Voltage noise density OPAMP consumption from VDDA MHz Normal mode at 1 kHz, Output loaded with 4 kΩ - 500 - Low-power mode at 1 kHz, Output loaded with 20 kΩ - 600 - Normal mode at 10 kHz, Output loaded with 4 kΩ - 180 - Low-power mode at 10 kHz, Output loaded with 20 kΩ - 290 - - 120 260 - 45 100 Normal mode Low-power mode no Load, quiescent mode nV/√Hz 1. Guaranteed by design, unless otherwise specified. 2. The temperature range is limited to 0 °C-125 °C when VDDA is below 2 V 3. Guaranteed by characterization results. 4. Mostly I/O leakage, when used in analog mode. Refer to Ilkg parameter in Table 57: I/O static characteristics. 5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between OPAMP inverting input and ground. The PGA gain =1+R2/R1 170/229 DocID025976 Rev 3 µA STM32L476xx 6.3.22 Electrical characteristics Temperature sensor characteristics Table 73. TS characteristics Symbol Parameter TL(1) Min Typ Max Unit - ±1 ±2 °C 2.3 2.5 2.7 mV/°C 0.742 0.76 0.785 V VTS linearity with temperature (2) Avg_Slope Average slope Voltage at 30°C (±5 °C)(3) V30 tSTART (TS_BUF)(1) Sensor Buffer Start-up time in continuous mode(4) - 8 15 µs tSTART(1) Start-up time when entering in continuous mode(4) - 70 120 µs tS_temp(1) ADC sampling time when reading the temperature 5 - - µs IDD(TS)(1) Temperature sensor consumption from VDD, when selected by ADC - 4.7 7 µA 1. Guaranteed by design. 2. Guaranteed by characterization results. 3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 8: Temperature sensor calibration values. 4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 6.3.23 VBAT monitoring characteristics Table 74. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 39 - kΩ Q Ratio on VBAT measurement - 3 - - Error on Q -10 - 10 % ADC sampling time when reading the VBAT 12 - - µs Er (1) tS_vbat(1) 1. Guaranteed by design. Table 75. VBAT charging characteristics Symbol RBC Parameter Conditions Battery charging resistor Min Typ Max VBRS = 0 - 5 - VBRS = 1 - 1.5 - DocID025976 Rev 3 Unit kΩ 171/229 204 Electrical characteristics 6.3.24 STM32L476xx LCD controller characteristics The devices embed a built-in step-up converter to provide a constant LCD reference voltage independently from the VDD voltage. An external capacitor Cext must be connected to the VLCD pin to decouple this converter. Table 76. LCD controller characteristics(1) Symbol Parameter Conditions Min Typ Max VLCD LCD external voltage - - 3.6 VLCD0 LCD internal reference voltage 0 - 2.62 - VLCD1 LCD internal reference voltage 1 - 2.76 - VLCD2 LCD internal reference voltage 2 - 2.89 - VLCD3 LCD internal reference voltage 3 - 3.04 - VLCD4 LCD internal reference voltage 4 - 3.19 - VLCD5 LCD internal reference voltage 5 - 3.32 - VLCD6 LCD internal reference voltage 6 - 3.46 - VLCD7 LCD internal reference voltage 7 - 3.62 - Buffer OFF (BUFEN=0 is LCD_CR register) 0.2 - 2 Buffer ON (BUFEN=1 is LCD_CR register) 1 - 2 Supply current from VDD at Buffer OFF (BUFEN=0 is LCD_CR register) VDD = 2.2 V - 3 - Supply current from VDD at Buffer OFF (BUFEN=0 is LCD_CR register) VDD = 3.0 V - 1.5 - Buffer OFF (BUFFEN = 0, PON = 0) - 0.5 - Buffer ON (BUFFEN = 1, 1/2 Bias) - 0.6 - Buffer ON (BUFFEN = 1, 1/3 Bias) - 0.8 - Buffer ON (BUFFEN = 1, 1/4 Bias) - 1 - Cext ILCD (2) IVLCD VLCD external capacitance Supply current from VLCD (VLCD = 3 V) Unit V μF μA μA RHN Total High Resistor value for Low drive resistive network - 5.5 - MΩ RLN Total Low Resistor value for High drive resistive network - 240 - kΩ V44 Segment/Common highest level voltage - VLCD - V34 Segment/Common 3/4 level voltage - 3/4 VLCD - V23 Segment/Common 2/3 level voltage - 2/3 VLCD - V12 Segment/Common 1/2 level voltage - 1/2 VLCD - V13 Segment/Common 1/3 level voltage - 1/3 VLCD - V14 Segment/Common 1/4 level voltage - 1/4 VLCD - V0 Segment/Common lowest level voltage - 0 - 172/229 DocID025976 Rev 3 V STM32L476xx Electrical characteristics 1. Guaranteed by design. 2. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected. 6.3.25 DFSDM characteristics Unless otherwise specified, the parameters given in Table 77 for DFSDM are derived from tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage conditions summarized in Table 21: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (DFSDM_CKINy, DFSDM_DATINy, DFSDM_CKOUT for DFSDM). Table 77. DFSDM characteristics(1) Symbol Parameter Conditions Min Typ Max fDFSDMCLK DFSDM clock - - - fSYSCLK - - 20 (fDFSDMCLK/4) MHz fCKIN (1/TCKIN) Input clock frequency SPI mode (SITP[1:0] = 01) Unit Output clock frequency - - - 20 MHz Output clock DuCyCKOUT frequency duty cycle - 45 50 55 % fCKOUT Input clock high and low time SPI mode (SITP[1:0] = 01), External clock mode (SPICKSEL[1:0] = 0) TCKIN/2-0.5 TCKIN/2 - tsu Data input setup time SPI mode (SITP[1:0]=01), External clock mode (SPICKSEL[1:0] = 0) 0 - - th Data input hold time SPI mode (SITP[1:0]=01), External clock mode (SPICKSEL[1:0] = 0) 2 - - Manchester data period (recovered clock period) Manchester mode (SITP[1:0] = 10 or 11), Internal clock mode (SPICKSEL[1:0] ≠ 0) (CKOUT DIV+1) ₓ TDFSDMCLK - (2 ₓ CKOUTDIV) ₓ TDFSDMCLK twh(CKIN) twl(CKIN) TManchester ns 1. Data based on characterization results, not tested in production. DocID025976 Rev 3 173/229 204 Electrical characteristics STM32L476xx ')6'0B &.,1,1\ ')6'0B'$7$,1\ 63,WLPLQJ63,&.6(/ Figure 16: DFSDM timing diagram WZO WZK WU WI 63,&.6(/ WVX WK 6,73 WVX WK 6,73 ')6'0B&.287 63,&.6(/ WZO WU WZK WI 63,&.6(/ ')6'0B'$7$,1\ WVX ')6'0B'$7$,1\ 0DQFKHVWHUWLPLQJ 63,WLPLQJ63,&.6(/ 63,&.6(/ WK 6,73 WVX WK 6,73 6,73 6,73 5HFRYHUHGFORFN 5HFRYHUHGGDWD 06Y9 6.3.26 Timer characteristics The parameters given in the following tables are guaranteed by design. Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). 174/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics Table 78. TIMx(1) characteristics Symbol tres(TIM) Parameter Timer resolution time Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 80 MHz 12.5 - ns 0 fTIMxCLK/2 MHz 0 40 MHz TIMx (except TIM2 and TIM5) - 16 TIM2 and TIM5 - 32 - 1 65536 tTIMxCLK fTIMxCLK = 80 MHz 0.0125 819.2 µs - - 65536 × 65536 tTIMxCLK fTIMxCLK = 80 MHz - 53.68 s Timer external clock frequency on CH1 to CH4 f TIMxCLK = 80 MHz fEXT ResTIM tCOUNTER tMAX_COUNT Timer resolution 16-bit counter clock period Maximum possible count with 32-bit counter bit 1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17. Table 79. IWDG min/max timeout period at 32 kHz (LSI)(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF /4 0 0.125 512 /8 1 0.250 1024 /16 2 0.500 2048 /32 3 1.0 4096 /64 4 2.0 8192 /128 5 4.0 16384 /256 6 or 7 8.0 32768 Unit ms 1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. Table 80. WWDG min/max timeout value at 80 MHz (PCLK) Prescaler WDGTB Min timeout value Max timeout value 1 0 0.0512 3.2768 2 1 0.1024 6.5536 4 2 0.2048 13.1072 8 3 0.4096 26.2144 DocID025976 Rev 3 Unit ms 175/229 204 Electrical characteristics 6.3.27 STM32L476xx Communication interfaces characteristics I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s • Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0351 reference manual). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O pins support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics: Table 81. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 260(3) ns 1. Guaranteed by design. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered 176/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics SPI characteristics Unless otherwise specified, the parameters given in Table 82 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 21: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 82. SPI characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency Conditions Min Typ Master mode receiver/full duplex 2.7 < VDD < 3.6 V Voltage Range 1 24 Master mode receiver/full duplex 1.71 < VDD < 3.6 V Voltage Range 1 13 Master mode transmitter 1.71 < VDD < 3.6 V Voltage Range 1 40 Slave mode receiver 1.71 < VDD < 3.6 V Voltage Range 1 - - 26(2) Slave mode transmitter/full duplex 1.71 < VDD < 3.6 V Voltage Range 1 16(2) 1.08 < VDDIO2 < 1.32 Unit MHz 40 Slave mode transmitter/full duplex 2.7 < VDD < 3.6 V Voltage Range 1 Voltage Range 2 tsu(NSS) NSS setup time Max 13 V(3) 8 Slave mode, SPI prescaler = 2 4ₓTPCLK - - ns Slave mode, SPI prescaler = 2 2ₓTPCLK - - ns Master mode TPCLK-2 TPCLK TPCLK+2 ns Master mode 3.5 - - Slave mode 3 - - Master mode 6.5 - - Slave mode 3 - - ta(SO) Data output access time Slave mode 9 - 36 ns tdis(SO) Data output disable time Slave mode 9 - 16 ns th(NSS) NSS hold time tw(SCKH) SCK high and low time tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) Data input setup time Data input hold time DocID025976 Rev 3 ns ns 177/229 204 Electrical characteristics STM32L476xx Table 82. SPI characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Slave mode 2.7 < VDD < 3.6 V Voltage Range 1 - 12.5 19 Slave mode 1.71 < VDD < 3.6 V Voltage Range 1 - 12.5 30 Slave mode 1.71 < VDD < 3.6 V Voltage Range 2 - 12.5 33 Slave mode 1.08 < VDDIO2 < 1.32 V(3) - 25 62.5 tv(MO) Master mode - 2.5 12.5 th(SO) Slave mode 9 - - 24 - - 0 - - tv(SO) Data output valid time - - Data output hold time Slave mode 1.08 < VDDIO2 < 1.32 Master mode th(MO) Unit ns V(3) ns 1. Guaranteed by characterization results. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50 %. 3. SPI mapped on Port G. Figure 27. SPI timing diagram - slave mode and CPHA = 0 166LQSXW 6&.,QSXW W68166 &3+$ &32/ &3+$ &32/ WK166 WF6&. WZ6&.+ WZ6&./ W962 WD62 0,62 287387 WK62 06%287 %,7287 06%,1 %,7,1 WU6&. WI6&. WGLV62 /6%287 WVX6, 026, ,1387 /6%,1 WK6, DLF 178/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics Figure 28. SPI timing diagram - slave mode and CPHA = 1 166LQSXW 6&.LQSXW W68166 &3+$ &32/ &3+$ &32/ WK166 WF6&. WZ6&.+ WZ6&./ WK62 WY62 WD62 0,62 287387 06%287 WGLV62 /6%287 WK6, WVX6, 026, ,1387 %,7287 WU6&. WI6&. 06%,1 %,7,1 /6%,1 DLE 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 29. SPI timing diagram - master mode +LJK 166LQSXW 6&.2XWSXW &3+$ &32/ 6&.2XWSXW WF6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX0, 0,62 ,13 87 WZ6&.+ WZ6&./ 06%,1 WU6&. WI6&. %,7,1 /6%,1 WK0, 026, 287387 06%287 WY02 % , 7287 /6%287 WK02 DLF 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. DocID025976 Rev 3 179/229 204 Electrical characteristics STM32L476xx Quad SPI characteristics Unless otherwise specified, the parameters given in Table 83 and Table 84 for Quad SPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 21: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 15 or 20 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics. Table 83. Quad SPI characteristics in SDR mode(1) Symbol FCK 1/t(CK) tw(CKH) tw(CKL) Parameter Quad SPI clock frequency Quad SPI clock high and low time ts(IN) Data input setup time th(IN) Data input hold time tv(OUT) Data output valid time th(OUT) Data output hold time Conditions Min Typ Max 1.71 < VDD< 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 40 1.71 < VDD< 3.6 V, CLOAD = 15 pF Voltage Range 1 - - 48 2.7 < VDD< 3.6 V, CLOAD = 15 pF Voltage Range 1 - - 60 1.71 < VDD < 3.6 V CLOAD = 20 pF Voltage Range 2 - - 26 t(CK)/2-2 - t(CK)/2 t(CK)/2 - t(CK)/2+2 Voltage Range 1 4 - - Voltage Range 2 3.5 - - Voltage Range 1 5.5 - - Voltage Range 2 6.5 - - Voltage Range 1 - 2.5 5 Voltage Range 2 - 3 5 Voltage Range 1 1.5 - - Voltage Range 2 2 - - fAHBCLK= 48 MHz, presc=0 1. Guaranteed by characterization results. 180/229 DocID025976 Rev 3 Unit MHz ns STM32L476xx Electrical characteristics Table 84. QUADSPI characteristics in DDR mode(1) Symbol Parameter FCK 1/t(CK) Quad SPI clock frequency tw(CKH) Quad SPI clock high and low time tw(CKL) tsf(IN);tsr(IN) Data input setup time thf(IN); thr(IN) Data input hold time tvf(OUT);tvr(OUT) Data output valid time thf(OUT); thr(OUT) Data output hold time Conditions Min Typ Max Unit 1.71 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 40 2 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 - - 48 1.71 < VDD < 3.6 V, CLOAD = 15 pF Voltage Range 1 - - 48 1.71 < VDD < 3.6 V CLOAD = 20 pF Voltage Range 2 - - 26 t(CK)/2-2 - t(CK)/2 t(CK)/2 - t(CK)/2+2 3.5 - - 6.5 - - 11 12 15 19 MHz fAHBCLK = 48 MHz, presc=0 Voltage Range 1 and 2 Voltage Range 1 - Voltage Range 2 Voltage Range 1 6 - Voltage Range 2 8 - ns - 1. Guaranteed by characterization results. Figure 30. Quad SPI timing diagram - SDR mode WU&. &ORFN W&. WZ&.+ WY287 WZ&./ WI&. WK287 'DWDRXWSXW ' ' WV,1 'DWDLQSXW ' ' WK,1 ' ' 06Y9 Figure 31. Quad SPI timing diagram - DDR mode WU&. &ORFN 'DWDRXWSXW W&. WYI287 WZ&.+ WKU287 ' WYU287 ' ' WZ&./ WKI287 ' WVI,1 WKI,1 'DWDLQSXW ' ' WI&. ' ' WVU,1 WKU,1 ' ' ' ' 06Y9 DocID025976 Rev 3 181/229 204 Electrical characteristics STM32L476xx SAI characteristics Unless otherwise specified, the parameters given in Table 85 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized inTable 21: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CK,SD,FS). Table 85. SAI characteristics(1) Symbol Parameter Conditions Min Max Unit fMCLK SAI Main clock output - - 50 MHz Master transmitter 2.7 ≤ VDD ≤ 3.6 Voltage Range 1 - 18.5 Master transmitter 1.71 ≤ VDD ≤ 3.6 Voltage Range 1 - 12.5 Master receiver Voltage Range 1 - 25 SAI clock frequency(2) Slave transmitter 2.7 ≤ VDD ≤ 3.6 Voltage Range 1 - 22.5 Slave transmitter 1.71 ≤ VDD ≤ 3.6 Voltage Range 1 - 14.5 Slave receiver Voltage Range 1 - 25 Voltage Range 2 - 12.5 Master mode 2.7 ≤ VDD ≤ 3.6 - 22 Master mode 1.71 ≤ VDD ≤ 3.6 - 40 fCK tv(FS) ns th(FS) FS hold time Master mode 10 - ns tsu(FS) FS setup time Slave mode 1 - ns th(FS) FS hold time Slave mode 2 - ns Master receiver 2.5 - Slave receiver 3 - Master receiver 8 - Slave receiver 4 - tsu(SD_A_MR) tsu(SD_B_SR) th(SD_A_MR) th(SD_B_SR) 182/229 FS valid time MHz Data input setup time Data input hold time DocID025976 Rev 3 ns ns STM32L476xx Electrical characteristics Table 85. SAI characteristics(1) (continued) Symbol tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Parameter Conditions Data output valid time Data output hold time Data output valid time Data output hold time Min Max Slave transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.6 - 22 Slave transmitter (after enable edge) 1.71 ≤ VDD ≤ 3.6 - 34 Slave transmitter (after enable edge) 10 - Master transmitter (after enable edge) 2.7 ≤ VDD ≤ 3.6 - 27 Master transmitter (after enable edge) 1.71 ≤ VDD ≤ 3.6 - 40 Master transmitter (after enable edge) 10 - Unit ns ns ns ns 1. Guaranteed by characterization results. 2. APB clock frequency must be at least twice SAI clock frequency. Figure 32. SAI master timing waveforms F3#+ 3!)?3#+?8 TH&3 3!)?&3?8 OUTPUT TV&3 TH3$?-4 TV3$?-4 3!)?3$?8 TRANSMIT 3LOTN TSU3$?-2 3!)?3$?8 RECEIVE 3LOTN TH3$?-2 3LOTN -36 DocID025976 Rev 3 183/229 204 Electrical characteristics STM32L476xx Figure 33. SAI slave timing waveforms F3#+ 3!)?3#+?8 TW#+(?8 3!)?&3?8 INPUT TW#+,?8 TH&3 TSU&3 TH3$?34 TV3$?34 3!)?3$?8 TRANSMIT 3LOTN TSU3$?32 3!)?3$?8 RECEIVE 3LOTN TH3$?32 3LOTN -36 SDMMC characteristics Unless otherwise specified, the parameters given in Table 86 for SDIO are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 21: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.14: I/O port characteristics for more details on the input/output characteristics. Table 86. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1) Symbol fPP - Parameter Conditions Min Typ Max Unit Clock frequency in data transfer mode - 0 - 50 MHz SDIO_CK/fPCLK2 frequency ratio - - - 4/3 - tW(CKL) Clock low time fPP = 50 MHz 8 10 - ns tW(CKH) Clock high time fPP = 50 MHz 8 10 - ns CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fPP = 50 MHz 2 - - ns tIH Input hold time HS fPP = 50 MHz 4.5 - - ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time HS fPP = 50 MHz - 12 14 ns tOH Output hold time HS fPP = 50 MHz 9 - - ns CMD, D inputs (referenced to CK) in SD default mode 184/229 tISUD Input setup time SD fPP = 50 MHz 2 - - ns tIHD Input hold time SD fPP = 50 MHz 4.5 - - ns DocID025976 Rev 3 STM32L476xx Electrical characteristics Table 86. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fPP = 50 MHz - 4.5 5 ns tOHD Output hold default time SD fPP = 50 MHz 0 - - ns 1. Guaranteed by characterization results. Table 87. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V(1)(2) Symbol fPP - Parameter Conditions Min Typ Max Unit Clock frequency in data transfer mode - 0 - 50 MHz SDIO_CK/fPCLK2 frequency ratio - - - 4/3 - tW(CKL) Clock low time fPP = 50 MHz 8 10 - ns tW(CKH) Clock high time fPP = 50 MHz 8 10 - ns CMD, D inputs (referenced to CK) in eMMC mode tISU Input setup time HS fPP = 50 MHz 0 - - ns tIH Input hold time HS fPP = 50 MHz 5 - - ns CMD, D outputs (referenced to CK) in eMMC mode tOV Output valid time HS fPP = 50 MHz - 13.5 15.5 ns tOH Output hold time HS fPP = 50 MHz 9 - - ns 1. Guaranteed by characterization results. 2. CLOAD = 20pF. Figure 34. SDIO high-speed mode TF TR T# T7#+( T7#+, #+ T/6 T/( $#-$ OUTPUT T)35 T)( $#-$ INPUT AI DocID025976 Rev 3 185/229 204 Electrical characteristics STM32L476xx Figure 35. SD default mode #+ T/6$ T/($ $#-$ OUTPUT AI 186/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics USB characteristics The STM32L476xx USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 88. USB electrical characteristics Symbol VDDUSB Parameter Conditions USB transceiver operating voltage Min 3.0 (1) Typ Max Unit - 3.6 V RPUI Embedded USB_DP pull-up value during idle 900 1250 1600 RPUR Embedded USB_DP pull-up value during reception 1400 2300 3200 28 36 44 ZDRV(2) Output driver impedance(3) Driving high and low Ω Ω 1. The STM32L476xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V voltage range. 2. Guaranteed by design. 3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver. CAN (controller area network) interface Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). DocID025976 Rev 3 187/229 204 Electrical characteristics 6.3.28 STM32L476xx FSMC characteristics Unless otherwise specified, the parameters given in Table 89 to Table 102 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 21, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.14: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 36 through Figure 39 represent asynchronous waveforms and Table 89 through Table 96 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • AddressSetupTime = 0x1 • AddressHoldTime = 0x1 • DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5) • BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. 188/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics Figure 36. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW.% &-#?.% TV./%?.% T W./% T H.%?./% &-#?./% &-#?.7% TV!?.% &-#?!;= T H!?./% !DDRESS TV",?.% T H",?./% &-#?.",;= T H$ATA?.% T SU$ATA?./% TH$ATA?./% T SU$ATA?.% $ATA &-#?$;= T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 DocID025976 Rev 3 189/229 204 Electrical characteristics STM32L476xx Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Min Max 2THCLK-0.5 2THCLK+0.5 0 1 2THCLK-0.5 2THCLK+1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 3.5 th(A_NOE) Address hold time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 2 th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 - tsu(Data_NE) Data to FMC_NEx high setup time THCLK-1 - tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time tsu(Data_NOE) Data to FMC_NOEx high setup time THCLK-0.5 - th(Data_NOE) Data hold time after FMC_NOE high 0 - th(Data_NE) Data hold time after FMC_NEx high 0 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 1 FMC_NADV low time - THCLK+0.5 tw(NADV) Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings(1)(2) Symbol tw(NE) tw(NOE) tw(NWAIT) Parameter Min Max FMC_NE low time 7THCLK-0.5 7THCLK+0.5 FMC_NWE low time 5THCLK-0.5 5THCLK+0.5 FMC_NWAIT low time THCLK-0.5 - 5THCLK+2 - 4THCLK - tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 1. CL = 30 pF. 2. Guaranteed by characterization results. 190/229 DocID025976 Rev 3 Unit ns STM32L476xx Electrical characteristics Figure 37. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms TW.% &-#?.%X &-#?./% TV.7%?.% TW.7% T H.%?.7% &-#?.7% TV!?.% &-#?!;= TH!?.7% !DDRESS TV",?.% &-#?.",;= TH",?.7% .", TV$ATA?.% TH$ATA?.7% $ATA &-#?$;= T V.!$6?.% &-#?.!$6 TW.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter Min Max FMC_NE low time 3THCLK-1 3THCLK+2 FMC_NEx low to FMC_NWE low THCLK-0.5 THCLK+1.5 THCLK-1 THCLK+1 THCLK-0.5 - - 0 THCLK-1 - - 1.5 THCLK-0.5 - - THCLK+4 THCLK+1 - FMC_NEx low to FMC_NADV low - 1 FMC_NADV low time - THCLK+0.5 FMC_NWE low time FMC_NWE high to FMC_NE high hold time FMC_NEx low to FMC_A valid th(A_NWE) Address hold time after FMC_NWE high tv(BL_NE) FMC_NEx low to FMC_BL valid th(BL_NWE) FMC_BL hold time after FMC_NWE high tv(Data_NE) Data to FMC_NEx low to Data valid th(Data_NWE) Data hold time after FMC_NWE high tv(NADV_NE) tw(NADV) Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. DocID025976 Rev 3 191/229 204 Electrical characteristics STM32L476xx Table 92. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)(2) Symbol Parameter Min Max FMC_NE low time 8THCLK+0.5 8THCLK+0.5 FMC_NWE low time 6THCLK-0.5 6THCLK+0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+2 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+2 - tw(NE) tw(NWE) Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 38. Asynchronous multiplexed PSRAM/NOR read waveforms TW.% &-#? .% TV./%?.% T H.%?./% &-#?./% T W./% &-#?.7% TH!?./% TV!?.% &-#? !;= !DDRESS TV",?.% TH",?./% &-#? .",;= .", TH$ATA?.% TSU$ATA?.% T V!?.% &-#? !$;= TSU$ATA?./% TH$ATA?./% $ATA !DDRESS TH!$?.!$6 T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 192/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics Table 93. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) Parameter Min Max FMC_NE low time 3THCLK-0.5 3THCLK+2 FMC_NEx low to FMC_NOE low 2THCLK-0.5 2THCLK+0.5 FMC_NOE low time THCLK+0.5 THCLK+1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 3 0 1 THCLK-0.5 THCLK+1 tv(NADV_NE) FMC_NEx low to FMC_NADV low tw(NADV) FMC_NADV low time th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high 0 - th(A_NOE) Address hold time after FMC_NOE high THCLK-0.5 - th(BL_NOE) FMC_BL time after FMC_NOE high 0 - FMC_NEx low to FMC_BL valid - 2 Data to FMC_NEx high setup time THCLK-2 - tsu(Data_NOE) Data to FMC_NOE high setup time THCLK-1 - Data hold time after FMC_NEx high 0 - th(Data_NOE) Data hold time after FMC_NOE high 0 - tv(BL_NE) tsu(Data_NE) th(Data_NE) Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Table 94. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2) Symbol tw(NE) tw(NOE) Parameter Min Max FMC_NE low time 8THCLK+2 8THCLK+4 FMC_NWE low time 5THCLK-1 5THCLK+1.5 5THCLK+1.5 - 4THCLK+1 - tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. DocID025976 Rev 3 193/229 204 Electrical characteristics STM32L476xx Figure 39. Asynchronous multiplexed PSRAM/NOR write waveforms TW.% &-#? .%X &-#?./% TV.7%?.% TW.7% T H.%?.7% &-#?.7% TH!?.7% TV!?.% &-#? !;= !DDRESS TV",?.% &-#? .",;= .", T V!?.% &-#? !$;= TH",?.7% T V$ATA?.!$6 !DDRESS TH$ATA?.7% $ATA TH!$?.!$6 T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 194/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics Table 95. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Min Max FMC_NE low time 4THCLK-0.5 4THCLK+2 FMC_NEx low to FMC_NWE low THCLK-0.5 THCLK+1 2xTHCLK-1.5 2xTHCLK+1. 5 THCLK-0.5 - FMC_NEx low to FMC_A valid - 3 FMC_NEx low to FMC_NADV low 0 1 THCLK-0.5 THCLK+1 FMC_AD(adress) valid hold time after FMC_NADV high THCLK-2 - th(A_NWE) Address hold time after FMC_NWE high THCLK-1 - th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK+0.5 - - 1.5 - THCLK +4 THCLK +0.5 - tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) tv(BL_NE) Parameter FMC_NWE low time FMC_NWE high to FMC_NE high hold time FMC_NADV low time FMC_NEx low to FMC_BL valid tv(Data_NADV) FMC_NADV high to Data valid th(Data_NWE) Data hold time after FMC_NWE high Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Table 96. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2) Symbol Min Max FMC_NE low time 9THCLK-0.5 9THCLK+2 FMC_NWE low time 7THCLK-1.5 7THCLK+1.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+2 - th(NE_NWAIT) 4THCLK-3 - tw(NE) tw(NWE) Parameter FMC_NEx hold time after FMC_NWAIT invalid Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Synchronous waveforms and timings Figure 40 through Figure 43 represent synchronous waveforms and Table 97 through Table 100 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • BurstAccessMode = FMC_BurstAccessMode_Enable • MemoryType = FMC_MemoryType_CRAM • WriteBurst = FMC_WriteBurst_Enable • CLKDivision = 1 • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM DocID025976 Rev 3 195/229 204 Electrical characteristics STM32L476xx In all timing tables, the THCLK is the HCLK clock period. Figure 40. Synchronous multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &-#?#,+ $ATALATENCY TD#,+,.%X, &-#?.%X T D#,+,.!$6, TD#,+(.%X( TD#,+,.!$6( &-#?.!$6 TD#,+,!6 TD#,+(!)6 &-#?!;= TD#,+,./%, TD#,+(./%( &-#?./% T D#,+,!$6 &-#?!$;= TD#,+,!$)6 TSU!$6#,+( !$;= TH#,+(!$6 TSU!$6#,+( $ TSU.7!)46#,+( &-#?.7!)4 7!)4#&'B 7!)40/,B &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46#,+( TSU.7!)46#,+( TH#,+(!$6 $ TH#,+(.7!)46 TH#,+(.7!)46 TH#,+(.7!)46 -36 196/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics Table 97. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Min Max 2THCLK-1 - - 2 THCLK+0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 - - 3.5 THCLK - - 1.5 THCLK+1 - tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 4 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 0 - th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 2.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 0 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 - Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. DocID025976 Rev 3 197/229 204 Electrical characteristics STM32L476xx Figure 41. Synchronous multiplexed PSRAM write timings WZ&/. %867851 WZ&/. )0&B&/. 'DWDODWHQF\ WG&/./1([/ WG&/.+1([+ )0&B1([ WG&/./1$'9/ WG&/./1$'9+ )0&B1$'9 WG&/.+$,9 WG&/./$9 )0&B$>@ WG&/.+1:(+ WG&/./1:(/ )0&B1:( WG&/./'DWD WG&/./$',9 WG&/./'DWD WG&/./$'9 )0&B$'>@ )0&B1:$,7 :$,7&)* E :$,732/E $'>@ ' WVX1:$,79&/.+ ' WK&/.+1:$,79 WG&/.+1%/+ )0&B1%/ 06Y9 198/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics Table 98. Synchronous multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) Parameter FMC_CLK period Min Max 2THCLK-1 - - 2 THCLK+0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 1 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3.5 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK - - 2 THCLK+1 - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low td(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 4 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 5.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2.5 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK+1 - 0 - 4 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. DocID025976 Rev 3 199/229 204 Electrical characteristics STM32L476xx Figure 42. Synchronous non-multiplexed NOR/PSRAM read timings TW#,+ TW#,+ &-#?#,+ TD#,+,.%X, TD#,+(.%X( $ATALATENCY &-#?.%X TD#,+,.!$6, TD#,+,.!$6( &-#?.!$6 TD#,+(!)6 TD#,+,!6 &-#?!;= TD#,+,./%, TD#,+(./%( &-#?./% TSU$6#,+( TH#,+($6 TSU$6#,+( &-#?$;= TH#,+($6 $ TSU.7!)46#,+( &-#?.7!)4 7!)4#&'B 7!)40/,B $ TH#,+(.7!)46 TSU.7!)46#,+( &-#?.7!)4 7!)4#&'B 7!)40/,B TSU.7!)46#,+( T H#,+(.7!)46 TH#,+(.7!)46 -36 Table 99. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) 200/229 Parameter FMC_CLK period Min Max 2THCLK - - 2.5 THCLK-0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 - - 3.5 THCLK - - 2 THCLK-0.5 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 0 - th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 0 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 - DocID025976 Rev 3 Unit ns STM32L476xx Electrical characteristics 1. CL = 30 pF. 2. Guaranteed by characterization results. Figure 43. Synchronous non-multiplexed PSRAM write timings WZ&/. WZ&/. )0&B&/. WG&/./1([/ WG&/.+1([+ 'DWDODWHQF\ )0&B1([ WG&/./1$'9/ WG&/./1$'9+ )0&B1$'9 WG&/.+$,9 WG&/./$9 )0&B$>@ WG&/.+1:(+ WG&/./1:(/ )0&B1:( WG&/./'DWD WG&/./'DWD )0&B'>@ ' ' )0&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WG&/.+1%/+ WK&/.+1:$,79 )0&B1%/ 06Y9 DocID025976 Rev 3 201/229 204 Electrical characteristics STM32L476xx Table 100. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) Parameter FMC_CLK period Min Max 2THCLK-0.5 - - 2 THCLK+0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2.5 - - 5 THCLK-1 - - 2 THCLK-1 - - 4.5 1.5 - THCLK+1 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) td(CLKL-NWEL) FMC_CLK low to FMC_NWE low td(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low td(CLKL-NBLL) FMC_CLK low to FMC_NBL low td(CLKH-NBLH) FMC_CLK high to FMC_NBL high tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 0 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 - Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. NAND controller waveforms and timings Figure 44 through Figure 47 represent synchronous waveforms, and Table 101 and Table 102 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x02 • COM.FMC_WaitSetupTime = 0x03 • COM.FMC_HoldSetupTime = 0x02 • COM.FMC_HiZSetupTime = 0x03 • ATT.FMC_SetupTime = 0x01 • ATT.FMC_WaitSetupTime = 0x03 • ATT.FMC_HoldSetupTime = 0x02 • ATT.FMC_HiZSetupTime = 0x03 • Bank = FMC_Bank_NAND • MemoryDataWidth = FMC_MemoryDataWidth_16b • ECC = FMC_ECC_Enable • ECCPageSize = FMC_ECCPageSize_512Bytes • TCLRSetupTime = 0 • TARSetupTime = 0 In all timing tables, the THCLK is the HCLK clock period. 202/229 DocID025976 Rev 3 STM32L476xx Electrical characteristics Figure 44. NAND controller waveforms for read access )0&B1&([ $/()0&B$ &/()0&B$ )0&B1:( WK12($/( WG1&(12( )0&B12(15( WVX'12( WK12(' )0&B'>@ 06Y9 Figure 45. NAND controller waveforms for write access )0&B1&([ $/()0&B$ &/()0&B$ WK1:($/( WG1&(1:( )0&B1:( )0&B12(15( WK1:(' WY1:(' )0&B'>@ 06Y9 Figure 46. NAND controller waveforms for common memory read access )0&B1&([ $/()0&B$ &/()0&B$ WK12($/( WG1&(12( )0&B1:( WZ12( )0&B12( WVX'12( WK12(' )0&B'>@ 06Y9 DocID025976 Rev 3 203/229 204 Electrical characteristics STM32L476xx Figure 47. NAND controller waveforms for common memory write access )0&B1&([ $/()0&B$ &/()0&B$ WG1&(1:( WZ1:( WK12($/( )0&B1:( )0&B12( WG'1:( WY1:(' WK1:(' )0&B'>@ 06Y9 Table 101. Switching characteristics for NAND Flash read cycles(1)(2) Symbol Tw(N0E) Parameter FMC_NOE low width Min Max 4THCLK-1 4THCLK+1 Tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 16 - Th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 6 - Td(NCE-NOE) FMC_NCE valid before FMC_NOE low - 3THCLK+1 Th(NOE-ALE) FMC_NOE high to FMC_ALE invalid 2THCLK-2 - Unit ns 1. CL = 30 pF. 2. Guaranteed by characterization results. Table 102. Switching characteristics for NAND Flash write cycles(1)(2) Symbol Tw(NWE) Parameter FMC_NWE low width Max 4THCLK-1 4THCLK+1 - 2.5 Tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid Th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 3THCLK-4 - Td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK-3 - - 3THCLK+1 2THCLK-2 - Td(NCE_NWE) FMC_NCE valid before FMC_NWE low Th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 1. CL = 30 pF. 2. Guaranteed by characterization results. 204/229 Min DocID025976 Rev 3 Unit ns STM32L476xx 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. LQFP144 package information Figure 48. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ & $ PP *$8*(3/$1( ' / ' . $ FFF & / ' ( 3,1 ( ( E 7.1 ,'(17,),&$7,21 H $B0(B9 1. Drawing is not to scale. DocID025976 Rev 3 205/229 226 Package information STM32L476xx Table 103. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.6890 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 206/229 DocID025976 Rev 3 STM32L476xx Package information Figure 49. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DLH 1. Dimensions are expressed in millimeters. DocID025976 Rev 3 207/229 226 Package information STM32L476xx Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 50. LQFP144 marking (package top view) 2SWLRQDOJDWHPDUN 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 670/=*7 'DWHFRGH < :: 3LQLGHQWLILHU 06Y9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 208/229 DocID025976 Rev 3 STM32L476xx 7.2 Package information UFBGA132 package information Figure 51. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package outline & 6HDWLQJSODQH GGG & $ $ $ $ E ( % H = ( $ 0 = ' ' H $ $EDOO LGHQWLILHU %277209,(: EEDOOV HHH 0 & $ % III 0 & $EDOO LQGH[DUHD 7239,(: 8)%*$B$*B0(B9 1. Drawing is not to scale. Table 104. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 0.6000 - - 0.0236 A1 - - 0.1100 - - 0.0043 A2 - 0.1300 - - 0.0051 - A4 - 0.3200 - - 0.0126 - b 0.2400 0.2900 0.3400 0.0094 0.0114 0.0134 D 6.8500 7.0000 7.1500 0.2697 0.2756 0.2815 D1 - 5.5000 - - 0.2165 - E 6.8500 7.0000 7.1500 0.2697 0.2756 0.2815 E1 - 5.5000 - - 0.2165 - e - 0.5000 - - 0.0197 - DocID025976 Rev 3 209/229 226 Package information STM32L476xx Table 104. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max Z - 0.7500 - - 0.0295 - ddd - 0.0800 - - 0.0031 - eee - 0.1500 - - 0.0059 - fff - 0.0500 - - 0.0020 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 52. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package recommended footprint 'SDG 'VP 8)%*$B$*B)3B9 Table 105. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) Dimension 210/229 Recommended values Pitch 0.5 mm Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm Ball diameter 0.280 mm DocID025976 Rev 3 STM32L476xx Package information Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 53. UFBGA132 marking (package top view) 3URGXFWLGHQWLILFDWLRQ 670/ 4*, < :: %DOO$LQGHQWLILHU 'DWHFRGH 5HYLVLRQFRGH 06Y9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID025976 Rev 3 211/229 226 Package information 7.3 STM32L476xx LQFP100 package information Figure 54. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! ! 3%!4).'0,!.% # '!5'%0,!.% $ ! + CCC # , $ , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. Table 106. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol 212/229 Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 DocID025976 Rev 3 STM32L476xx Package information Table 106. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 55. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint AIC 1. Dimensions are expressed in millimeters. Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. DocID025976 Rev 3 213/229 226 Package information STM32L476xx Figure 56. LQFP100 marking (package top view) 3URGXFWLGHQWLILFDWLRQ 670/ 2SWLRQDOJDWHPDUN 9*7 5HYLVLRQFRGH 'DWHFRGH < :: 3LQ LQGHQWLILHU 06Y9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 214/229 DocID025976 Rev 3 STM32L476xx 7.4 Package information WLCSP81 package information Figure 57. WLCSP81 - 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package outline H EEE = $EDOO ORFDWLRQ H $EDOO ORFDWLRQ ' $ H 'HWDLO$ ( H - * %RWWRPYLHZ %XPSVLGH DDD $ ) 7RSYLHZ :DIHUEDFNVLGH $ $ 6LGHYLHZ 'HWDLO$ URWDWHGE\ $ HHH = T FFF0 TGGG0 E =;< = 6HDWLQJSODQH = $=B0(B9 1. Drawing is not to scale. Table 107. WLCSP81- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - A3(2) - 0.025 - - 0.0010 - 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 4.3734 4.4084 4.4434 0.1722 0.1736 0.1749 E 3.7244 3.7594 3.7944 0.1466 0.1480 0.1494 e - 0.400 - - 0.0157 - e1 - 3.200 - - 0.1260 - e2 - 3.200 - - 0.1260 - b (3) DocID025976 Rev 3 215/229 226 Package information STM32L476xx Table 107. WLCSP81- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max F - 0.6042 - - 0.0238 - G - 0.2797 - - 0.0110 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 58. WLCSP81- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package recommended footprint 'SDG 'VP $=B)3B9 Table 108. WLCSP81 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. 216/229 DocID025976 Rev 3 STM32L476xx Package information Figure 59. WLCSP81 marking (package top view) %DOO$LGHQWLILHU /0(< 3URGXFWLGHQWLILFDWLRQ TBD 5HYLVLRQFRGH < :: 'DWHFRGH 06Y9 7.5 WLCSP72 package information Figure 60. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package outline EEE = H ' H H 'HWDLO$ * DDD $ $ $ ) < ( H %RWWRPYLHZ %XPSVLGH ; $EDOOORFDWLRQ 7RSYLHZ :DIHUEDFNVLGH 6LGHYLHZ %XPS HHH = $ E; = ;< = T FFF0 TGGG0 = 6HDWLQJSODQH 'HWDLO$ URWDWHGE\ $5B0(B9 1. Drawing is not to scale. DocID025976 Rev 3 217/229 226 Package information STM32L476xx Table 109. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 4.3734 4.4084 4.4434 0.1722 0.1736 0.1749 E 3.7244 3.7594 3.7944 0.1466 0.1480 0.1494 e - 0.400 - - 0.0157 - e1 - 3.200 - - 0.1260 - e2 - 3.200 - - 0.1260 - F - 0.6042 - - 0.0238 - G - 0.2797 - - 0.0110 - aaa - 0.100 - - 0.0039 - bbb - 0.100 - - 0.0039 - ccc - 0.100 - - 0.0039 - ddd - 0.050 - - 0.0020 - eee - 0.050 - - 0.0020 - A3 (2) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 218/229 DocID025976 Rev 3 STM32L476xx Package information Figure 61. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale package recommended footprint 'SDG 'VP :/&63B$5B)3B9 Table 110. WLCSP72 recommended PCB design rules (0.4 mm pitch BGA) Dimension Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the solder mask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. DocID025976 Rev 3 219/229 226 Package information STM32L476xx Figure 62. WLCSP72 marking (package top view) %DOO$LGHQWLILHU /-*< 3URGXFWLGHQWLILFDWLRQ 5HYLVLRQFRGH 'DWHFRGH < :: 06Y9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 220/229 DocID025976 Rev 3 STM32L476xx LQFP64 package information Figure 63. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*(3/$1( F $ $ 6($7,1*3/$1( & $ $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( E ( 7.6 Package information H :B0(B9 1. Drawing is not to scale. Table 111. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - DocID025976 Rev 3 221/229 226 Package information STM32L476xx Table 111. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 64. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint AIC 1. Dimensions are expressed in millimeters. Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. 222/229 DocID025976 Rev 3 STM32L476xx Package information Figure 65. LQFP64 marking (package top view) 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 670/ 5*7 < :: 'DWHFRGH 3LQLGHQWLILHU 06Y9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID025976 Rev 3 223/229 226 Package information 7.7 STM32L476xx Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 21: General operating conditions. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 112. Package thermal characteristics Symbol ΘJA 7.7.1 Parameter Value Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient LQFP100 - 14 × 14mm 42 Thermal resistance junction-ambient LQFP144 - 20 × 20 mm 32 Thermal resistance junction-ambient UFBGA132 - 7 × 7 mm 55 Thermal resistance junction-ambient WLCSP72 46 Thermal resistance junction-ambient WLCSP81 41 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 7.7.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Part numbering. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. 224/229 DocID025976 Rev 3 STM32L476xx Package information As applications do not commonly use the STM32L476xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Using the values obtained in Table 112 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Section 8: Part numbering. In this case, parts must be ordered at least with the temperature range suffix 6 (see Part numbering). Note: With this given PDmax we can find the TAmax allowed for a given device temperature range (order code suffix 6 or 7). Suffix 6: TAmax = TJmax - (45°C/W × 447 mW) = 105-20.115 = 84.885 °C Suffix 7: TAmax = TJmax - (45°C/W × 447 mW) = 125-20.115 = 104.885 °C Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA × 3.5 V= 70 mW PIOmax = 20 × 8 mA × 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW DocID025976 Rev 3 225/229 226 Package information STM32L476xx Using the values obtained in Table 112 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Part numbering) unless we reduce the power dissipation in order to be able to use suffix 6 parts. Refer to Figure 66 to select the required temperature range (suffix 6 or 7) according to your ambient temperature or power requirements. Figure 66. LQFP64 PD max vs. TA 3'P: 6XIIL[ 6XIIL[ 7$& 226/229 DocID025976 Rev 3 06Y9 STM32L476xx 8 Part numbering Part numbering Table 113. STM32L476xx ordering information scheme Example: STM32 L 476 R G T 6 TR Device family STM32 = ARM® based 32-bit microcontroller Product type L = ultra-low-power Device subfamily 476: STM32L476xx Pin count R = 64 pins J = 72 pins M = 81 pins V = 100 pins Q = 132 pins Z = 144 pins Flash memory size C = 256 KB of Flash memory E = 512 KB of Flash memory G = 1 MB of Flash memory Package T = LQFP ECOPACK®2 I = UFBGA ECOPACK®2 Y = CSP ECOPACK®2 Temperature range 6 = Industrial temperature range, -40 to 85 °C (105 °C junction) 7 = Industrial temperature range, -40 to 105 °C (125 °C junction) 3 = Industrial temperature range, -40 to 125 °C (130 °C junction) Packing TR = tape and reel xxx = programmed parts DocID025976 Rev 3 227/229 228 Revision history 9 STM32L476xx Revision history Table 114. Document revision history Date Revision 29-May-2015 1 Initial release. 15-Jun-2015 2 Updated Table 1: Device summary and Table 71: COMP characteristics. 3 Changed alternate function pin name “SWDAT” into “SWDIO” in all the document. Updated Section 3.9.1: Power supply schemes. Updated Section 3.15.1: Temperature sensor. In all Section 6: Electrical characteristics, renamed table footnotes related to test and characterization. Added Note 2. Updated Table 40: Low-power mode wakeup timings. Updated Table 41: Regulator modes transition times. Updated Table 46: HSI16 oscillator characteristics. Added Table 19: HSI16 frequency versus temperature. Updated Table 47: MSI oscillator characteristics. Updated Table 48: LSI oscillator characteristics. Updated Table 56: I/O current injection susceptibility. Removed first Note in Table 57: I/O static characteristics. Removed second Note in Table 58: Output voltage characteristics. Updated Table 62: ADC characteristics. Updated Table 64: ADC accuracy - limited test conditions 1. Added Table 65: ADC accuracy - limited test conditions 2. Added Table 66: ADC accuracy - limited test conditions 3. Added Table 67: ADC accuracy - limited test conditions 4. Updated Table 69: DAC accuracy. Updated Table 70: VREFBUF characteristics. Added Section 6.3.25: DFSDM characteristics. Updated Section : Quad SPI characteristics. Updated Table 83: Quad SPI characteristics in SDR mode. Updated Table 84: QUADSPI characteristics in DDR mode. Updated Table 88: USB electrical characteristics. Updated Section 7.2: UFBGA132 package information. Updated Section 7.5: WLCSP72 package information. Updated Table 65: LQFP64 marking (package top view). 18-Sep-2015 228/229 Changes DocID025976 Rev 3 STM32L476xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID025976 Rev 3 229/229 229