NVMFS5C612NL D

NVMFS5C612NL
Power MOSFET
60 V, 1.5 mW, 235 A, Single N−Channel
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFS5C612NLWF − Wettable Flank Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(ON) MAX
ID MAX
1.5 mW @ 10 V
60 V
235 A
2.3 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
V
Gate−to−Source Voltage
VGS
±20
V
ID
235
A
Parameter
Continuous Drain
Current RqJC
(Notes 1, 3)
TC = 25°C
Power Dissipation
RqJC (Note 1)
Continuous Drain
Current RqJA
(Notes 1, 2, 3)
Steady
State
TC = 100°C
TC = 25°C
TC = 100°C
TA = 25°C
Power Dissipation
RqJA (Notes 1 & 2)
Pulsed Drain Current
Steady
State
ID
Operating Junction and Storage Temperature
Source Current (Body Diode)
S (1,2,3)
N−CHANNEL MOSFET
A
36
25
PD
TA = 100°C
TA = 25°C, tp = 10 ms
W
167
83
TA = 100°C
TA = 25°C
G (4)
166
PD
D (5,6)
MARKING
DIAGRAM
W
3.8
D
1.9
1
IDM
900
A
TJ, Tstg
−55 to
+175
°C
IS
164
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 17 A)
EAS
451
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
S
S
S
G
D
XXXXXX
AYWZZ
D
D
XXXXXX = 5C612L
XXXXXX = (NVMFS5C612NL) or
XXXXXX = 612LWF
XXXXXX = (NVMFS5C612NLWF)
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case − Steady State
Parameter
RqJC
0.9
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
39
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 3
1
Publication Order Number:
NVMFS5C612NL/D
NVMFS5C612NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
60
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
12.7
VGS = 0 V,
VDS = 60 V
mV/°C
TJ = 25 °C
10
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = ±16 V
VGS(TH)
VGS = VDS, ID = 250 mA
±100
mA
nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
1.2
2.0
−5.76
VGS = 10 V
ID = 50 A
1.2
1.5
VGS = 4.5 V
ID = 50 A
1.65
2.3
gFS
VDS = 15 V, ID = 50 A
V
mV/°C
151
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
6660
VGS = 0 V, f = 1 MHz, VDS = 25 V
2953
pF
45
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 30 V; ID = 50 A
41
Total Gate Charge
QG(TOT)
VGS = 10 V, VDS = 30 V; ID = 50 A
91
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
5
nC
17.1
VGS = 4.5 V, VDS = 30 V; ID = 50 A
Gate−to−Drain Charge
QGD
Plateau Voltage
VGP
10.9
2.9
td(ON)
19
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 4.5 V, VDS = 30 V,
ID = 50 A, RG = 1.0 W
tf
51
ns
47
18
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
VSD
VGS = 0 V,
IS = 50 A
TJ = 25°C
0.78
TJ = 125°C
0.66
tRR
ta
tb
1.2
V
78
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 50 A
QRR
36
ns
42
105
nC
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
NVMFS5C612NL
TYPICAL CHARACTERISTICS
200
200
VGS = 10 V to 3.4 V
160
3.2 V
140
120
3.0 V
100
2.8 V
80
160
60
40
140
120
100
80
TJ = 25°C
60
40
TJ = 125°C
20
0
20
0
0.5
1.0
1.5
2.0
2.5
TJ = −55°C
0
3.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
VDS ≤ 10 V
180
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
180
2.1
2.0
1.9
TJ = 25°C
ID = 50 A
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
4.0
TJ = 25°C
VGS = 4.5 V
VGS = 10 V
10
30
50
70
90
110 130
150 170 190
VGS, GATE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
VGS = 10 V
ID = 40 A
1.7
100,000
IDSS, LEAKAGE (nA)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE (W)
1,000,000
1.9
1.5
1.3
1.1
0.9
0.7
−50 −25
TJ = 150°C
TJ = 125°C
10,000
TJ = 85°C
1000
100
10
0
25
50
75
100
125
150
175
5
15
25
35
45
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
55
NVMFS5C612NL
CISS
7000
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
8000
6000
5000
VGS = 0 V
TJ = 25°C
f = 1 MHz
COSS
4000
3000
2000
1000
CRSS
0
0
10
20
30
40
50
10
30
QT
25
8
20
6
15
4
QGD
QGS
10
VDS = 30 V
TJ = 25°C
ID = 50 A
2
5
0
0
0
60
10
20
30
40
50
60
70
80
90
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
1000
td(off)
46
IS, SOURCE CURRENT (A)
t, TIME (ns)
VGS = 4.5 V
VDD = 30 V
ID = 50 A
tf
tr
100
td(on)
10
41
TJ = 125°C
36
31
26
21
TJ = 25°C
16
11
6
1
TJ = −55°C
1
1
10
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
1000
TC = 25°C
VGS ≤ 10 V
0.01 ms
0.1 ms
TJ(initial) = 25°C
IPEAK (A)
IDS (A)
100
1 ms
dc
10 ms
TJ(initial) = 100°C
10
10
RDS(on) Limit
Thermal Limit
Package Limit
1
1
0.1
1
10
1E−04
100
1E−03
VDS (V)
TIME IN AVALANCHE (s)
Figure 11. Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
1E−02
NVMFS5C612NL
100
R(t) (°C/W)
50% Duty Cycle
10
20%
10%
5%
1
2%
1%
NVMFS5C612NL 650 mm2, 2 oz., Cu Single Layer Pad
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
Marking
Package
Shipping†
NVMFS5C612NLT1G
5C612L
DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFS5C612NLWFT1G
612LWF
DFN5
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
NVMFS5C612NLT3G
5C612L
DFN5
(Pb−Free)
5000 / Tape & Reel
NVMFS5C612NLWFT3G
612LWF
DFN5
(Pb−Free, Wettable Flanks)
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NVMFS5C612NL
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE M
2X
0.20 C
D
A
2
B
D1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
2X
0.20 C
4X
E1
2
q
E
c
1
2
3
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
A1
4
TOP VIEW
C
SEATING
PLANE
DETAIL A
0.10 C
A
0.10 C
SIDE VIEW
0.10
8X b
C A B
0.05
c
DETAIL A
RECOMMENDED
SOLDERING FOOTPRINT*
e/2
1
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
2X
0.495
e
L
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.15
5.00
5.30
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.15
6.30
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
4.560
2X
1.530
4
K
3.200
E2
PIN 5
(EXPOSED PAD)
G
L1
4.530
M
D2
1.330
2X
0.905
1
BOTTOM VIEW
0.965
4X
1.000
4X 0.750
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
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NVMFS5C612NL/D