® RT2070 3 Channel DC/DC Converters +LDO +LSW PMIC with I2C Interface for Industrial/Automotive Application General Description Features The RT2070 is a highly-integrated low-power highperformance analog SOC with PMIC (Power Management IC) in one single chip designed for Industrial/Automotive applications. The RT2070 PMIC includes one high voltage synchronous step-down DC/DC converter, two low voltage synchronous step-down DC/DC converters, one low dropout LDO and one load switch with soft-start control and current limit. All MOSFETs are integrated, and compensation networks are built-in. The RT2070 also uses I2C interface to set timing of power on/off, sequence and discharge function, and includes power good indicator (PGOOD). The RT2070 is an Automotive-Grade Product that is AEC-Q100 Grade 1 Qualified and provides fault condition protections, including over-current protection, undervoltage lockout, over-voltage protection and overtemperature protection. Input Voltage Operating Range is 4.5V to 15V CH1 HV-Step-Down Regulator : VIN Range is 4.5V to 15V Support up to 2A Loading with up to 90% Efficiency Switching Frequency is 2MHz CH2/3 LV Step-Down Regulator : VIN Range is 2.7V to 5.5V Support up to 1A Loading, with up to 90% Efficiency Switching Frequency is 2MHz Linear Regulator : VIN Range is 2.7V to 5.5V Max Loading 0.5A Load Switch (LSW) : VIN Range is 2.7V to 5.5V Max Loading 0.5A Sequence Can be Controlled by Setting the Resistances of the SEQ Pin AEC-Q100 Grade 1 Qualified Marking Information 2R= : Product Code Applications 2R=YM DNN Industrial/Automotive Camera Module Car Infotainment YMDNN : Date Code Simplified Application Circuit Input Power VIN VDDA RT2070 VOUT1 SWI LX1 SWO FB1 VOUT1S VOUT1 PVD4 LDO for Sensor VOUT4 FB4 SCL SDA ENA Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 VOUT1 Load SW for Core PVD2 LX2 Step Down for I/F VOUT1 FB2 PVD3 LX3 VOUT1 Step Down for Logic FB3 PGOOD SEQ GND is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT2070 Pin Configurations Ordering Information RT2070 (TOP VIEW) SCL SDA VDDA FB1 NC LX1 Package Type QW : WQFN-24L 4x4 (W-Type) (Exposed Pad-Option 1) 24 23 22 21 20 19 Lead Plating System G : Green (Halogen Free and Pb Free) ENA NC VOUT4 PVD4 FB4 PVD2 Note : Richtek products are : RoHS compliant and compatible with the current require- Suitable for use in SnPb or Pb-free soldering processes. 1 18 2 17 3 15 25 5 14 6 13 7 8 9 10 11 12 LX2 PGOOD FB2 VOUT1S SEQ LX3 ments of IPC/JEDEC J-STD-020. 16 GND 4 VIN GND SWI SWO FB3 PVD3 WQFN-24L 4X4 Functional Pin Description Pin No. 1 Pin Name Pin Function ENA IC Enable Control Input. Hi Active. Internal pull-down resister (100k). NC No Internal Connection. 3 VOUT4 Output Voltage Regulation Node for LDO4. 4 PVD4 Power Input for LDO4. 5 FB4 Feedback Voltage Input for LDO4 6 PVD2 Power Input for Buck2. 7 LX2 Switch Node of Buck2. 8 PGOOD Buck1 to Buck 3, LDO4 and LSW PGOOD Output Node by Open Drain. Hi Active. 9 FB2 Feedback Voltage Input for Buck2. 10 VOUT1S HV Buck Output Voltage for OVP Detection. Input HV Buck (CH1) Output. 11 SEQ Power Sequence Selection. 12 LX3 Switch Node of Buck3. 13 PVD3 Power Input for Buck3. 14 FB3 Feedback Voltage Input for Buck3. 15 SWO Load Switch Output. 16 SWI Load Switch Input. 2, 20 17, GND 25 (Exposed Pad) IC Power Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum thermal dissipation and current flow. 18 VIN Power Input for Buck1. 19 LX1 Switch Node of Buck1. 21 FB1 22 VDDA Feedback Voltage Input for Buck1. IC Internal Analog Power Output 4.45V (typ.). Only 1F and SCL/SDA pull up resister can be connected. 23 SDA I2C Data Input / Output. 24 SCL I2C Clock Input. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Function Block Diagram VIN VDDA PVD2 VDDA VDDA Pre-Regulator VREF, IBIAS, OTP, OSC VDDA GND VIN VIN OVP VIN + VOUT1S VOUT1S PVD3 VDDA - VREF FB2 VREF VDDA GND GND FB1 GND VDDA + CH1 Sync. HV Step-Down LX1 LX2 - VIN CH2 Sync. LV Step-Down CH3 Sync. LV Step-Down VOUT1 OVP LX3 VDDA GND SWI Well Control GND Load Switch Control + SWO VDDA FB1 PGOOD FB2 PGOOD Control FB3 PVD4 CH4 LDO FB3 VREF FB4 GND SWO VOUT4 VDDA FB4 + VREF 2 I C Interface SDA SCL VDDA SEQ Sequence Control Enable Sequence Control ENA GND Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT2070 Operation The RT2070 is a highly-integrated solution for automotive systems, including a 1-CH HV step-down DC/DC converter, 2-CH LV step-down DC/DC converter and 1-CH LDO. The RT2070 application mechanism will be introduced in later sections. The power-on and power-off sequences are detected in the SEQ pin. Additionally, users control the next power on/off sequence by setting I2C registers from A01 to A12 when VDDA exists. When the ENA pin is at Hi level, the PMIC follows the power-on sequence to turn on channels. The IC turns on base and calibrates. Time is less than 500μs; during this time, the IC doesn't allow users to set I2C data. Pre-Regulator This HV regulator is designed to handle input operation range of 4.5V to 15V. The regulator provides low voltage power to supply the internal control circuits and avoid connecting any load from VDDA pin. In noisy environments, a 1μF decoupling capacitor must be connected between VDDA and GND. The I2C compatible interface remains fully functional if VIN and VDDA are present. If the VDDA is under the threshold voltage, all internal registers are reset to their default values. Input Over-Voltage Protection The device provides an input Over-Voltage Protection (OVP) once the input voltage exceeds 15.5V typically; the OVP function is started and all channels will be turned off after 5ms. If OVP is set to Hiccup, once the input voltage drops below the hysteresis 2V typically, the device is re-enabled and automatically reinstates the power-on sequence. This OVP feature can easily minimize the input overshoot. ENA : IC Enable Pin The ENA pin is a device enable input. Pulling the ENA pin to logic low that is typically less than the set threshold voltage 1.2V shuts the device down and it enters a low quiescent current state of about 20μA. The regulator starts switching again once the ENA pin voltage exceeds the threshold voltage of 2V. In addition, the ENA pin features an internal 100kΩ pull-low resistor. Power Good (PGOOD) Control The power good output is an open-drain output and needs to be connected to a voltage source with a pull-up 10kΩ resistor to avoid PGOOD floating. Each channel turns on according to power-on sequence. When the last channel reaches 90% of its target voltage, PMU (Power Management Unit) starts counting TPGOOD = 20ms (Power Good Delay time) then pulls PGOOD Hi until ENA is pulled low or any other protection happens. Over-Temperature Protection An Over-Temperature Protection (OTP) is featured in the device. The protection is triggered to force device shutdown when the junction temperature exceeds 160°C typically. If OTP is set to Hiccup once the junction temperature drops below the hysteresis 20°C typically, the device is re-enabled and automatically reinstated the power-on sequence. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Absolute Maximum Ratings (Note 1) Analog Base Input Voltage, VIN ---------------------------------------------------------------------------------------Control Output Voltage, PGOOD -------------------------------------------------------------------------------------Control Input Voltage, ENA --------------------------------------------------------------------------------------------HV Buck Power Switch (DC), LX1 ------------------------------------------------------------------------------------LV Buck Input Voltage, PVD2/3 ---------------------------------------------------------------------------------------LV Buck Power Switch (DC), LX2, LX3 ------------------------------------------------------------------------------LV Buck Power Switch (Spike Voltage <200ns), LX2, LX3 -----------------------------------------------------Other Pins ------------------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C −0.3V to 20V −0.3V to 6V −0.3V to 15V −0.3V to 15V −0.3V to 6V −0.3V to 6V −0.3V to 6V −0.3V to 6V WQFN-24L 4x4 -----------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) (Note 3) WQFN-24L 4x4, θJA ------------------------------------------------------------------------------------------------------WQFN-24L 4x4, θJC -----------------------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 4) HBM (Human Body Model) ---------------------------------------------------------------------------------------------MM (Machine Model) ----------------------------------------------------------------------------------------------------- 4.46W Recommended Operating Conditions 28°C/W 7°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 5) Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 150°C Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C Electrical Characteristics (VIN = 4.5V to 15V, TA = −40°C to 125°C, unless otherwise specified) Parameter Symbol Test Conditions VIN Operation Voltage Range Min Typ Max Unit 4.5 -- 15 V IQ VIN = 5V, LDOs, Bucks are ON with no load, LVBucks are in FCCM mode. 8 10 12 mA IQ_PSM VIN = 5V, LDOs, Bucks are ON with no load, LVBucks are in PSM mode. 600 1000 1200 A ISHD VIN = 5V, ENA = 0V, LDOs, Bucks are OFF. 2 7 20 A Over-Temperature Protection OTP 150 160 170 C OTP Hysteresis OTP_HYS 10 20 30 C OVP 15 15.5 16 V OVP_HYS 1.5 2 2.5 V Quiescent Current Shutdown Current (Note 6) VIN OVP (Hysteresis High) VIN OVP Hysteresis (Gap) (Note 7) Copyright © 2016 Richtek Technology Corporation. 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DS2070-00 March 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT2070 Parameter Symbol Test Conditions Min Typ Max Unit VIN UVLO2 UVLO2 3.8 3.9 4 V UVLO2 Hysteresis (Gap) UVLO2_HYS 0.4 0.5 0.6 V 4.25 4.45 4.65 V f SW 2 10% 2 2 +10% MHz Input Voltage Range VIN 4.5 -- 15 V Output Voltage Range VOUT 1.6 -- 5 V Feedback Voltage Accuracy FB1 0.8 1.5% 0.8 0.8 + 1.5% V FB1 Under-Voltage Protection FB1_UVP FB1 = FB1 x 0.5 (50%) 0.3 0.4 0.5 V Suggest Inductor LHVBuck 4.7 TA = 25°C CL1_T 40°C < TA < 125°C -3+ 15% 3+ 25% H CL1 -3 15% 3 25% 0 -- 5 A 1 -- 1 % 1 -- 1 % -- -- 20 mV VDDA Voltage Switching Frequency (CH1/CH2/CH3) CH1 HV-Buck Current Limit LX1 Leakage Current Ilx_leakage TA = 25°C, VIN = 6V, VOUT = 3.3V, Load = 0mA to 2000mA TA = 25°C, VIN = 5V to 15V, VOUT = 3.3V, Load = 1000mA Load Regulation Line Regulation Max Output Ripple VOUT = 3.3V, COUT = 22F 3 3 A P-MOSFET On-Resistance RDS(ON)_P VIN = 5V, ILX1 = 800mA 230 330 470 m N-MOSFET On-Resistance RDS(ON)_N VIN = 5V, ILX1 = 800mA 100 150 250 m Soft-Start Time Tr1 VOUT1 0.9 x VTarget, IOUT = 0mA 0.8 1 1.2 ms VIN = 5V, VOUT = 3.3V 870 970 1070 2.7 -- 5.5 V 60 85 120 m Discharge Resistance Load Switch (LSW) Supply Voltage Vswi MOSFET On-Resistance RDS(ON) SWI = 3.3V, IOUT = 500mA CLSW TA = 25°C 750 15% 750 750 + 15% CLSW_T 40°C < TA < 125°C 750 20% 750 750 + 20% Off Current Ioff_lsw ENA = Low 0 -- 0.15 A Quiescent Current Iq_lsw ENA = High, IOUT = 0mA 20 32 40 A Under-Voltage Threshold UVP_sw VSWI VSWO 0.7V 0.5 0.7 0.9 V Under-Voltage Threshold UVP_sw 0.7 0.85 1 V Soft-Start Time Tr_sw VSWO 0.85V VOUT 0.9 x VTarget, IOUT = 0mA VOUT1 = 3.3V, SWO = 3.3V 0.8 1 1.2 ms 400 440 480 Current Limit Discharge Resistance Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 mA is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Parameter Symbol Test Conditions Min Typ Max Unit 2.7 -- 5.5 V 1 0.8 1.5% -- 3.6 0.8 + 1.5% V Buck2 to Buck3 Input Voltage Range PVD2/PVD3 Output Voltage Range VOUT Feedback Voltage Accuracy FB2/3 IPVD Consumption Current IPVD_PSM Efficiency Peak Eff VIN = 5V, Buck is ON with no load FCCM mode. (per each buck) VIN = 5V, LVBuck is ON with no load in PSM mode.(per each buck) VOUT = 1.8V, VIN = 3.3V, ILOAD = 300mA Output Voltage Temperature Coefficient Suggest Inductor LBuck 0.8 V 4 5 6 mA 10 20 40 A -- 92 -- % -- ±100 -- ppm/C -- 2.2 -- H TA = 25°C 1300 1300 1300 15% + 15% CL2/3_T 40°C < TA < 125°C 1300 1300 1300 25% + 25% FB2/3 Under-Voltage Protection UVP2/3 FB2/3 = FB2/3 x 0.5 (50%) -- 0.4 -- V Output Transient Response Vpeak 0.1A to 0.5A at 10s, VOUT = 1.2V TA = 25°C, PVD2/3 = 3.3V, VOUT = 1.2V, Load = 0mA to 1000mA TA = 25°C, PVD2/3 = 3V to 5.5V, VOUT = 1.2V, Load = 1000mA COUT = 20F 4 -- 4 % 1 -- 1 % 1 -- 1 % -- -- 20 mV CL2/3 Current Limit Load Regulation Line Regulation Max Output Ripple mA P-MOSFET On-Resistance RDS(ON)_P PVD2/3 = 3.3V 180 270 360 m N-MOSFET On-Resistance RDS(ON)_N PVD2/3 = 3.3V 100 175 250 m Soft-Start Time Tr2/3 VOUT2/3 0.9 x VTarget, IOUT = 0mA 0.8 1 1.5 ms PVD2 = 3.3V, VOUT = 1.2V 5 6 7 PVD3 = 3.3V, VOUT = 1.8V 6 7 8 Discharge Resistance CH4 LDO Input Voltage for PVD4 PVD4 2.7 -- 5.5 V Output Voltage Range VOUT 1 -- 3.6 V Feedback Voltage Accuracy FB4 0.8 1.5% 0.8 0.8 + 1.5% V 750 + 15% 750 + 35% mA CL4 TA = 25°C CL4_T 40°C < TA < 125°C VDROP IOUT = 150mA, PVD4 = VOUT4 0.1V Current Limit Dropout Voltage (PVD4 VOUT4) Output Voltage Temperature Coefficient PVD4 = 3.3V Copyright © 2016 Richtek Technology Corporation. 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DS2070-00 March 2016 750 15% 750 30% 750 750 0.03 -- 0.15 V -- ±100 -- ppm/C is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT2070 Parameter Symbol Min Typ Max Unit 100 140 180 A 0 1 2 A 0 1 5 mV 0 0.1 1 % -- 85 -- mV -- -- 10 mV 0.2 0.3 0.4 V -- 60 -- dB VOUT4 0.9 x VTarget, IOUT = 0mA 0.8 1 1.2 ms PVD4 = 3.3V, VOUT = 2.7V 380 450 520 -- 200 -- mV 18 20 22 ms Logic-High 2 -- -- Logic-Low -- -- 0.5 70 -- 140 k SDA, SCLK Input High Level Threshold 0.7 x VDDA -- -- V SDA, SCLK Input Low Level Threshold -- -- 0.3 x VDDA V -- -- 400 kHz Supply Current Iq4 Shutdown Current Ioff4 Line Regulation LiR Load Regulation LoR Transient Response VOUT Max Output Ripple FB4 Under Voltage Protection Test Conditions IOUT = 0mA PVD4 = 3V to 5V, VOUT4 = 2.7V, Load = 100mA PVD4 = 3.3V, Load 10mA to 500mA 50AIOUTMAX / 2 (SR = 10mA / 1s) @COUT = 2.2F COUT = 2.2F FB4_UVP FB4 = 0.8V x 0.4 (40%) Feq = 1kHz, IOUT = 100mA, VOUT = 2.7V PSRR Soft-Start Time Tr4 Discharge Resistance Power Good Power Good Pull-Down Voltage PGOOD Power Good Delay Time TPGOOD PGOOD Current equal to 5mA Control ENA Input Voltage ENA Pull Down Resistor RLOW VIN = 5V, Temperature = 40C to 125C. V I2C SCLK Clock Rate f SCL Hold Time (Repeated) START Condition. After this period, the first clock pulse is generated tHD;STA 0.6 -- -- s LOW Period of the SCL Clock tLOW 1.3 -- -- s HIGH Period of the SCL Clock tHIGH 0.6 -- -- s 0.6 -- -- s Set-Up Time for a Repeated tSU;STA START Condition Data Hold Time tHD;DAT 0 -- 0.9 s Data Set-Up Time tSU;DAT 100 -- -- ns Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Parameter Symbol Test Conditions Min Typ Max Unit Set-Up Time for STOP Condition tSU;STO 0.6 -- Bus Free Time Between a STOP and START Condition tBUF 1.3 -- -- s Rise Time of Both SDA and SCL Signals tR 20 -- 300 ns Fall Time of Both SDA and SCL Signals tF 20 -- 300 ns SDA and SCL Output Low Sink Current IOL 2 -- -- mA SDA or SCL voltage = 0.4V s Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. The junction temperature(TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in watts) according to the formula : TJ = TA + (PD x θJA) where θJA (in °C/W) in the package thermal impedance. Another, PIN − PO = PD and PO = η x PIN PD = (1 / η − 1) x PO where PIN is the total input power and Po is the total output power. Note 4. Devices are ESD sensitive. Handling precaution is recommended. Note 5. The device is not guaranteed to function outside its operating conditions. Note 6. When OTP is set to Hiccup by I2C. Note 7. When VIN OVP is set to Hiccup by I2C Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT2070 Typical Application Circuit C1 1µF VIN C101 4.7µF L101 4.7µH VOUT1 3.3V C102 10µF R101 15k 22 VDDA PVD2 6 RT2070 18 VIN LX2 7 PVD3 13 10 VOUT1S VOUT1 3.3V 16 SWI VOUT4 2.7V C401 2.2µF R403 22.1k C404 470pF R404 9.31k R203 27k LX3 12 FB3 14 4 PVD4 VOUT1 3.3V C301 4.7µF L301 2.2µH VOUT3 1.2V 10µF x2 C302 C303 C304 220pF 15 SWO C3, C4 10µF x 2 C402 4.7µF C204 120pF R204 21.5k VOUT1 3.3V VOUT1 3.3V VOUT2 1.8V 10µF x2 C202 C203 FB2 9 R102 4.75k DSP 3.3V L201 2.2µH 19 LX1 21 FB1 C2 10µF VOUT1 3.3V C201 4.7µF VOUT1 R303 14k R304 28k 10k PGOOD 8 PGOOD VDDA 3 VOUT4 1k SDA 5 FB4 11 SEQ 10k 23 VDDA SDA 1k SCL ENA 24 SCL 1 ENA GND 17, 25 (Exposed Pad) If there is any CHx is not used that external components still must be existed and keep original application circuit. If LSW isn't used, user can remove C2, C3 and C4, but the SWI pin must connect to VOUT1 and floating the SWO pin. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Typical Operating Characteristics CH2 Buck Efficiency vs. Output Current 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) CH1 HV Buck Efficiency vs. Output Current 100 60 VIN VIN VIN VIN VIN VIN 50 40 30 20 10 = = = = = = 5V 6V 9V 10V 12V 15V VIN VIN VIN VIN VIN VIN 60 50 40 = = = = = = 2.7V 3.3V 3.6V 4.2V 5V 5.5V 30 20 10 VOUT = 3.3V, L = 4.7μH, COUT = 10μF x 2 VOUT = 1.8V, L = 2.2μH, COUT = 10μF x 2, FPWM 0 0 10 100 1000 10 10000 100 1000 Output Current (mA) Output Current (mA) CH3 Buck Efficiency vs. Output Current CH1 HV Buck Output Voltage vs. Output Current 3.36 100 90 Output Voltage (V) Efficiency (%) VIN VIN VIN VIN VIN VIN 3.35 80 70 60 VIN VIN VIN VIN VIN VIN 50 40 30 = = = = = = 2.7V 3.3V 3.6V 4.2V 5V 5.5V 20 3.34 3.33 = = = = = = 5V 6V 9V 10V 12V 15V 3.32 3.31 10 VOUT = 1.2V, L = 2.2μH, COUT = 10μF x 2, FPWM L = 4.7μH, COUT = 10μF x 2 3.30 0 10 100 0 1000 0.5 1 1.5 2 Load Current (A) Output Current (mA) CH2 Buck Output Voltage vs. Output Current CH3 Buck Output Voltage vs. Output Current 1.820 1.210 Output Voltage (V) Output Voltage (V) 1.208 1.818 1.816 1.814 VIN VIN VIN VIN VIN VIN 1.812 = = = = = = 2.7V 3.3V 3.6V 4.2V 5V 5.5V L = 2.2μH, COUT = 10μF x 2 1.810 1.206 1.204 1.202 VIN VIN VIN VIN VIN VIN 1.200 1.198 1.196 = = = = = = 2.7V 3.3V 3.6V 4.2V 5V 5.5V L = 2.2μH, COUT = 10μF x 2 1.194 0 200 400 600 800 Output Current (mA) Copyright © 2016 Richtek Technology Corporation. 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DS2070-00 March 2016 1000 0 200 400 600 800 1000 Output Current (mA) is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT2070 CH4 LDO Output Voltage vs. Output Current CH1 HV Buck Output Voltage vs. Input Voltage 2.710 3.36 3.35 2.700 Output Voltage (V) Output Voltage (V) 2.705 2.695 2.690 VIN VIN VIN VIN VIN VIN 2.685 2.680 2.675 = = = = = = 3V 3.3V 3.6V 4.2V 5V 5.5V 3.34 3.33 3.32 IOUT = 0mA IOUT = 500mA IOUT = 1000mA IOUT = 1500mA IOUT = 2000mA 3.31 COUT = 2.2μF 2.670 0 100 200 300 400 500 600 5 6 7 8 Output Current (mA) CH2 Buck Output Voltage vs. Input Voltage 10 11 12 13 14 15 CH3 Buck Output Voltage vs. Input Voltage 1.205 1.204 1.817 1.816 1.815 1.814 1.813 IOUT = 0mA IOUT = 200mA IOUT = 400mA IOUT = 600mA IOUT = 800mA IOUT = 1000mA 1.812 1.811 1.810 2.7 3 3.3 1.203 Output Voltage (V) Output Voltage (V) 9 Input Voltage (V) 1.818 1.202 1.201 1.200 IOUT = 0mA IOUT = 200mA IOUT = 400mA IOUT = 600mA IOUT = 800mA IOUT = 1000mA 1.199 1.198 1.197 1.196 L = 2.2μH, COUT = 10μF x 2 L = 2.2μH, COUT = 10μF x 2 1.195 3.6 3.9 4.2 4.5 4.8 5.1 2.7 5.4 3 3.3 Input Voltage (V) 3.6 3.9 4.2 4.5 4.8 5.1 5.4 Input Voltage (V) CH4 LDO Output Voltage vs. Input Voltage CH4 LDO Dropout Voltage vs. Load Current 2.698 0.12 125°C 2.696 0.10 2.694 Dropout Voltage (V) Output Voltage (V) L = 4.7μH, COUT = 10μF x 2 3.30 2.692 2.690 2.688 IOUT = 0mA IOUT = 100mA IOUT = 400mA IOUT = 600mA 2.686 2.684 90°C 0.08 25°C 0.06 −40°C 0.04 0.02 2.682 COUT = 2.2μF 2.680 0.00 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 Input Voltage (V) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 5.4 0 50 100 150 200 Load Current (mA) is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Load Switch Ron vs Temperature CH4 LDO PSRR 120 0 (mΩ) Load Switch Ron (mΩ) -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -90 100 80 60 40 20 PVD4 = 3.3V, VOUT4 = 2.7V, IOUT = 10mA -100 0 10 100 1000 10000 100000 1000000 -50 -25 0 Frequency (Hz) 25 50 75 100 125 Temperature (°C) Shutdown Current vs. Temperature CH1 HV Buck Frequency vs. Temperature 10 2200 2150 8 Frequency (kHz) Shutdown Current (μA)1 9 7 6 5 VIN = 13V VIN = 5V 4 3 2 2100 2050 2000 1950 1 VIN = 12V, VOUT1 = 3.3V, IOUT = 600mA ENA = 0V 0 1900 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) SEQ4 Power On Sequence SEQ4 Power Off Sequence 125 CH2 VOUT2 (1V/Div) CH2 VOUT2 (1V/Div) CH3 VOUT3 (1V/Div) CH3 VOUT3 (1V/Div) CH4 VOUT4 (1V/Div) CH4 VOUT4 (1V/Div) LSW SWO (1V/Div) LSW SWO (1V/Div) VIN = 12V Time (1ms/Div) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 VIN = 12V Time (5ms/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT2070 Applications Information The RT2070 is a highly integrated automotive system Power Management IC that contains 3-CH switching DC/ DC converters and one generic LDO and one load switch. CH1 : HV Step-Down DC/DC Converter CH1 is a HV step-down converter for LV DC/DC converter power. The current-mode PWM converter with integrated internal MOSFETs and compensation network operates at fixed frequency. The output voltage of CH1 is set by external feedback resistors, as expressed in the following equation : VOUT1 = (1 + R101 / R102) x VFB1 Where VFB1 is 0.8V typically and suggested value for R101 is 10k to 500k. CH2 : Synchronous Step-Down DC/DC Converter CH2 is a synchronous step-down converter for I/F power and it operates with typically 2MHz fixed frequency Pulse Width Modulation (PWM) at moderate to heavy load currents. At light load currents, the converter can automatically enter Power Save Mode and operates in PFM mode which can be set by I2C interface. The converter output voltage is externally adjustable using a resistor divider at FB2. The output voltage of CH2 is set by external feedback resistors, as expressed in the following equation : VOUT2 = (1 + R203 / R204) x VFB2 Where VFB2 is 0.8V typically and suggested value for R203 is 10k to 600k. CH3 : Synchronous Step-Down DC/DC Converter CH3 is suitable for logic power. The converter with integrated internal MOSFETs and compensation network operates at synchronous PSM or fixed frequency PWM current mode which can be set by the I2C interface. The output voltage of CH3 is set by external feedback resistors, as expressed in the following equation : VOUT3 = (1 + R303 / R304) x VFB3 Where VFB3 is 0.8V typically and suggested value for R303 is 10k to 600k. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 For CH2 and CH3, to improve control performance using a feedforward capacitor in parallel to R203 or R303 is recommended, the value for the feedforward capacitor can be calculated using below formula : 3.16 s For CH2, CFF = R203 3.16 s For CH3, CFF = R303 CH4 : Generic LDO CH4 is a low-dropout (LDO) voltage regulator which offers benefits of high input voltage and low-dropout voltage for sensor power. The output voltage of CH4 is set by external feedback resistors, as expressed in the following equation: VOUT4 = (1 + R403 / R404) x VFB4 Where VFB4 is 0.8V typically and suggested value for R403 is 5k to 500k. To improve control performance using a feedforward capacitor in parallel to R403 is recommended, the value for the feedforward capacitor can be calculated using below formula : 10.4 s CFF = R403 Load Switch : Load Switch The load switch for core power is equipped with soft-start control and current limit function. If LSW isn't used, user can remove C2, C3 and C4, but the SWI pin must connect to VOUT1 and floating the SWO pin. Power On/Off Control The register value will be recovered to default value as VIN plug in. In normal operation, users can set the power on/ off relative setting by I2C for next ENA power on. The RT2070 support 6 sets power on/off sequence selected by the SEQ pin. The sequence detection operation only work as VIN plug in. The RT2070 includes 6 sets power on/off sequence and the default value is decided by factory trim. In the RT2070, users can plan the next power on/off sequence by setting register A01/A02. The register value means the power on location, and “000” means this channel is power off. The RT2070 doesn't allow missing power on code or discrete code occurs. is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Output Voltage Setting SEQ0 to SEQ5 Soft-Start End Delay Time (A01.Bit [7:6]) Discharge Finish Delay Time (A02.Bit [7:6]) [00] [00] SEQX_LSW [2:0] LSW [001] SEQX_Buk2 [2:0] Buck2 [010] SEQX_Buk3 [2:0] Buck3 [011] SEQX_LDO [2:0] LDO4 [100] Note : The default value will be decided in factory trim. Define : [000] means channel always turn off. [001] means firstly turn on channel. ----[100] means the finally turn on channel. Example : In above setting, the power on sequence is as below : LSW (001) Buck2 (010) Buck3 (011) LDO4 (100). Normally Power ON/OFF Sequence In the RT2070, the HV Buck (CH1) always firstly turns on and on sequence of the other channels are decided by SEQ setting. The off sequence will follow first-on-last-off rule to turn off channels. Normal power on ENA Normal power off from CPU < 500µs ON_Td CH1 CH2 90% x FB1 ON_Td 1ms 1ms CH4 1ms LSW OFF_Td 90% x FB2 ON_Td 90% x SWO 1ms 10% x FB4 OFF_Td 10% x SWO 90% x FB3 TPGOOD 10% x FB1 10% x FB2 OFF_Td 90% x FB4 ON_Td 1ms CH3 OFF_Td 10% x FB3 PGOOD Note : ON_Td and OFF_Td time control by Register ON_Td <1:0> and OFF_Td <1:0>, default setting <00> = 0ms, and TPGOOD = 20ms Figure 1. Sequence Example : CH1 (Always First Turn On) CH2 CH4 LSW CH3 Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT2070 Abnormal Off When the abnormal event occurs, all channels turns off immediately. If users want to turn on again, users must pull ENA low to reset state then pull high to turn on again. Normal power on ENA IC can be return on again when ENA low one shut operation. Abnormal power off from CPU (When Protection Occur) < 500µs ON_Td 1ms CH1 < 500µs ON_Td 1ms ON_Td 90% x FB1 ON_Td 90% x FB1 90% x FB2 ON_Td ON_Td 90% x FB2 1ms 90% x FB4 ON_Td 1ms 90% x SWO 1ms 90% x FB3 1ms TPGOOD CH2 CH4 LSW CH3 1ms 90% x FB4 ON_Td 1ms 90% x SWO 1ms 90% x FB3 1ms TPGOOD PGOOD Note : ON_Td and OFF_Td time control by Register ON_Td <1:0> and OFF_Td <1:0> , default setting <00> = 0ms, and TPGOOD = 20ms Figure 2. Protection Example : Each Channel Shutdown at the Same Time When output channel to discharge over 64ms and ENA is keep in high level, the RT2070 will re-start and follow SEQ setting to power on. Normal Power OFF Sequence Hiccup Power ON Sequence 64ms ENA < 64ms CH1 CH2 VOUT2 can’t discharge completely fault release CH3 CH4 SWO Figure 3 Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 PMU On/Off Sequence Setting by SEQ The SEQ pull-down resistance is used to define power on/off sequence (SEQ1 to SEQ5). The RT2070 will do sequence detection as VIN plug in. Enable sequence will be executed when detection phase finish. If users don't change the sequence setting by I2C in register A01 to A12, the IC will follow default value to turn on IC set by factory trim. If there is any CHx is not used that external components still must be existed and keep original application circuit. SEQ RSEQ Range CH2 LSW CH3 CH4 SEQ1 LSW CH4 CH3 CH2 SEQ2 CH4 CH3 CH2 LSW SEQ3 CH2 CH3 LSW CH4 SEQ4 CH2 CH3 CH4 LSW SEQ5 LSW CH2 CH4 CH3 If VIN is smaller than 3.9V, all channels will be turned off after 32μs. Typical RSEQ SEQ0 Short to VDDA SEQ1 64k RSEQ 25k 39k SEQ2 16k RSEQ 6.8k 10k SEQ3 3.9k RSEQ 1.6k 2.4k SEQ4 Short to GND SEQ5 200k RSEQ 100k Next, VIN is larger than 4.4V, the system will be sequence turn on by setting. 160k Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 SEQ0 VIN UVLO2 Operation Sequence Control RESQ SEQ Users can plan the combination of six sequences (SEQ0 to SEQ5). is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT2070 Max Load of Every Channel Purpose RT2070 Peak Current Limit Max Loading (IOUT)* Condition (VIN VOUT) HV to LV CH1_HV Buck 3000mA 2000mA 5V 3.3V VI/O CH2_LV Buck 1300mA 900mA 3.3V 1.8V VCORE CH3_LV Buck 1300mA 1000mA 3.3V 1.2V VSENSOR CH4_LDO 750mA 500mA 3.3V 2.7V Load SW LSW 750mA 500mA 3.3V 3.3V * Buck converter Vin / Vout levels will affect the max loading Higher max loading current Higher step-down ratio (Vout/Vin) results in shorter switch on-time (Ton), hence lower peak switch current. Lower max loading current Lower step down ratio (Vin closer to Vout) results a lower differential inductor voltage, so the slope of the inductor current during the ramp-up period is reduced. V VIN VIN UVLO2 threshold 0.5V 3.9V (typ.) VOUT1 (HV_Buck Output) VOUT1 Other channels Others channels (CH2,CH3,CH4,LSW) T Normal Operation Note : 0.5V is hysteresis voltage. VIN UVLO2 Sequence On Normal Operation Figure 4. UVLO2 Diagram Protection Act UVLO2 Protection Action Hiccup Vth_R(V) 4.4 Vth_F(V) 3.9 Power On Confirm YES Detect Power Pin VIN *Hiccup : Recover automatically. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Flow Chart Power ON/OFF Operation Power OFF (ENA = Low) No Enable Detection Phase ENA = Hi Yes BASE ON E-Fuse Normal Read BASE Wake Up and V/I Calibration Phase V/I Auto Calibration SEQ Detection Phase SEQ Detection B No Confirm VIN > UVLO2 Confirm UVLO2 Yes Protection Function On A (All protection function is working during Power On Sequence) Power On Sequence Finish Power On Sequence Abnormal On No Yes PGOOD = L 20ms delay PGOOD = H ENA=Low No Power On/Off Yes Power Off Sequence Finish Power Off Sequence in 64ms C No D Yes Power OFF Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT2070 Flow Chart of Protection A No No VINOVP Check (VINOVP = Hi) OTP Check (OTP = Hi) Yes No No No UVLO2 Check (UVLO2 = Hi) No OTP_TypeSel = <1> (default = 1) Yes Yes UVP Check (UVP = Hi) Yes Yes Yes VINOVP_TypeSel = <1> (default = 1) OCP Check (OCP = Hi) Yes OCP_TdSel = <1> (default = 1) OCP = Hi keep 10ms No Latch-Off No PGOOD = L Yes No ENA = Low Hiccup D Yes PGOOD = L ENA = Low Yes C No Anyone Yes OTP / VINOVP/ UVLO2 Check All No B (OTP = VINOVP = UVLO2 = <0>) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 I2C Interface I2C slave address = 0110100 (7bits). I2C interface supports fast mode (bit rate up to 400kb/s). The write or read bit stream (N ≥ 1) is shown below : The RT2070 I2C interface bus power must be supplied by VDDA or equal potential node. If I2C interface isn't used, SDA and SCL must be connected to GND. The RT2070 Driven by Master S Start P Stop Sr Repeat Start Driven by Slave (RT2070) Read N bytes from RT2070 S Slave Address MSB 0 A Register Address A Sr Slave Address Data 1 Data 2 A Write N bytes to RT2070 Data N …… Register Address LSB A Assume Address = m R/W A P Data for Address = m + N - 1 MSB A LSB MSB Data for Address = m + 1 0 A Data for Address = m LSB MSB Slave Address LSB A Assume Address = m R/W S 1 Data 1 MSB A Data for Address = m LSB Data 2 Data for Address = m + 1 MSB LSB Data N …… A A P Data for Address = m + N - 1 I2C Waveform Information SDA tLOW tF tSU;DAT tR tF tHD;STA tSP tBUF tR SCL S tHD;STA tHD;DAT tHIGH Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 tSU;STA Sr tSU;STO P S is a registered trademark of Richtek Technology Corporation. www.richtek.com 21 RT2070 I2C Register Table Address Register Description Name Address Bit7 Bit6 Bit5 Function A00 0x00 Meaning Bit4 Bit3 Bit2 Bit1 Bit0 Buck Function Trim Reserved FPWM3 FPWM2 EnDis_ LDO EnDis_ buck3 EnDis_ buck2 Reserved Default 0 1 1 1 1 1 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define the Buck3 switching operation mode FPWM3 0 : Automatic PWM/PSM switching operation 1 : Force PWM Define the Buck2 switching operation mode FPWM2 0 : Automatic PWM/PSM switching operation 1 : Force PWM LDO power off discharge enable control EnDis_LDO 0 : Won't discharge when LDO power off 1 : Discharge when LDO power off Buck3 power off discharge enable control EnDis_buck3 0 : Won't discharge when Buck3 power off 1 : Discharge when Buck3 power off EnDis_buck2 0 : Won't discharge when Buck2 power off 1 : Discharge when Buck2 power off Buck2 power off discharge enable control Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 22 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Address Register Description Name Address Bit7 Bit6 Bit5 Function A01 0x01 Meaning Bit4 Bit3 Bit2 Bit1 Bit0 SEQ0 Trim ON_Td <1:0> SEQ0_Buk2 <2:0> SEQ0_LSW <2:0> Default 0 0 0 0 1 0 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define the interval between soft-start finish and the next channel enabled ON_Td <1:0> 11 : 2ms 10 : 1ms 01 : 0.5ms 00 : 0ms Define Buck2 power on sequence in SEQ0 (Note : every channel can't choose the same code except <000> in SEQ0 ) SEQ0_Buck2 <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Define LSW power on sequence in SEQ0 (Note : every channel can't choose the same code except <000> in SEQ0 ) SEQ0_LSW <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 23 RT2070 Address Register Description Name Address Bit7 Bit6 Bit5 Function A02 0x02 Meaning Bit4 Bit3 Bit2 Bit1 Bit0 SEQ0 Trim OFF_Td <1:0> SEQ0_LDO <2:0> SEQ0_Buk3 <2:0> Default 0 0 1 0 0 0 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define the interval between shut-down OK and the next channel disabled OFF_Td <1:0> 11 : 2ms 10 : 1ms 01 : 0.5ms 00 : 0ms Define Buck3 power on sequence in SEQ0 (Note : every channel can't choose the same code except <000> in SEQ0) SEQ0_Buck3 <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Define LDO power on sequence in SEQ0 (Note : every channel can't choose the same code except <000> in SEQ0) SEQ0_LDO <2:0> Address Register Description Name Address 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Bit7 Bit6 Bit5 Function A03 0x03 Meaning Bit4 Bit3 Bit2 Bit1 Bit0 SEQ1 Trim Reserved Reserved SEQ1_Buk2 <2:0> SEQ1_LSW <2:0> Default 0 0 1 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define Buck2 power on sequence in SEQ1 (Note : every channel can't choose the same code except <000> in SEQ1) SEQ1_Buck2 <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Define LSW power on sequence in SEQ1 (Note : every channel can't choose the same code except <000> in SEQ1) SEQ1_LSW <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 24 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Address Register Description Name Address Bit7 Bit6 Bit5 Function A04 0x04 Meaning Bit4 Bit3 Bit2 Bit1 Bit0 SEQ1 Trim Reserved Reserved SEQ1_LDO <2:0> SEQ1_Buk3 <2:0> Default 0 0 0 1 0 0 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define LDO power on sequence in SEQ1 (Note : every channel can't choose the same code except <000> in SEQ1) SEQ1_LDO <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Define Buck3 power on sequence in SEQ1 (Note : every channel can't choose the same code except <000> in SEQ1) SEQ1_Buck3 <2:0> Address Register Description Name Address 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Bit7 Bit6 Bit5 Function A05 0x05 Meaning Bit4 Bit3 Bit2 Bit1 Bit0 SEQ2 Trim Reserved Reserved SEQ2_Buk2 <2:0> SEQ2_LSW <2:0> Default 0 0 0 1 1 1 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define Buck2 power on sequence in SEQ2 (Note : every channel can't choose the same code except <000> in SEQ2) SEQ2_Buck2 <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Define LSW power on sequence in SEQ2 (Note : every channel can't choose the same code except <000> in SEQ2) SEQ2_LSW <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 25 RT2070 Address Register Description Name Address Bit7 Bit6 Bit5 Function A06 0x06 Meaning Bit4 Bit3 Bit2 Bit1 Bit0 SEQ2 Trim Reserved Reserved SEQ2_LDO <2:0> SEQ2_Buk3 <2:0> Default 0 0 0 0 1 0 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define LDO power on sequence in SEQ2 (Note : every channel can't choose the same code except <000> in SEQ2) SEQ2_LDO <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Define Buck3 power on sequence in SEQ2 (Note : every channel can't choose the same code except <000> in SEQ2) SEQ2_Buck3 <2:0> Address Register Description Name Address 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Bit7 Bit6 Bit5 Function A07 0x07 Meaning Bit4 Bit3 Bit2 Bit1 Bit0 SEQ3 Trim Reserved Reserved SEQ3_Buk2 <2:0> SEQ3_LSW <2:0> Default 0 0 0 0 1 0 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define Buck2 power on sequence in SEQ3 (Note : every channel can't choose the same code except <000> in SEQ3) SEQ3_Buck2 <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Define LSW power on sequence in SEQ3 (Note : every channel can't choose the same code except <000> in SEQ3) SEQ3_LSW <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 26 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Address Register Description Name Address Bit7 Bit6 Bit5 Function A08 0x08 Meaning Bit4 Bit3 Bit2 Bit1 Bit0 SEQ3 Trim Reserved Reserved SEQ3_LDO <2:0> SEQ3_Buk3 <2:0> Default 0 0 1 0 0 0 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define LDO power on sequence in SEQ3 (Note : every channel can't choose the same code except <000> in SEQ3) SEQ3_LDO <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Define Buck3 power on sequence in SEQ3 (Note : every channel can't choose the same code except <000> in SEQ3) SEQ3_Buck3 <2:0> Address Register Description Name Address 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Bit7 Bit6 Bit5 Function A09 0x09 Meaning Bit4 Bit3 Bit2 Bit1 Bit0 SEQ4 Trim Reserved Reserved SEQ4_Buk2 <2:0> SEQ4_LSW <2:0> Default 0 0 0 0 1 1 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define Buck2 power on sequence in SEQ4 (Note : every channel can't choose the same code except <000> in SEQ4) SEQ4_Buck2 <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Define LSW power on sequence in SEQ4 (Note : every channel can't choose the same code except <000> in SEQ4) SEQ4_LSW <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 27 RT2070 Address Register Description Name Address Bit7 Bit6 Bit5 Function A10 0x0A Meaning Bit4 Bit3 Bit2 Bit1 Bit0 SEQ4 Trim Reserved Reserved SEQ4_LDO <2:0> SEQ4_Buk3 <2:0> Default 0 0 0 1 1 0 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define LDO power on sequence in SEQ4 (Note : every channel can't choose the same code except <000> in SEQ4) SEQ4_LDO <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Define Buck3 power on sequence in SEQ4 (Note : every channel can't choose the same code except <000> in SEQ4) SEQ4_Buck3 <2:0> Address Register Description Name Address 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Bit7 Bit6 Bit5 Function A11 0x0B Meaning Bit4 Bit3 Bit2 Bit1 Bit0 SEQ5 Trim Reserved Reserved SEQ5_Buk2 <2:0> SEQ5_LSW <2:0> Default 0 0 0 1 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define Buck2 power on sequence in SEQ5 (Note : every channel can't choose the same code except <000> in SEQ5) SEQ5_Buck2 <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Define LSW power on sequence in SEQ5 (Note : every channel can't choose the same code except <000> in SEQ5) SEQ5_LSW <2:0> 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 28 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Address Register Description Name Address Bit7 Bit6 Bit5 Function A12 0x0C Meaning Bit4 Bit3 Bit2 Bit1 Bit0 SEQ5 Trim Reserved Reserved SEQ5_LDO <2:0> SEQ5_Buk3 <2:0> Default 0 0 0 1 1 1 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define LDO power on sequence in SEQ5 (Note : every channel can't choose the same code except <000> in SEQ5) SEQ5_LDO <2:0> SEQ5_Buck3 <2:0> Address Register Description Name Address A13 0x0D 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Define Buck3 power on sequence in SEQ5 (Note : every channel can't choose the same code except <000> in SEQ5) 100 : the last turn on 011 : the third turn on 010 : the second turn on 001 : the first turn on 000 : disable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function OTP/OVP Function Level Trim Meaning VINOVP_ VINOVP_TdSel OTP_ Reserved Reserved Reserved Reserved TypeSel <1:0> TypeSel Default 1 0 0 0 0 1 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define OTP protection operation mode. OTP_TypeSel 0 : Hiccup protection 1 : Latch-off protection Define OVP protection operation mode. VINOVP_TypeSel 0 : Hiccup protection 1 : Latch-off protection Define OVP deglitch time VINOVP_TdSel <1:0> 11 : 10ms 10 : 5ms 01 : 1ms 00 : 0ms Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 29 RT2070 Address Register Description Name Address Bit7 Bit6 Bit5 Function A14 0x0E Meaning Bit4 Bit3 Bit2 Bit1 Bit0 Buck2/3 Performance Trim Buck3MP_Cur <1:0> Buck3Drv <1:0> Buck2MP_Cur <1:0> Buck2Drv <1:0> Default 1 0 1 0 1 0 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Define the Buck3 Minimum Peak Current Level Buck3MP_Cur <1:0> 11 : Minimum Peak Current Level = 210mA 10 : Minimum Peak Current Level = 170mA 01 : Minimum Peak Current Level = 110mA 00 : Minimum Peak Current Level = 70mA Define Buck3 Driver ability Buck3Drv <1:0> 11 : stronger 10 : middle 01 : weaker 00 : weakest Define the Buck2 Minimum Peak Current Level Buck2MP_Cur <1:0> 11 : Minimum Peak Current Level = 210mA 10 : Minimum Peak Current Level = 170mA 01 : Minimum Peak Current Level = 110mA 00 : Minimum Peak Current Level = 70mA Define Buck2 Driver ability Buck2Drv <1:0> 11 : stronger 10 : middle 01 : weaker 00 : weakest Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 30 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Address Register Description Name Address Bit7 Bit6 Function A15 Meaning 0x0F Default Read/Write HVBuck_OSC <1:0> Err_Base Err_HVBuck Err_LSW Err_Buck2 Err_Buck3 Err_LDO Bit4 Bit3 Bit2 Bit1 Bit0 HVBuck fsw selection / Eerror information HVBuck_OSC <1:0> 1 1 R/W R/W Err_Base 0 R Err_ Err_LSW HVBuck 0 0 R R Err_ Buck2 0 Err_ Buck3 0 R R Err_LDO 0 R Define HVBuck switching frequency 11 : 2MHz 10 : 2MHz 01 : 1MHz 00 : 500kHz Mark Base protection happen, reset when ENA = <0> and Hiccup recycle to power on sequence 1 : Happen VINUVLO or VINOVP or OTP or sequence time too long 0 : Didn't happen VINUVLO, VINOVP, OTP and sequence time too long Mark HVBuck protection happen, reset when ENA = <0> and Hiccup recycle to power on sequence 1 : Happen HVBuck UVP or OCP 0 : Didn't happen HVBuck UVP and OCP Mark LSW protection happen, reset when ENA = <0> and Hiccup recycle to power on sequence 1 : Happen LSW UVP or OCP 0 : Didn't happen LSW UVP and OCP Mark Buck2 protection happen, reset when ENA = <0> and Hiccup recycle to power on sequence 1 : Happen Buck2 UVP or OCP 0 : Didn't happen Buck2 UVP and OCP Mark Buck3 protection happen, reset when ENA = <0> and Hiccup recycle to power on sequence 1 : Happen Buck3 UVP or OCP 0 : Didn't happen Buck3 UVP and OCP Mark LDO protection happen, reset when ENA = <0> and Hiccup recycle to power on sequence 1 : Happen LDO UVP or OCP 0 : Didn't happen LDO UVP and OCP Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 Bit5 is a registered trademark of Richtek Technology Corporation. www.richtek.com 31 RT2070 Address Register Description Name Address Function A16 Meaning 0x10 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Disable Normal Read / Reload default setting / Error function information DIS_NR RELOAD Reserved Err_ Err_OVP Err_OTP Err_UVP Err_OCP UVLO2 Default 0 0 0 0 0 0 0 0 Read/Write R/W R/W R R R R R R Disable Normal Read Control DIS_NR 1 : Didn't load normal read data while power on (ENA = Hi) again. Hold original register setting of sRG0x00 to sRG0x0E and sRG0x0F <7:6>. 0 : Enable normal read while power on (ENA = Hi), reset register sRG0x00 to sRG0x0E and sRG0x0F <7:6> Reload default register setting Control RELOAD Err_UVLO2 Err_OVP Err_OTP 1 : Reload normal read result into register table and can't write register when RELOAD = <1> 0 : register can be wrote Mark UVLO2 protection happen, reset when ENA = <0> or hiccup recycle to power on sequence 1 : Happen UVLO2 0 : Didn't happen UVLO2 MarkVINOVP protection happen, reset when ENA = <0> or hiccup recycle to power on sequence 1 : Happen VINOVP 0 : Didn't happen VINOVP Mark OTP protection happen, reset when ENA = <0> or hiccup recycle to power on sequence 1 : Happen OTP 0 : Didn't happen OTP Mark UVP protection happen, reset when ENA = <0> Err_UVP 1 : Happen UVP 0 : Didn't happen UVP Mark OCP protection happen, reset when ENA = <0> Err_OCP 1 : Happen OCP 0 : Didn't happen OCP Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 32 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 Protections List Protection Type Threshold (Typical Value) Mask Time Reset Method Hiccup protection, Restart if VIN > 4.4V and EN = Hi UVLO2 VIN < 3.9V 32s Disable all channels OVP VIN > 15.5V 5ms Latch-off protection, Disable all channels VIN < 13.5V, VDDA < 1.6V or EN = low OCP PMOS current > 3A 10ms Cycle-by-Cycle Latch-off protection, detection then VDDA < 1.6V or EN = low disable all channels UVP VOUT1 < VOUT1 x 0.5 (50%) No mask Disable all channels Latch-off protection, VDDA < 1.6V or EN = low VOUT1 OVP VOUT1 > 5.5V No mask Disable CH1 Hiccup Until fail event to be dissolved OCP PMOS current > 1.3A 10ms UVP VOUT2 < VOUT2 x 0.5 (50%) No mask Disable all channels OCP PMOS current > 1.3A UVP VOUT3 < VOUT3 x 0.5 (50%) No mask Disable all channels OCP PMOS current > 0.75A Disable all channels Latch-off protection, VDDA < 1.6V or EN = low UVP VOUT4 < VOUT4 x 0.4 (40%) No mask Disable all channels Latch-off protection, VDDA < 1.6V or EN = low Current Limit NMOS current > 0.75A No mask Disable all channels Latch-off protection, VDDA < 1.6V or EN = low VSWI - VSWO > 0.7V No mask Disable all channels Latch-off protection, VDDA < 1.6V or EN = low VSWO < 0.85V No mask Disable all channels Latch-off protection, VDDA < 1.6V or EN = low Temperature > 160°C Latch-off protection, EN = No mask Disable all channels High and Temperature < 140°C VIN CH1 Protection Method CH2 10ms CH3 10ms* Cycle-by-Cycle Latch-off protection, detection then VDDA < 1.6V or EN = low disable all channels Cycle-by-Cycle Latch-off protection, detection then VDDA < 1.6V or EN = low disable all channels CH4 LSW UVP Thermal Thermal Shutdown Latch-off protection, VDDA < 1.6V or EN = low Latch-off protection, VDDA < 1.6V or EN = low * When current limit is working, VOUT4 drops and UVP trigger less than 10ms. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 33 RT2070 Thermal Considerations Layout Consideration For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : For the best performance of the RT2070, the following PCB layout guidelines must be strictly followed. Place the input and output capacitors as close as possible to the input and output pins respectively for good filtering. Keep the main power traces as wide and short as possible. The switching node area connected to LX and inductor should be minimized for lower EMI. For recommended operating condition specifications, the maximum junction temperature is 150°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-24L 4x4 package, the thermal resistance, θJA, is Place the feedback components as close as possible to the FBx pin and keep these components away from the noisy devices. 28°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : Connect the GND and Exposed Pad to a strong ground plane for maximum thermal dissipation and noise protection. Directly connect the output capacitors to the feedback network of each channel to avoid bouncing caused by parasitic resistance and inductance from the PCB trace. PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. P D(MAX) = (150°C − 25°C) / (28°C/W) = 4.46W for WQFN-24L 4x4 package Maximum Power Dissipation (W)1 The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 5 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 5.0 Four-Layer PCB 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 125 150 Ambient Temperature (°C) Figure 5. Derating Curve of Maximum Power Dissipation Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 34 is a registered trademark of Richtek Technology Corporation. DS2070-00 March 2016 RT2070 LX should be connected to inductor by wide and short trace, keep sensitive components away from this trace. C102 R102 R101 VOUT1 C1 GND SCL SDA VDDA FB1 NC LX1 L101 C402 C404 VOUT4 R404 ENA NC VOUT4 GND VOUT1 PVD4 C401 FB4 VOUT1 PVD2 C201 Input/Output capacitors must be placed as close as possible to the Input/Output pins. GND 1 18 2 17 3 16 GND 4 15 25 5 6 14 13 7 8 9 10 11 12 LX2 GND PGOOD FB2 VOUT1S SEQ LX3 R403 GND C101 24 23 22 21 20 19 VIN GND C2 SWI VOUT1 SWO FB3 VOUT1 PVD3 C301 GND L301 L201 C3 SWO C304 R304 R303 C302 R204 C202 R203 C204 VOUT3 The exposed pad must be soldered to a large PCB and connected to GND for maximum thermal dissipation. VOUT2 Place the feedback components as close as possible to the FBx pin and keep away from noisy devices. Figure 6. PCB Layout Guide Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS2070-00 March 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 35 RT2070 Outline Dimension D2 D SEE DETAIL A L 1 E E2 e b A3 Symbol D2 E2 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A1 1 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.950 4.050 0.156 0.159 Option 1 2.400 2.500 0.094 0.098 Option 2 2.650 2.750 0.104 0.108 E 3.950 4.050 0.156 0.159 Option 1 2.400 2.500 0.094 0.098 Option 2 2.650 2.750 0.104 0.108 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 24L QFN 4x4 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 36 DS2070-00 March 2016