a FEATURES +5 V, 65 V Power Supplies Ultralow Power Dissipation (<0.5 mW) Low Leakage (<100 pA) Low On Resistance (<50 V) Fast Switching Times Low Charge Injection TTL/CMOS Compatible TSSOP Package APPLICATIONS Battery Powered Instruments Single Supply Systems Remote Powered Equipment +5 V Supply Systems Computer Peripherals such as Disk Drives Precision Instrumentation Audio and Video Switching Automatic Test Equipment Precision Data Acquisition Sample Hold Systems Communication Systems LC2MOS Precision 5 V Quad SPST Switches ADG661/ADG662/ADG663 FUNCTIONAL BLOCK DIAGRAM S1 S1 IN1 IN1 D1 S2 D1 S2 IN2 IN2 ADG661 D2 ADG662 S3 D2 S3 IN3 IN3 D3 S4 D3 S4 IN4 IN4 D4 D4 S1 IN1 D1 S2 IN2 ADG663 D2 S3 IN3 D3 S4 IN4 D4 SWITCHES SHOWN FOR A LOGIC "1" INPUT GENERAL DESCRIPTION The ADG661, ADG662 and ADG663 are monolithic CMOS devices comprising four independently selectable switches. These switches feature low, well-controlled on resistance and wide analog signal range, making them ideal for precision analog signal switching. They are fabricated using Analog Devices' advanced linear compatible CMOS (LC2MOS) process, which offers benefits of low leakage currents, ultralow power dissipation and low capacitance for fast switching speeds with minimum charge injection. The on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals. Fast switching speed coupled with high signal bandwidth also make the parts suitable for video signal switching. CMOS construction ensures ultralow power dissipation making the parts ideally suited for portable and battery powered instruments. The ADG661, ADG662 and ADG663 contain four independent SPST switches. The ADG661 and ADG662 differ only in that the digital control logic is inverted. The ADG661 switches are turned on with a logic low on the appropriate control input, while a logic high is required for the ADG662. The ADG663 has two switches with digital control logic similar to that of the ADG661, while the logic is inverted on the other two switches. Each switch conducts equally well in both directions when ON and has an input signal range that extends to the supplies. In the OFF condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action for use in multiplexer applications. Inherent in the design is low charge injection for minimum transients when switching the digital inputs. PRODUCT HIGHLIGHTS 1. +5 V Single Supply Operation The ADG661, ADG662 and ADG663 offer high performance, including low on resistance and wide signal range, fully specified and guaranteed with ± 5 V and +5 V supply rails. 2. Ultralow Power Dissipation CMOS construction ensures ultralow power dissipation. 3. Low RON 4. Break-Before-Make Switching This prevents channel shorting when the switches are configured as a multiplexer. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 ADG661/ADG662/ADG663–SPECIFICATIONS1 Dual Supply (V DD = +5 V 6 10%, VSS = –5 V 6 10%, GND = 0 V, unless otherwise noted) Parameter ANALOG SWITCH Analog Signal Range RON LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) +258C B Versions – 408C to +858C Units Test Conditions/Comments V Ω typ Ω max VD = –3.5 V to +3.5 V, IS = –10 mA; VDD = +4.5 V, VSS = –4.5 V ±5 nA typ nA max nA typ nA max nA typ nA max VDD = +5.5 V, VSS = –5.5 V VD = ± 4.5 V, VS = ± 4.5 V; Test Circuit 2 VD = ± 4.5 V, VS = ± 4.5 V; Test Circuit 2 VD = VS = ± 4.5 V; Test Circuit 3 2.4 0.8 V min V max ± 0.1 µA typ µA max VIN = VINL or VINH RL = 300 Ω, CL = 35 pF; VS = ± 3 V; Test Circuit 4 RL = 300 Ω, CL = 35 pF; VS = ± 3 V; Test Circuit 4 RL = 300 Ω, CL = 35 pF; VS1 = VS2 = +3 V; Test Circuit 5 VS = 0 V, RS = 0 Ω, CL = 10 nF; Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 8 f = 1 MHz f = 1 MHz f = 1 MHz VDD to VSS 30 38 ± 0.025 ± 0.1 ± 0.025 ± 0.1 ± 0.05 ± 0.2 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH 0.005 DYNAMIC CHARACTERISTICS2 tON 150 50 ± 2.5 ± 2.5 tOFF 55 Break-Before-Make Time Delay, tD (ADG663 Only) Charge Injection 80 ns typ ns max ns typ ns max ns typ 6 pC typ OFF Isolation 70 dB typ Channel-to-Channel Crosstalk 90 dB typ CS (OFF) CD (OFF) CD, CS (ON) 9 9 28 pF typ pF typ pF typ 275 120 POWER REQUIREMENTS VDD IDD +4.5/5.5 –4.5/5.5 0.0001 1 ISS 0.0001 1 V min/max V min/max µA typ µA max µA typ µA max VDD = +5.5 V, VSS = –5.5 V Digital Inputs = 0 V or 5 V NOTES 1 Temperature ranges are as follows: B Versions, –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. –2– REV. 0 ADG661/ADG662/ADG663 Single Supply (V DD = +5 V 6 10%, VSS = 0 V, GND = 0 V, unless otherwise noted) Parameter ANALOG SWITCH Analog Signal Range RON LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) +258C B Versions – 408C to +858C Units Test Conditions/Comments V Ω typ Ω max VD = 0 V to +3.5 V, IS = –10 mA; VDD = +4.5 V ±5 nA typ nA max nA typ nA max nA typ nA max VDD = +5.5 V VD = 4.5 V/1 V, VS = 1 V/4.5 V; Test Circuit 2 VD = 4.5 V/1 V, VS = 1 V/4.5 V; Test Circuit 2 VD = VS = +4.5 V/+1 V; Test Circuit 3 2.4 0.8 V min V max ± 0.1 µA typ µA max VIN = VINL or VINH 0 V to VDD 45 68 ± 0.025 ± 0.1 ± 0.025 ± 0.1 ± 0.05 ± 0.2 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH 0.005 DYNAMIC CHARACTERISTICS2 tON 250 75 ± 2.5 ± 2.5 tOFF 45 Break-Before-Make Time Delay, tD (ADG663 Only) Charge Injection 140 ns typ ns max ns typ ns max ns typ 12 pC typ OFF Isolation 70 dB typ Channel-to-Channel Crosstalk 90 dB typ CS (OFF) CD (OFF) CD, CS (ON) 9 9 28 pF typ pF typ pF typ RL = 300 Ω, CL = 35 pF; VS = +2 V; Test Circuit 4 RL = 300 Ω, CL = 35 pF; VS = +2 V; Test Circuit 4 RL = 300 Ω, CL = 35 pF; VS1 = VS2 = +2 V; Test Circuit 5 VS = 0 V, RS = 0 Ω, CL = 10 nF; Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 8 f = 1 MHz f = 1 MHz f = 1 MHz V min/max µA typ µA max VDD = +5.5 V Digital Inputs = 0 V or 5 V 400 100 POWER REQUIREMENTS VDD IDD +4.5/5.5 0.0001 1 NOTES 1 Temperature ranges are as follows: B Versions, –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. REV. 0 –3– ADG661/ADG662/ADG663 ABSOLUTE MAXIMUM RATINGS 1 Lead Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C (TA = +25°C unless otherwise noted) VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V Analog, Digital Inputs2 . . . . . . . . . . . VSS –2 V to VDD +2 V or 30 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C TSSOP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 115°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. ORDERING GUIDE Model Temperature Range Package Description Package Option ADG661BRU ADG662BRU ADG663BRU –40°C to +85°C –40°C to +85°C –40°C to +85°C 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP RU-16 RU-16 RU-16 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG661/ADG662/ADG663 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 ADG661/ADG662/ADG663 PIN CONFIGURATION IN1 1 16 IN2 D1 2 15 D2 S1 3 14 S2 13 VDD VSS 4 ADG661 ADG662 ADG663 TERMINOLOGY VDD VSS GND S D IN RON IS (OFF) ID (OFF) ID, IS (ON) VD (VS) CS (OFF) CD (OFF) CD, CS (ON) tON 12 NC TOP VIEW S4 6 (Not to Scale) 11 S3 GND 5 D4 7 10 D3 IN4 8 9 IN3 NC = NO CONNECT Table I. Truth Table (ADG661/ADG662) ADG661 In ADG662 In Switch Condition 0 1 1 0 ON OFF Table II. Truth Table (ADG663) Logic Switch 1, 4 Switch 2, 3 0 1 OFF ON ON OFF tOFF tD Crosstalk Off Isolation Charge Injection REV. 0 –5– Most positive power supply potential. Most negative power supply potential in dual supplies. In single supply applications, it may be connected to GND. Ground (0 V) Reference. Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input. Ohmic resistance between D and S. Source leakage current with the switch “OFF.” Drain leakage current with the switch “OFF.” Channel leakage current with the switch “ON.” Analog voltage on terminals D, S. “OFF” Switch Source Capacitance. “OFF” Switch Drain Capacitance. “ON” Switch Capacitance. Delay between applying the digital control input and the output switching on. Delay between applying the digital control input and the output switching off. “OFF” time or “ON” time measured between the 90% points of both switches, when switching from one address state to another. A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. A measure of unwanted signal coupling through an “OFF” switch. A measure of the glitch impulse transferred from the digital input to analog output during switching. ADG661/ADG662/ADG663 Typical Performance Characteristics 50 50 50 VDD = +5V VSS = –5V 40 30 30 30 20 +858C 20 RON – V 40 10 0 –5 –4 –3 –2 Figure 1. On Resistance as a Function of VD (VS) Dual Supplies Figure 2. On Resistance as a Function of VD (VS) for Different Temperatures 0 2 3 4 0 1 5 VD OR VS – DRAIN OR SOURCE VOLTAGE – V Figure 3. On Resistance as a Function of VD (VS) Single Supply 10 LEAKAGE CURRENT – nA 100mA 4 SW 10mA 1 SW 1mA I–, I+ 120 VDD = +5V VSS = –5V VDD = +5V VSS = –5V VS = 65V VD = 65V 1 OFF ISOLATION – dB 10mA VDD = +5V VSS = –5V 20 10 0 1 2 3 4 5 –5 –4 –3 –2 –1 0 VD OR VS – DRAIN OR SOURCE VOLTAGE – V –1 0 1 2 3 4 5 VD OR VS – DRAIN OR SOURCE VOLTAGE – V 1mA VDD = +5V VSS = 0V +258C VDD = +5V VSS = –5V 10 ISUPPLY TA = +25°C 40 RON – V RON – V TA = +258C ID (OFF) 0.1 ID (ON) 0.01 100 80 60 100nA IS (OFF) 10nA 0.001 10 100 10k 100k 1M 1k FREQUENCY – Hz 25 10M Figure 4. Supply Current vs. Input Switching Frequency 0.000 95 105 40 100 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 6. Off Isolation vs. Frequency 110 VDD = +5V VSS = –5V TA = +258C VDD = +5V VSS = –5V ID(ON) 100 ID(OFF) IS(OFF) –0.002 –0.004 –0.006 –5 –4 –3 –2 –1 0 1 2 3 4 5 VD OR VS – DRAIN OR SOURCE VOLTAGE Figure 7. Leakage Currents as a Function of VD (VS) CROSSTALK – dB LEAKAGE CURRENT – nA 0.002 45 55 65 75 85 TEMPERATURE – 8C Figure 5. Leakage Currents as a Function of Temperature 0.006 0.004 35 90 80 70 60 100 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 8. Crosstalk vs. Frequency –6– REV. 0 ADG661/ADG662/ADG663 Test Circuits IDS ID (OFF) IS (OFF) V1 S A S VS D D ID (ON) S A VD VS 3. On Leakage 2. Off Leakage VDD 0.1mF 3V VDD S VS D VIN ADG661 VIN ADG662 VOUT RL 300V IN 50% 50% 50% 50% 3V CL 35pF 90% 90% VOUT VSS GND 0.1mF VSS tON tOFF 4. Switching Times VDD 0.1mF 3V VIN VDD VS1 VS2 S1 D1 S2 VIN VOUT1 VOUT2 D2 RL2 300V IN1, IN2 GND 50% 0V RL1 300V 50% 90% 90% VOUT1 CL1 35pF 0V CL2 35pF VSS 90% VOUT2 90% 0V tD 0.1mF VSS tD 5. Break-Before-Make Time Delay VDD 3V VDD RS VS S D VOUT VIN CL 10nF IN VOUT GND VSS DVOUT QINJ = CL 3 DVOUT VSS 6. Charge Injection –7– A VD VS RON = V1/IDS 1. On Resistance REV. 0 D ADG661/ADG662/ADG663 APPLICATION Test Circuits (Continued) VDD 0.1mF VDD S D Due to switch and capacitor leakage, the voltage on the hold capacitor will decrease with time. The ADG661/ADG662/ ADG663 minimizes this droop due to its low leakage specifications. The droop rate is further minimized by the use of a polystyrene hold capacitor. The droop rate for the circuit shown is typically 15 µV/µs. VOUT RL 50V VS VIN IN VSS GND A second switch SW2, which operates in parallel with SW1, is included in this circuit to reduce pedestal error. Since both switches will be at the same potential, they will have a differential effect on the op amp OP07 which will minimize charge injection effects. Pedestal error is also reduced by the compensation network RC and CC. This compensation network also reduces the hold time glitch while optimizing the acquisition time. Using the illustrated op amps and component values, the pedestal error has a maximum value of 5 mV over the ± 3 V input range. The acquisition time is 2.5 ms while the settling time is 1.85 µs. 0.1mF VSS 7. Off Isolation VDD 0.1mF VDD S 50V D C3257–8–1/98 Figure 9 illustrates a precise, sample-and-hold circuit. An AD845 is used as the input buffer while the output operational amplifier is an OP07. During the track mode, SW1 is closed and the output VOUT follows the input signal VIN. In the hold mode, SW1 is opened and the signal is held by the hold capacitor CH. +5V VIN1 VS 2200pF VIN2 +5V SW1 D GND +5V NC S VIN VSS AD845 0.1mF VSS CHANNEL TO CHANNEL CROSSTALK = 20 3 LOG VS/VOUT D SW2 S D RC 75V CC 1000pF CH 2200pF OP07 VOUT –5V –5V ADG661 ADG662 ADG663 8. Channel-to-Channel Crosstalk –5V Figure 9. Accurate Sample-and-Hold OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead TSSOP (RU-16) 16 PRINTED IN U.S.A. 0.201 (5.10) 0.193 (4.90) 9 0.256 (6.50) 0.246 (6.25) RL 50V 0.177 (4.50) 0.169 (4.30) VOUT S 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0256 SEATING (0.65) PLANE BSC 0.0433 (1.10) MAX 0.0118 (0.30) 0.0075 (0.19) 8° 0° 0.0079 (0.20) 0.0035 (0.090) –8– 0.028 (0.70) 0.020 (0.50) REV. 0