REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing YY MM DD CHECKED BY 12-11-20 Phu H. Nguyen APPROVED BY Thomas M. Hess SIZE A REV AMSC N/A 4 CODE IDENT. NO. 5 6 7 8 9 10 11 12 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil/ TITLE MICROCIRCUIT, DIGITAL-LINEAR, CMOS 1.8 V TO 5.5 V, 2.5 Ω, 2:1 MUX/SPDT SWITCH, MONOLITHIC SILICON DWG NO. V62/12650 16236 PAGE 1 OF 12 5962-V028-13 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance CMOS 1.8 V to 5.5 V, 2.5 Ω, 2:1 Mux/SPDT switch microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12650 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 ADG719-EP Circuit function CMOS 1.8 V to 5.5 V, 2.5 Ω, 2:1 Mux/SPDT switch 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 6 JEDEC MO-178-AB X Package style Small Outline Transistor Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12650 PAGE 2 1.3 Absolute maximum ratings. 1/ VDD to GND ................................................................................... Analog, Digital inputs .................................................................... Peak current, S or D ...................................................................... Continuous current, S or D ............................................................ Operating temperature range: ....................................................... Storage temperature range ........................................................... Junction temperature ................................................................... Case outline X, θJA Thermal impedance ................................. Lead soldering: Reflow, Peak temperature ...................................................... Time at peak temperature ...................................................... ESD ............................................................................................ -0.3 V to +7.0 V -0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 2/ 100 mA (Pulsed at 1 ms, 10% duty cycle max) 30 mA -55°C to +125°C -65°C to 150°C 150°C 186.45 °C/W 3/ 260(+0/-5) °C 20 sec to 40 sec 1 kV 2. APPLICABLE DOCUMENTS JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 – Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 1/ 2/ 3/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Over voltages at IN, S, or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. Measured on a 4-layer board. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12650 PAGE 3 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Truth table. The truth table shall be as shown in figure 4. 3.5.5 Functional block diagram. The functional block diagram shall be as shown in figure 5. 3.5.6 On resistance. The On resistance shall be as shown in figure 6. 3.5.7 Off leakage. The Off leakage shall be as shown in figure 7. 3.5.8 On leakage. The On leakage shall be as shown in figure 8. 3.5.9 Switching times. The switching times shall be as shown in figure 9. 3.5.10 Break before make time delay, tD. The break before make time delay, tD shall be as shown in figure 10. 3.5.11 Off isolation. The Off isolation shall be as shown in figure 11. 3.5.12 Channel to Channel crosstalk. The Channel to Channel crosstalk shall be as shown in figure 12. 3.5.13 Bandwidth. The Bandwidth shall be as shown in figure 13. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12650 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions VDD = 5 V ±10%, GND = 0 V unless otherwise noted Limits +25°C Min Typ -55°C to +125°C Max Analog switch Analog signal range On Resistance Unit Min 0 RON VS = 0 V to VDD, IS = -10 mA See FIGURE 6 VS = 0 V to VDD, IS = -10 mA Typ Max VDD V Ω 2.5 4 On resistance match Δ RON between channels On resistance Flatness RFLAT(ON) VS = 0 V to VDD, IS = -10 mA Leakage current IS (Off) (VDD = 5.5 V) Source off leakage IS (Off) VS = 4.5 V/1 V, VD = 1 V/4.5 V; See FIGURE 7 Channel On leakage ID, IS (ON) VS = VD = 1 V or VS = VD = 4.5 V See FIGURE 8 Digital inputs Input high voltage VIH Input low voltage VIL Input current INL or INH VIN = VINL or VINH Dynamic characteristics 2/ tON RL = 300 Ω, CL 35 pF, VS = 3 V, See FIGURE 9 tOFF Break before Make time tD RL = 300 Ω, CL 35 pF, delay VS1 = VS2 = 3 V, See FIGURE 10 RL = 50 Ω, CL 5 pF, f = 10 MHz, See FIGURE 11 Off Isolation RL = 50 Ω, CL 5 pF, f = 1 MHz, See FIGURE 11 RL = 50 Ω, CL 5 pF, Channel to channel f = 10 MHz, See FIGURE 12 crosstalk RL = 50 Ω, CL 5 pF, f = 1 MHz, See FIGURE 12 Bandwith -3 dB RL = 50 Ω, CL 5 pF, See FIGURE 13 CS (Off) CD, CS (ON) Power requirements (VDD = 5.5 V, Digital inputs = 0 V or 5,5 V) IDD 0.1 7 0.4 Ω 0.75 1.5 Ω ±0.01 ±0.25 1 nA ±0.01 ±0.25 5 nA 2.4 0.005 7 3 8 V 0.8 ±0.1 µA 12 6 ns 1 -67 dB -87 -62 -82 200 MHz 7 27 pF 0.001 1.0 µA See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12650 PAGE 5 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions VDD = 3 V ±10%, GND = 0 V unless otherwise noted Limits +25°C Min Typ -55°C to +125°C Max Analog switch Analog signal range On Resistance 2/ Min Typ 0 RON VS = 0 V to VDD, IS = -10 mA See FIGURE 6 VS = 0 V to VDD, IS = -10 mA Max VDD V Ω 6 On resistance match Δ RON between channels On resistance Flatness RFLAT(ON) VS = 0 V to VDD, IS = -10 mA Leakage current IS (Off) (VDD = 3.3 V) Source off leakage IS (Off) VS = 3 V/1 V, VD = 1 V/3 V; See FIGURE 7 Channel On leakage ID, IS (ON) VS = VD = 1 V or VS = VD = 3 V See FIGURE 8 Digital inputs Input high voltage VIH Input low voltage VIL Input current INL or INH VIN = VINL or VINH Dynamic characteristics 2/ tON RL = 300 Ω, CL 35 pF, VS = 2 V, See FIGURE 9 tOFF Break before Make time tD RL = 300 Ω, CL 35 pF, delay VS1 = VS2 = 2 V, See FIGURE 10 RL = 50 Ω, CL 5 pF, f = 10 MHz, See FIGURE 11 Off Isolation RL = 50 Ω, CL 5 pF, f = 1 MHz, See FIGURE 11 RL = 50 Ω, CL 5 pF, Channel to channel f = 10 MHz, See FIGURE 12 crosstalk RL = 50 Ω, CL 5 pF, f = 1 MHz, See FIGURE 12 Bandwith -3 dB RL = 50 Ω, CL 5 pF, See FIGURE 13 CS (Off) CD, CS (ON) Power requirements (VDD = 5.5 V, Digital inputs = 0 V or 5,5 V) IDD 1/ Unit 12 0.4 0.1 Ω Ω 2.5 ±0.01 ±0.25 1 nA ±0.01 ±0.25 5 nA 2.0 V 0.8 ±0.1 0.005 10 4 8 µA 15 8 ns 1 -67 dB -87 -62 -82 200 MHz 7 27 pF 0.001 1.0 µA Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Guaranteed by design, not subject to production test. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12650 PAGE 6 Case X e b 6 PLS 6 5 4 E1 E 1 2 3 0°-10° PIN 1 INDEX AREA L L1 D DETAIL A SEE DETAIL A A c A2 SEATING PLANE A1 Symbol A A1 A2 b D Dimensions Millimeters Symbol Min Max Millimeters Min Max 0.90 0.05 0.95 0.30 2.80 1.50 1.70 2.60 3.00 0.95 BSC 0.35 0.55 0.60 BSC 1.30 0.15 1.45 0.50 3.00 E E1 e L L1 NOTES: 1. All linear dimensions are in millimeters. 2. Falls within JEDEC MO-15-AB3. FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12650 PAGE 7 Case outline X Terminal Terminal symbol number IN 6 VDD 5 GND 4 Terminal number 1 2 3 Terminal symbol S2 D S1 FIGURE 2. Terminal connections. Terminal Number Mnemonic 1 IN 2 VDD 3 GND 4 S1 5 D 6 S2 Case outline X Description Digital switch control pin. Most positive power supply pin. Ground (0 V) reference pin. Source terminal. Can be used as an input or output Drain terminal. Can be used as an input or output Source terminal. Can be used as an input or output FIGURE 3. Terminal function. Input IN Switch S1 Switch S2 0 1 On Off Off On FIGURE 4. Truth table S2 D S1 IN NOTES: 1. Switches shown for a logic 1 input. FIGURE 5. Functional block diagram. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12650 PAGE 8 I DS V1 S V D R ON S =V1/I DS FIGURE 6. On resistance. IS (OFF) S A V I D (OFF) D A V S D FIGURE 7. Off leakage. S V I D (ON) D A V S D FIGURE 8. On leakage. V 0.1 DD F V DD S D V R V S IN L 330 C OUT V IN 50% L 35 pF 90% V OUT GND t ON t OFF FIGURE 9. Switching times. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12650 PAGE 9 VDD 0.1 VS1 VS2 S1 F VDD D D2 S2 RL2 330 IN VIN VOUT CL2 35 pF V IN V OUT GND 50% 0V 50% 0V tD tD FIGURE 10. Break before make time delay, tD. VDD 0.1 F NETWORK ANALYZER 50 VDD S IN VS 50 D VIN RL GND VOUT 50 OFF ISOLATION=20 LOG VOUT VS FIGURE 11. Off isolation. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12650 PAGE 10 VDD 0.1 F NETWORK ANALYZER VOUT VDD S1 RL 50 S2 D R 50 50 IN GND VS CHANNEL-TO-CHANNEL VOUT CROSSTALK=20 LOG VS FIGURE 12. Channel to Channel crosstalk. VDD 0.1 F NETWORK ANALYZER 50 VDD S VS IN D VIN RL GND INSERTION LOSS=20 LOG VOUT 50 VOUT WITH SWITCH VOUT WITHOUT SWITCH FIGURE 13. Bandwidth. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12650 PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/12650-01XE 24355 ADG719SRJZ-EP-RL7 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 24355 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Analog Devices 1 Technology Way P.O. Box 9106 Norwood, MA 02062-9106 SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12650 PAGE 12