REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA 12-12-21 4 A REV 5 6 7 8 9 10 11 12 13 14 15 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil/ TITLE MICROCIRCUIT, LINEAR, LOW VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER, MONOLITHIC SILICON APPROVED BY CHARLES F. SAFFLE SIZE AMSC N/A 3 CODE IDENT. NO. DWG NO. V62/12624 16236 PAGE 1 OF 15 5962-V079-12 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low voltage 1:10 LVPECL with selectable input clock driver microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12624 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 Circuit function CDCLVP111-EP Low voltage 1:10 low voltage positive emitter coupled logic (LVPECL) with selectable input clock driver 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 32 JEDEC PUB 95 Package style See figure 1 Plastic quad flat pack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 2 1.3 Absolute maximum ratings. 1/ Supply voltage (VCC) (relative to VEE) ....................................................................... -0.3 V to 4.6 V Input voltage (VIN) ...................................................................................................... -0.3 V to VCC + 0.5 V Output voltage (VOUT) ............................................................................................... -0.3 V to VCC + 0.5 V Input current (IIN) ....................................................................................................... ±20 mA Negative supply voltage (VEE) (relative to VCC) ........................................................ -4.6 V to 0.3 V Sink/source current (IBB) ............................................................................................ -1 mA to 1 mA DC output current (IO) ................................................................................................ -50 mA Storage temperature range (TSTG) ............................................................................ -65°C to +150°C Maximum operating junction temperature (TJ) ........................................................... +150°C 1.4 Recommended operating conditions. 2/ Supply voltage (VCC) (relative to VEE) ....................................................................... 2.375 V to 3.8 V Operating junction temperature range (TJ) ................................................................ -55°C to +125°C 1/ 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 3 1.5 Package thermal impedance. Thermal metric Thermal resistance, junction-to-ambient 3/ Thermal resistance, junction-to-case (top) Symbol Test condition Limit Unit θJA 0 LFM 74 °C/W 150 LFM 66 °C/W 250 LFM 64 °C/W 500 LFM 61 °C/W 39 °C/W θJC 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 EIA/JEDEC 51-7 – – Registered and Standard Outlines for Semiconductor Devices High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. _______ 3/ According to JEDEC 51-7 standard. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VSUPPLY: VCC = 0 V, Temperature, TJ Device type Limits VEE = -2.375 V to -3.8 V, unless otherwise specified Supply internal current IEE Absolute value of current Output and internal supply current ICC All outputs terminated 50 Ω to IIN 01 -55°C, +25°C 01 Min Max 35 85 mA 385 mA 405 +125°C VCC – 2 V Input current -55°C to +125°C Includes pull up/pull down resistors, Unit -55°C to +125°C 01 -150 150 µA -55°C to +125°C 01 -1.45 -1.125 V -1.4 -1.1 VIH = VCC, VIL = VCC – 2V Internally generated bias voltage VBB VEE = -3 V to -3.8 V, IBB = -0.2 mA VEE = -2.375 V to -2.75 V, IBB = -0.2 mA High level input voltage (CLK_SEL) VIH -55°C to +125°C 01 -1.165 -0.88 V Low level input voltage (CLK_SEL) VIL -55°C to +125°C 01 -1.81 -1.475 V Input amplitude voltage VID Difference of input, |VIH – VIL| 2/ -55°C to +125°C 01 0.5 1.3 V VCM DC offset relative to VEE -55°C to +125°C 01 VEE +1 -0.3 V VOH IOH = -21 mA -55°C 01 -1.26 -0.85 V +25°C -1.2 -0.85 +125°C -1.15 -0.80 -1.85 -1.425 -1.85 -1.25 (CLKn, CLKn ) Common mode voltage (CLKn, CLKn ) High level output voltage Low level output voltage VOL +25°C IOL = -5 mA 01 -55°C, +125°C Differential output voltage swing VOD Terminated with 50 Ω to VCC – 2 V, see figure 4 -55°C to +125°C 01 400 V mV See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 5 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions VSUPPLY: VCC = 2.375 V to 3.8 V, Temperature, TJ Device type Limits VEE = 0 V, unless otherwise specified Supply internal current IEE Absolute value of current Output and internal supply current ICC All outputs terminated 50 Ω to VCC – 2 V Input current IIN -55°C to +125°C 01 -55°C, +25°C 01 Min Max 35 85 mA 385 mA 405 +125°C Includes pull up/pull down resistors, Unit -55°C to +125°C 01 -150 150 µA -55°C to +125°C 01 VCC -1.45 VCC -1.125 V VCC -1.4 VCC -1.1 VIH = VCC, VIL = VCC – 2V Internally generated bias voltage VBB VCC = -3 V to -3.8 V, IBB = -0.2 mA VCC = 2.375 V to 2.75 V, IBB = -0.2 mA High level input voltage (CLK_SEL) VIH -55°C to +125°C 01 VCC -1.165 VCC -0.88 V Low level input voltage (CLK_SEL) VIL -55°C to +125°C 01 VCC -1.81 VCC -1.475 V Input amplitude voltage VID Difference of input, |VIH – VIL| 2/ -55°C to +125°C 01 0.5 1.3 V VCM DC offset relative to VEE -55°C to +125°C 01 1 VCC -0.3 V VOH IOH = -21 mA -55°C 01 VCC -1.26 VCC -0.85 V +25°C VCC -1.2 VCC -0.85 +125°C VCC -1.15 VCC -0.80 (CLKn, CLKn ) Common mode voltage (CLKn, CLKn ) High level output voltage See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 6 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions VSUPPLY: VCC = 2.375 V to 3.8 V, Temperature, TJ Device type Limits Min Max VCC -1.85 VCC -1.425 VCC -1.85 VCC -1.25 VEE = 0 V, unless otherwise specified Low level output voltage VOL +25°C IOL = -5 mA 01 -55°C, +125°C Differential output voltage swing VOD Terminated with 50 Ω to VCC – 2 V, see figure 4 -55°C to +125°C Unit 01 400 V mV See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 7 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions VSUPPLY: VCC = 0 V, Temperature, TJ Device type VEE = -2.375 V to -3.8 V, unless otherwise specified or VSUPPLY: VCC = 2.375 V to 3.8 V, Limits Unit Min Max 200 355 ps VEE = 0 V, unless otherwise specified Differential propagation tpd -55°C to +125°C 01 delay CLKn, CLKn to all Q0, Q0 ..Q9, Q9 Output to output skew tsk(o) See figure 5 -55°C to +125°C 01 50 ps Additive phase jitter taj Integration bandwidth of 20 kHz to 20 MHz, fout = 200 MHz at 25°C -55°C to +125°C 01 < 0.8 ps Maximum frequency f(max) Functional up to 3.5 GHz, see figure 4 -55°C to +125°C 01 3500 MHz Output rise and fall time (20%, 80%) tr / tf See note 4 in figure 5 -55°C to +125°C 01 240 ps 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ VID minimum and maximum is required to maintain ac specifications, actual device function tolerates a minimum VID of 100 mV. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 8 Case X FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 9 Case X – continued. Dimensions Inches Symbol Millimeters Min Max Min Max A --- 0.062 --- 1.60 A1 0.053 0.057 1.35 1.45 A2 --- 0.009 --- 0.25 A3 b 0.001 MIN 0.009 c 0.05 MIN 0.017 0.25 0.005 NOM 0.45 0.13 NOM D/E 0.346 0.362 8.80 9.20 D1/E1 0.267 0.283 6.80 7.20 D2/E2 0.220 TYP 5.60 TYP e 0.031 BSC 0.80 BSC L 0.017 0.029 0.45 0.75 NOTES: 1. Controlling dimensions are inch, millimeter dimensions are given for reference only. FIGURE 1. Case outline - Continued. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 10 Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 VCC 17 Q6 2 CLK_SEL 18 Q6 3 CLK0 19 Q5 4 CLK 0 20 Q5 5 VBB 21 Q4 6 CLK1 22 Q4 7 CLK 1 23 Q3 8 VEE 24 Q3 9 VCC 25 VCC 10 Q9 26 Q2 11 Q9 27 Q2 12 Q8 28 Q1 13 Q8 29 Q1 14 Q7 30 Q0 15 Q7 31 Q0 16 VCC 32 VCC FIGURE 2. Terminal connections. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 11 Terminal symbol Description CLK0, CLK 0 Clock select. Used to select between CLK0 and CLK1 input pairs. Low voltage transistor-transistor logic (LVTTL) / low voltage complementary metal oxide semiconductor (LVCMOS) functionality compatible. Differential low voltage emitter coupled logic (LVECL) / LVPECL input pair CLK1, CLK 1 Differential LVECL/LVPECL input pair CLK_SEL LVECL/LVPECL clock outputs, these outputs provide low-skew copies of CLKn. LVECL/LVPECL complementary clock inputs, Q(9:0) Q (9:0) VBB these outputs provide copies of CLKn . Reference voltage output for single ended input operation. VCC Supply voltage. VEE Device ground or negative supply voltage in emitter coupled logic (ECL) mode. FIGURE 2. Terminal connections - continued. CLK_SEL Active clock input 0 CLK0, CLK0 1 CLK1, CLK1 FIGURE 3. Truth table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 12 FIGURE 4. Differential output voltage swing graph. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 13 NOTES: 1. Output skew tsk(0), is calculated as the greater of: the difference between the fastest and the slowest tPLHn (n = 0, 1, ..9) or the difference between the fastest and the slowest tPHLn (n = 0, 1,..9). 2. Part to part skew tsk(pp), is calculated as the greater of: the difference between the fastest and the slowest tPLHn (n = 0, 1,…9) across multiple devices or the difference between the fastest and the slowest tPHLn (n = 0, 1, …9) across multiple devices. 3. Typical values measured at ambient when clock input is 155.52 MHz for an integration bandwidth of 20 kHz to 5 MHz. 4. Input conditions: VCM = 1 V, VID = 0.5 V, and fIN = 1 GHz FIGURE 5. Waveform for calculating both output and part to part skew. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 14 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ 2/ Device manufacturer CAGE code Top side marking Vendor part number V62/12624-01XE 01295 LVP111MEP CDCLVP111MVFREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ For the most current package and ordering information, see the package option addendum at the end of the manufacturer’s data sheet. CAGE code 01295 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12624 PAGE 15