REVISIONS LTR DESCRIPTION DATE APPROVED A Table I, input offset voltage test; with TA = 25°C delete 9 mV and substitute 6 mV, with -40°C ≤ TA ≤ 125°C, delete 15 mV and substitute 8 mV. Table I, input offset current test, with -40°C ≤ TA ≤ 125°C delete 20 nA and substitute 2 nA. Table I, input bias current test, add -40°C ≤ TA ≤ 125°C, delete 50 nA and substitute 20 nA. Table I, large signal differential voltage amplification test, add -40°C ≤ TA ≤ 125°C for 15 V/mV min limit. Table I, common mode rejection ratio test, delete 75 dB and substitute 80 dB. Table I, slew rate at unity gain test, delete 5 V/µs and substitute 8 V/µs. - ro 13-01-09 C. SAFFLE Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen 11-11-07 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil/ TITLE MICROCIRCUIT, DIGITAL-LINEAR, LOW NOISE JFET INPUT OPERATIONAL AMPLIFIER, MONOLITHIC SILICON APPROVED BY Thomas M. Hess SIZE CODE IDENT. NO. A REV AMSC N/A DWG NO. V62/11621 16236 A PAGE 1 OF 10 5962-V032-13 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low noise JFET input operational amplifier microcircuit, with an operating temperature range of -40°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/11621 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 Circuit function TL074Q-EP Low noise JFET input operational amplifier 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 14 JEDEC PUB 95 Package style JEDEC MS-012 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/11621 PAGE 2 1.3 Absolute maximum ratings. 1/ Maximum supply voltage: 2/ VCC+ ................................................................................................................... 18 V VCC- ................................................................................................................... 18 V Maximum differential input voltage (VID) ................................................................ ±30 V 3/ Maximum input voltage (VI) .................................................................................... ±15 V 2/ 4/ Duration of output short circuit ............................................................................... Unlimited 5/ Maximum package thermal impedance (θJA) ........................................................ 86°C/W 6/ 7/ Maximum operating virtual junction temperature (TJ) ............................................ 150°C Storage temperature range (Tstg) .......................................................................... -65°C to 150°C 2. APPLICABLE DOCUMENTS JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 JEDEC STD 51-7 – – Registered and Standard Outlines for Semiconductor Devices High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http://www.jedec.org) 1/ 6/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC-. Differential voltages are at IN+, with respect to IN-. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable 7/ ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. The package thermal impedance is calculated in accordance with JESD 51-7. 2/ 3/ 4/ 5/ DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/11621 PAGE 3 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Symbol diagram. The symbol diagram shall be as shown in figure 3. 3.5.4 Schematic diagram. The schematic diagram shall be as shown in figure 4. 3.5.5 Unity gain amplifier. The unity gain amplifier shall be as shown in figure 5. 3.5.6 Gain of 10 inverting amplifier. The gain of 10 inverting amplifier shall be as shown in figure 6. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/11621 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol TA 4/ Conditions 2/ 3/ Input offset voltage VIO VO = 0, RS = 50 Ω 25°C Temperature coefficient of input offset voltage Input offset current αVIO VO = 0, RS = 50 Ω -40°C ≤ TA ≤ 125°C -40°C ≤ TA ≤ 125°C Input bias current IIO VO = 0 IIB VO = 0 Common mode input voltage range VICR Maximum peak output voltage swing VOM Large signal differential voltage amplification AVD Unity gain bandwidth B1 Input resistance CMRR Supply voltage rejection ratio (∆VCC±/∆VIO) kSVR Supply current (each amplifier) Crosstalk attenuation ICC VO1/VO2 Min Unit Max 6 8 18 typical µV/°C 100 pA -40°C ≤ TA ≤ 125°C 2 nA 25°C 200 pA -40°C ≤ TA ≤ 125°C 25°C 20 ±11 nA V RL = 10 kΩ 25°C ±12 V RL ≥ 10 kΩ -40°C ≤ TA ≤ 125°C ±12 RL ≥ 2 kΩ -40°C ≤ TA ≤ 125°C ±10 25°C 35 V/mV 15 3 typical MHz 25°C VO = ±10 V, RL ≥ 2 kΩ -40°C ≤ TA ≤ 125°C 25°C 12 25°C 10 VIC = VICmin, VO = 0, RS = 50 Ω VCC = ±9 V to ±15 V, VO = 0, RS = 50 Ω VO = 0, no load 25°C 80 Ω dB 25°C 80 dB 25°C 2.5 mA AVD = 100 25°C 120 typical dB VI = 10 V, RL = 2 kΩ, CL = 100 pF, see figure 1 25°C 8 VI = 10 V, RL = 2 kΩ, CL = 100 pF, see figure 1 f = 1 kHz RS = 20 Ω f = 10 Hz to 10 kHz 25°C 25°C 0.1 typical 20 typical 18 typical RS = 20 Ω, f = 1 kHz 25°C 0.01 typical VIrms = 6 V, AVD = 1, RL ≥ 2 kΩ, RS ≤ 1 kΩ, f = 1 kHz 25°C 0.003 typical ri Common mode rejection ratio Limits typical Operating characteristics. Slew rate at unity gain SR Rise time overshoot factor tr Equivalent input noise voltage Vn Equivalent input noise current Total harmonic distortion THD V/µs 4 typical µs % nV/√Hz µV pA/√Hz % 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ VCC± = ±15 V (unless otherwise noted). 3/ Input bias currents of an FET input operational amplifier are normal junction reverse currents, which are temperature sensitive. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as possible. 4/ All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/11621 PAGE 5 Case X e b .010(0.25) M 8 14 E E1 7 1 PIN 1 INDEX AREA D SEE DETAIL A A1 A c 0°-8° .004(0.10) GAGE PLANE SEATING PLANE .010(0.25) L DETAIL A Symbol A A1 b c D Inches Min Max .004 .012 .005 .337 .069 .010 .020 .010 .344 Dimensions Millimeters Symbol Min Max 0.10 0.31 0.13 8.55 1.75 0.25 0.51 0.25 8.75 E E1 e L Inches Min Max Millimeters Min Max .150 .157 .228 .244 .050 BSC .016 .050 3.80 4.00 5.80 6.20 1.27 BSC 0.40 1.27 NOTES: 1. All linear dimensions are in inches. 2. This drawing is subject to change without notice. 3. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006. inches (0.15 mm) each side. 4. Body width does not include interlead flash. Interlead flash shall not exceed .017 inche (0.43 mm) each side. 5. Reference JEDEC MS-012 variation AB. FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/11621 PAGE 6 Case outline X Device type 01 Terminal number 1 Terminal symbol 1OUT Terminal number 8 Terminal symbol 3OUT 2 1IN 9 3IN- 3 1IN+ 10 3IN- 4 VCC+ 11 VCC- 5 2IN+ 12 4IN+ 6 2IN- 13 4IN- 7 2OUT 14 4OUT FIGURE 2. Terminal connections. IN+ IN- + OUT - FIGURE 3. Symbol diagram. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/11621 PAGE 7 V CC+ IN+ 64 IN- 128 OUT 64 C1 18 pF 1080 V 1080 CC- FIGURE 4. Schematic diagram. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/11621 PAGE 8 - VO + VI CL RL = 100 pF =2k FIGURE 5. Unity gain amplifier. 10 k VI 1k + VO RL CL = 100 pF FIGURE 6. Gain of 10 inverting amplifier. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/11621 PAGE 9 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Top side marking Vendor part number V62/11621-01XE 01295 TL074QDR TL074QDREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 01295 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/11621 PAGE 10