OP262-DSCC: Military Data Sheet

REVISIONS
LTR
DESCRIPTION
DATE
Prepared in accordance with ASME Y14.24
APPROVED
Vendor item drawing
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PMIC N/A
PREPARED BY
Phu H. Nguyen
Original date of drawing
YY MM DD
CHECKED BY
12-10-12
Phu H. Nguyen
APPROVED BY
Thomas M. Hess
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DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
TITLE
MICROCIRCUIT, LINEAR, 15 MHz, RAIL TO
RAIL, DUAL OPERATIONAL AMPLIFIER,
MONOLITHIC SILICON
DWG NO.
V62/12639
16236
PAGE
1
OF
11
5962-V010-13
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance 15 MHz, rail to rail, dual operational amplifier
microcircuit, with an operating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/12639
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
01
Circuit function
OP262-EP
15 MHz. rail to rail, dual operational amplifier
1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter
Number of pins
JEDEC PUB 95
8
JEDEC MS-012-AA
X
Package style
Standard Small Outline Package
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
DLA LAND AND MARITIME
COLUMBUS, OHIO
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12639
PAGE
2
1.3 Absolute maximum ratings.
1/
Supply voltage .........................................................................................
Input voltage ............................................................................................
Differential input voltage ..........................................................................
Internal power dissipation SOIC (S) ........................................................
Output short circuit duration ....................................................................
Operating temperature range: .................................................................
Storage temperature range .....................................................................
Junction temperature range ....................................................................
Lead temperature range (Soldering, 10 sec) ..........................................
±6 V
±6 V
2/
±0.6 V
3/
Observe derating curves
Observe derating curves
-55°C to +125°C
-65°C to +150°C
-65°C to +150°C
300°C
1.4 Thermal characteristics.
Thermal resistance
Case outline
Case X
θJA 4/
157
θJC
56
Unit
°C/W
2. APPLICABLE DOCUMENTS
JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JEP95
–
Registered and Standard Outlines for Semiconductor Devices
(Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103
North 10th Street, Suite 240–S, Arlington, VA 22201.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
1/
2/
3/
4/
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
For supply voltage greater than 6 V, the input voltage is limited to less than or equal to the supply voltage.
For differential input voltages greater than 0.6 V, the input current should be limited to less than 5 mA to prevent degradation or
destruction of the input device.
θJA is specified for the worst case conditions, that is, θJA is specified for a device soldered in circuit board for SOIC package.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12639
PAGE
3
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as
specified in 1.3 and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12639
PAGE
4
TABLE I. Electrical performance characteristics. 1/
Test
Symbol
Limits
Test conditions
VS = 5.0 V, VCM = 0 V
TA = 25°C
unless otherwise specified
Min
Unit
Typ
Max
45
325
1
µV
mV
360
600
650
nA
±2.5
±25
±40
Input characteristics
Offset voltage
VOS
Input bias current
IS
Input offset current
IOS
Input voltage range
Common mode rejection
VCM
CMRR
Large signal voltage gain
AVO
-55°C ≤ TA ≤ +125°C
-55°C ≤ TA ≤ +125°C
-55°C ≤ TA ≤ +125°C
0
70
0 V ≤ VCM ≤ 4.0 V, -55°C ≤ TA ≤ +125°C
RL = 2 kΩ, 0.5 V ≤ VOUT ≤ 4.5 V
RL = 10 kΩ, 0.5 V ≤ VOUT ≤ 4.5 V
2/
Bias current drift
Output characteristics
Output voltage swing high
V/mV
ΔVOS/ΔT
1
µV/°C
ΔIB/ΔT
250
pA/°C
4.95
4.99
V
4.85
4.94
14
65
±80
±30
VOH
Output voltage swing low
VOL
Short circuit current
Maximum output current
Power supply
ISC
IOUT
Power supply rejection ratio
V
dB
30
88
65
40
RL = 10 kΩ, -55°C ≤ TA ≤ +125°C
Offset voltage drift
4
110
PSRR
IL = 250 µA, -55°C ≤ TA ≤ +125°C
IL = 5 mA
IL = 250 µA, -55°C ≤ TA ≤ +125°C
IL = 5 mA
Short to ground
VS = 2.7 V to 7 V
50
150
mA
120
-55°C ≤ TA ≤ +125°C
VOUT = 2.5 V
mV
dB
90
500
700
850
µA
Supply current/Amplifier
ISY
Dynamic performance
Slew rate
Settling time
Gain bandwidth product
Phase margin
SR
tS
GBP
1 V ≤ VOUT ≤ 4 V, RL = 10 kΩ
To 0.1%, AV = -1, VO = 2 V step
10
540
15
61
V/µs
ns
MHz
Degrees
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.5
9.5
0.4
µV p-p
nV/√Hz
pA/√Hz
Noise performance
Voltage noise
Voltage noise density
Current noise density
-55°C ≤ TA ≤ +125°C
ᵩm
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12639
PAGE
5
TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Test conditions
VS = 3.0 V, VCM = 0 V
TA = 25°C
unless otherwise specified
Limits
Min
Unit
Typ
Max
50
325
1
600
±25
2
Input characteristics
Offset voltage
VOS
Input bias current
Input offset current
Input voltage range
Common mode rejection
IS
IOS
VCM
CMRR
Large signal voltage gain
AVO
-55°C ≤ TA ≤ +125°C
360
±2.5
0
70
0 V ≤ VCM ≤ 4.0 V, -55°C ≤ TA ≤ +125°C
RL = 2 kΩ, 0.5 V ≤ VOUT ≤ 2.5 V
RL = 10 kΩ, 0.5 V ≤ VOUT ≤ 2.5 V
20
110
20
30
µV
mV
nA
V
dB
V/mV
Output characteristics
Output voltage swing high
VOH
Output voltage swing low
VOL
IL = 250 µA
IL = 5 mA
IL = 250 µA
IL = 5 mA
2.95
2.85
2.99
2.93
14
66
V
50
150
mV
Power supply
Power supply rejection ratio
PSRR
VS = 2.7 V to 7 V
110
-55°C ≤ TA ≤ +125°C
VOUT = 1.5 V
dB
60
500
650
850
µA
Supply current/Amplifier
ISY
Dynamic performance
Slew rate
Settling time
Gain bandwidth product
Phase margin
SR
tS
GBP
RL = 10 kΩ
To 0.1%, AV = -1, VO = 2 V step
10
575
15
59
V/µs
ns
MHz
Degrees
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.5
9.5
0.4
µV p-p
nV/√Hz
pA/√Hz
Noise performance
Voltage noise
Voltage noise density
Current noise density
-55°C ≤ TA ≤ +125°C
ᵩm
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12639
PAGE
6
TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Limits
Test conditions
VS = ±5.0 V, VCM = 0 V
TA = 25°C
unless otherwise specified
Min
Unit
Typ
Max
25
325
1
µV
mV
260
500
650
nA
±2.5
±25
±40
Input characteristics
Offset voltage
VOS
Input bias current
IS
Input offset current
IOS
Input voltage range
Common mode rejection
VCM
CMRR
Large signal voltage gain
AVO
-55°C ≤ TA ≤ +125°C
-55°C ≤ TA ≤ +125°C
-55°C ≤ TA ≤ +125°C
-4.9 V ≤ VCM ≤ +4.0 V, -55°C ≤ TA ≤ +125°C
RL = 2 kΩ, -4.5 V ≤ VOUT ≤ +4.5 V
RL = 10 kΩ, -4.5 V ≤ VOUT ≤ 4.5 V
-55°C ≤ TA ≤ +125°C
Long term offset voltage
Offset voltage drift 2/
Bias current drift
Output characteristics
3/
Output voltage swing high
Output voltage swing low
Short circuit current
Maximum output current
Power supply
Power supply rejection ratio
-5
70
75
25
VOS
ΔVOS/ΔT
ΔIB/ΔT
VOH
VOL
ISC
IOUT
PSRR
Supply current/Amplifier
ISY
Supply voltage range
Dynamic performance
Slew rate
Settling time
Gain bandwidth product
Phase margin
VS
+4
110
35
120
µV/°C
pA/°C
4.95
4.99
V
4.85
4.94
-4.99
IL = 250 µA, -55°C ≤ TA ≤ +125°C
IL = 5 mA
Short to ground
-4.94
±80
±30
VS = ±1.35 V to ±6 V
-4.95
-4.85
mA
110
-55°C ≤ TA ≤ +125°C
VOUT = 0 V
µV
1
250
dB
60
650
-55°C ≤ TA ≤ +125°C
VOUT = 0 V
550
-55°C ≤ TA ≤ +125°C
SR
tS
GBP
V/mV
600
IL = 250 µA, -55°C ≤ TA ≤ +125°C
IL = 5 mA
V
dB
3.0 (±1.5)
-4 V ≤ VOUT ≤ +4 V, RL = 10 kΩ
To 0.1%, AV = -1, VO = 2 V step
800
1.15
775
1
12 (±6)
13
475
15
64
ᵩm
µA
mA
µA
mA
V/µs
ns
MHz
Degrees
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12639
PAGE
7
TABLE I. Electrical performance characteristics - Continued. 1/
Test
Noise performance
Voltage noise
Voltage noise density
Current noise density
1/
2/
3/
Symbol
en p-p
en
in
Limits
Test conditions
VS = ±5.0 V, VCM = 0 V
TA = 25°C
unless otherwise specified
Min
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
Typ
Unit
Max
0.5
9.5
0.4
µV p-p
nV/√Hz
pA/√Hz
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not
necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
Offset voltage drift is the average of the -55°C to +25°C delta and the +25°C to +125°C delta.
Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125°C, with a LTPD of 1.3.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12639
PAGE
8
Case X
e
b
8
5
0°-8°
E
1
E1
4
L
D
DETAIL A
SEE
DETAIL A
A1
A
Symbol
A
A1
b
c
D
c
SEATING
PLANE
Millimeters
Min
Max
Dimensions
Inches
Symbol
Min
Max
1.35
0.10
0.31
0.17
4.80
.053
.004
.012
.006
.189
1.75
0.25
0.51
0.25
5.00
.068
.009
.020
.009
.197
E
E1
e
L
Millimeters
Min
Max
Min
Inches
Max
3.80
4.00
5.80
6.20
1.27 BSC
0.40
1.27
.149
.157
.228
.244
.050 BSC
.015
.050
NOTES:
1. Controlling dimensions are in millimeters; inch dimensions are rounded-off millimeter equivalents for reference only and are not
appropriate for use in design.
2. Falls within JEDEC MS-012-AA.
FIGURE 1. Case outline.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12639
PAGE
9
Case outline X
Terminal
Terminal
symbol
number
Terminal
number
Terminal
symbol
1
2
3
OUT A
-IN A
+IN A
8
7
6
V+
OUT B
4
V-
5
+IN B
-IN B
FIGURE 2. Terminal connections.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12639
PAGE
10
4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of
present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current
sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
V62/12639-01XE
24355
Vendor part number
OP262TRZ-EP-R7
OP262TRZ-EP
1/ The vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.
CAGE code
24355
DLA LAND AND MARITIME
COLUMBUS, OHIO
Source of supply
Analog Devices
1 Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12639
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